Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. |
| 3 | * |
| 4 | * Author: Shlomi Gridish <gridish@freescale.com> |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 5 | * Li Yang <leoli@freescale.com> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 6 | * |
| 7 | * Description: |
| 8 | * QE UCC Gigabit Ethernet Driver |
| 9 | * |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
| 13 | * option) any later version. |
| 14 | */ |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/errno.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/stddef.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/netdevice.h> |
| 22 | #include <linux/etherdevice.h> |
| 23 | #include <linux/skbuff.h> |
| 24 | #include <linux/spinlock.h> |
| 25 | #include <linux/mm.h> |
| 26 | #include <linux/ethtool.h> |
| 27 | #include <linux/delay.h> |
| 28 | #include <linux/dma-mapping.h> |
| 29 | #include <linux/fsl_devices.h> |
| 30 | #include <linux/ethtool.h> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 31 | #include <linux/mii.h> |
| 32 | |
Kim Phillips | a4f0c2c | 2006-11-15 12:29:35 -0600 | [diff] [blame] | 33 | #include <asm/of_platform.h> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 34 | #include <asm/uaccess.h> |
| 35 | #include <asm/irq.h> |
| 36 | #include <asm/io.h> |
| 37 | #include <asm/immap_qe.h> |
| 38 | #include <asm/qe.h> |
| 39 | #include <asm/ucc.h> |
| 40 | #include <asm/ucc_fast.h> |
| 41 | |
| 42 | #include "ucc_geth.h" |
| 43 | #include "ucc_geth_phy.h" |
| 44 | |
| 45 | #undef DEBUG |
| 46 | |
Andy Gospodarek | d5b2069 | 2006-09-11 17:39:18 -0400 | [diff] [blame] | 47 | #define DRV_DESC "QE UCC Gigabit Ethernet Controller version:Sept 11, 2006" |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 48 | #define DRV_NAME "ucc_geth" |
| 49 | |
| 50 | #define ugeth_printk(level, format, arg...) \ |
| 51 | printk(level format "\n", ## arg) |
| 52 | |
| 53 | #define ugeth_dbg(format, arg...) \ |
| 54 | ugeth_printk(KERN_DEBUG , format , ## arg) |
| 55 | #define ugeth_err(format, arg...) \ |
| 56 | ugeth_printk(KERN_ERR , format , ## arg) |
| 57 | #define ugeth_info(format, arg...) \ |
| 58 | ugeth_printk(KERN_INFO , format , ## arg) |
| 59 | #define ugeth_warn(format, arg...) \ |
| 60 | ugeth_printk(KERN_WARNING , format , ## arg) |
| 61 | |
| 62 | #ifdef UGETH_VERBOSE_DEBUG |
| 63 | #define ugeth_vdbg ugeth_dbg |
| 64 | #else |
| 65 | #define ugeth_vdbg(fmt, args...) do { } while (0) |
| 66 | #endif /* UGETH_VERBOSE_DEBUG */ |
| 67 | |
| 68 | static DEFINE_SPINLOCK(ugeth_lock); |
| 69 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 70 | static struct ucc_geth_info ugeth_primary_info = { |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 71 | .uf_info = { |
| 72 | .bd_mem_part = MEM_PART_SYSTEM, |
| 73 | .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES, |
| 74 | .max_rx_buf_length = 1536, |
| 75 | /* FIXME: should be changed in run time for 1G and 100M */ |
| 76 | #ifdef CONFIG_UGETH_HAS_GIGA |
| 77 | .urfs = UCC_GETH_URFS_GIGA_INIT, |
| 78 | .urfet = UCC_GETH_URFET_GIGA_INIT, |
| 79 | .urfset = UCC_GETH_URFSET_GIGA_INIT, |
| 80 | .utfs = UCC_GETH_UTFS_GIGA_INIT, |
| 81 | .utfet = UCC_GETH_UTFET_GIGA_INIT, |
| 82 | .utftt = UCC_GETH_UTFTT_GIGA_INIT, |
| 83 | #else |
| 84 | .urfs = UCC_GETH_URFS_INIT, |
| 85 | .urfet = UCC_GETH_URFET_INIT, |
| 86 | .urfset = UCC_GETH_URFSET_INIT, |
| 87 | .utfs = UCC_GETH_UTFS_INIT, |
| 88 | .utfet = UCC_GETH_UTFET_INIT, |
| 89 | .utftt = UCC_GETH_UTFTT_INIT, |
| 90 | #endif |
| 91 | .ufpt = 256, |
| 92 | .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET, |
| 93 | .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, |
| 94 | .tenc = UCC_FAST_TX_ENCODING_NRZ, |
| 95 | .renc = UCC_FAST_RX_ENCODING_NRZ, |
| 96 | .tcrc = UCC_FAST_16_BIT_CRC, |
| 97 | .synl = UCC_FAST_SYNC_LEN_NOT_USED, |
| 98 | }, |
| 99 | .numQueuesTx = 1, |
| 100 | .numQueuesRx = 1, |
| 101 | .extendedFilteringChainPointer = ((uint32_t) NULL), |
| 102 | .typeorlen = 3072 /*1536 */ , |
| 103 | .nonBackToBackIfgPart1 = 0x40, |
| 104 | .nonBackToBackIfgPart2 = 0x60, |
| 105 | .miminumInterFrameGapEnforcement = 0x50, |
| 106 | .backToBackInterFrameGap = 0x60, |
| 107 | .mblinterval = 128, |
| 108 | .nortsrbytetime = 5, |
| 109 | .fracsiz = 1, |
| 110 | .strictpriorityq = 0xff, |
| 111 | .altBebTruncation = 0xa, |
| 112 | .excessDefer = 1, |
| 113 | .maxRetransmission = 0xf, |
| 114 | .collisionWindow = 0x37, |
| 115 | .receiveFlowControl = 1, |
| 116 | .maxGroupAddrInHash = 4, |
| 117 | .maxIndAddrInHash = 4, |
| 118 | .prel = 7, |
| 119 | .maxFrameLength = 1518, |
| 120 | .minFrameLength = 64, |
| 121 | .maxD1Length = 1520, |
| 122 | .maxD2Length = 1520, |
| 123 | .vlantype = 0x8100, |
| 124 | .ecamptr = ((uint32_t) NULL), |
| 125 | .eventRegMask = UCCE_OTHER, |
| 126 | .pausePeriod = 0xf000, |
| 127 | .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1}, |
| 128 | .bdRingLenTx = { |
| 129 | TX_BD_RING_LEN, |
| 130 | TX_BD_RING_LEN, |
| 131 | TX_BD_RING_LEN, |
| 132 | TX_BD_RING_LEN, |
| 133 | TX_BD_RING_LEN, |
| 134 | TX_BD_RING_LEN, |
| 135 | TX_BD_RING_LEN, |
| 136 | TX_BD_RING_LEN}, |
| 137 | |
| 138 | .bdRingLenRx = { |
| 139 | RX_BD_RING_LEN, |
| 140 | RX_BD_RING_LEN, |
| 141 | RX_BD_RING_LEN, |
| 142 | RX_BD_RING_LEN, |
| 143 | RX_BD_RING_LEN, |
| 144 | RX_BD_RING_LEN, |
| 145 | RX_BD_RING_LEN, |
| 146 | RX_BD_RING_LEN}, |
| 147 | |
| 148 | .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1, |
| 149 | .largestexternallookupkeysize = |
| 150 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE, |
| 151 | .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_NONE, |
| 152 | .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP, |
| 153 | .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP, |
| 154 | .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT, |
| 155 | .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE, |
| 156 | .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC, |
| 157 | .numThreadsTx = UCC_GETH_NUM_OF_THREADS_4, |
| 158 | .numThreadsRx = UCC_GETH_NUM_OF_THREADS_4, |
| 159 | .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, |
| 160 | .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, |
| 161 | }; |
| 162 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 163 | static struct ucc_geth_info ugeth_info[8]; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 164 | |
| 165 | #ifdef DEBUG |
| 166 | static void mem_disp(u8 *addr, int size) |
| 167 | { |
| 168 | u8 *i; |
| 169 | int size16Aling = (size >> 4) << 4; |
| 170 | int size4Aling = (size >> 2) << 2; |
| 171 | int notAlign = 0; |
| 172 | if (size % 16) |
| 173 | notAlign = 1; |
| 174 | |
| 175 | for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16) |
| 176 | printk("0x%08x: %08x %08x %08x %08x\r\n", |
| 177 | (u32) i, |
| 178 | *((u32 *) (i)), |
| 179 | *((u32 *) (i + 4)), |
| 180 | *((u32 *) (i + 8)), *((u32 *) (i + 12))); |
| 181 | if (notAlign == 1) |
| 182 | printk("0x%08x: ", (u32) i); |
| 183 | for (; (u32) i < (u32) addr + size4Aling; i += 4) |
| 184 | printk("%08x ", *((u32 *) (i))); |
| 185 | for (; (u32) i < (u32) addr + size; i++) |
| 186 | printk("%02x", *((u8 *) (i))); |
| 187 | if (notAlign == 1) |
| 188 | printk("\r\n"); |
| 189 | } |
| 190 | #endif /* DEBUG */ |
| 191 | |
| 192 | #ifdef CONFIG_UGETH_FILTERING |
| 193 | static void enqueue(struct list_head *node, struct list_head *lh) |
| 194 | { |
| 195 | unsigned long flags; |
| 196 | |
| 197 | spin_lock_irqsave(ugeth_lock, flags); |
| 198 | list_add_tail(node, lh); |
| 199 | spin_unlock_irqrestore(ugeth_lock, flags); |
| 200 | } |
| 201 | #endif /* CONFIG_UGETH_FILTERING */ |
| 202 | |
| 203 | static struct list_head *dequeue(struct list_head *lh) |
| 204 | { |
| 205 | unsigned long flags; |
| 206 | |
| 207 | spin_lock_irqsave(ugeth_lock, flags); |
| 208 | if (!list_empty(lh)) { |
| 209 | struct list_head *node = lh->next; |
| 210 | list_del(node); |
| 211 | spin_unlock_irqrestore(ugeth_lock, flags); |
| 212 | return node; |
| 213 | } else { |
| 214 | spin_unlock_irqrestore(ugeth_lock, flags); |
| 215 | return NULL; |
| 216 | } |
| 217 | } |
| 218 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 219 | static int get_interface_details(enum enet_interface enet_interface, |
| 220 | enum enet_speed *speed, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 221 | int *r10m, |
| 222 | int *rmm, |
| 223 | int *rpm, |
| 224 | int *tbi, int *limited_to_full_duplex) |
| 225 | { |
| 226 | /* Analyze enet_interface according to Interface Mode |
| 227 | Configuration table */ |
| 228 | switch (enet_interface) { |
| 229 | case ENET_10_MII: |
| 230 | *speed = ENET_SPEED_10BT; |
| 231 | break; |
| 232 | case ENET_10_RMII: |
| 233 | *speed = ENET_SPEED_10BT; |
| 234 | *r10m = 1; |
| 235 | *rmm = 1; |
| 236 | break; |
| 237 | case ENET_10_RGMII: |
| 238 | *speed = ENET_SPEED_10BT; |
| 239 | *rpm = 1; |
| 240 | *r10m = 1; |
| 241 | *limited_to_full_duplex = 1; |
| 242 | break; |
| 243 | case ENET_100_MII: |
| 244 | *speed = ENET_SPEED_100BT; |
| 245 | break; |
| 246 | case ENET_100_RMII: |
| 247 | *speed = ENET_SPEED_100BT; |
| 248 | *rmm = 1; |
| 249 | break; |
| 250 | case ENET_100_RGMII: |
| 251 | *speed = ENET_SPEED_100BT; |
| 252 | *rpm = 1; |
| 253 | *limited_to_full_duplex = 1; |
| 254 | break; |
| 255 | case ENET_1000_GMII: |
| 256 | *speed = ENET_SPEED_1000BT; |
| 257 | *limited_to_full_duplex = 1; |
| 258 | break; |
| 259 | case ENET_1000_RGMII: |
| 260 | *speed = ENET_SPEED_1000BT; |
| 261 | *rpm = 1; |
| 262 | *limited_to_full_duplex = 1; |
| 263 | break; |
| 264 | case ENET_1000_TBI: |
| 265 | *speed = ENET_SPEED_1000BT; |
| 266 | *tbi = 1; |
| 267 | *limited_to_full_duplex = 1; |
| 268 | break; |
| 269 | case ENET_1000_RTBI: |
| 270 | *speed = ENET_SPEED_1000BT; |
| 271 | *rpm = 1; |
| 272 | *tbi = 1; |
| 273 | *limited_to_full_duplex = 1; |
| 274 | break; |
| 275 | default: |
| 276 | return -EINVAL; |
| 277 | break; |
| 278 | } |
| 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 283 | static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 284 | { |
| 285 | struct sk_buff *skb = NULL; |
| 286 | |
| 287 | skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length + |
| 288 | UCC_GETH_RX_DATA_BUF_ALIGNMENT); |
| 289 | |
| 290 | if (skb == NULL) |
| 291 | return NULL; |
| 292 | |
| 293 | /* We need the data buffer to be aligned properly. We will reserve |
| 294 | * as many bytes as needed to align the data properly |
| 295 | */ |
| 296 | skb_reserve(skb, |
| 297 | UCC_GETH_RX_DATA_BUF_ALIGNMENT - |
| 298 | (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT - |
| 299 | 1))); |
| 300 | |
| 301 | skb->dev = ugeth->dev; |
| 302 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 303 | out_be32(&((struct qe_bd *)bd)->buf, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 304 | dma_map_single(NULL, |
| 305 | skb->data, |
| 306 | ugeth->ug_info->uf_info.max_rx_buf_length + |
| 307 | UCC_GETH_RX_DATA_BUF_ALIGNMENT, |
| 308 | DMA_FROM_DEVICE)); |
| 309 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 310 | out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W))); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 311 | |
| 312 | return skb; |
| 313 | } |
| 314 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 315 | static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 316 | { |
| 317 | u8 *bd; |
| 318 | u32 bd_status; |
| 319 | struct sk_buff *skb; |
| 320 | int i; |
| 321 | |
| 322 | bd = ugeth->p_rx_bd_ring[rxQ]; |
| 323 | i = 0; |
| 324 | |
| 325 | do { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 326 | bd_status = in_be32((u32*)bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 327 | skb = get_new_skb(ugeth, bd); |
| 328 | |
| 329 | if (!skb) /* If can not allocate data buffer, |
| 330 | abort. Cleanup will be elsewhere */ |
| 331 | return -ENOMEM; |
| 332 | |
| 333 | ugeth->rx_skbuff[rxQ][i] = skb; |
| 334 | |
| 335 | /* advance the BD pointer */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 336 | bd += sizeof(struct qe_bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 337 | i++; |
| 338 | } while (!(bd_status & R_W)); |
| 339 | |
| 340 | return 0; |
| 341 | } |
| 342 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 343 | static int fill_init_enet_entries(struct ucc_geth_private *ugeth, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 344 | volatile u32 *p_start, |
| 345 | u8 num_entries, |
| 346 | u32 thread_size, |
| 347 | u32 thread_alignment, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 348 | enum qe_risc_allocation risc, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 349 | int skip_page_for_first_entry) |
| 350 | { |
| 351 | u32 init_enet_offset; |
| 352 | u8 i; |
| 353 | int snum; |
| 354 | |
| 355 | for (i = 0; i < num_entries; i++) { |
| 356 | if ((snum = qe_get_snum()) < 0) { |
| 357 | ugeth_err("fill_init_enet_entries: Can not get SNUM."); |
| 358 | return snum; |
| 359 | } |
| 360 | if ((i == 0) && skip_page_for_first_entry) |
| 361 | /* First entry of Rx does not have page */ |
| 362 | init_enet_offset = 0; |
| 363 | else { |
| 364 | init_enet_offset = |
| 365 | qe_muram_alloc(thread_size, thread_alignment); |
| 366 | if (IS_MURAM_ERR(init_enet_offset)) { |
| 367 | ugeth_err |
| 368 | ("fill_init_enet_entries: Can not allocate DPRAM memory."); |
| 369 | qe_put_snum((u8) snum); |
| 370 | return -ENOMEM; |
| 371 | } |
| 372 | } |
| 373 | *(p_start++) = |
| 374 | ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset |
| 375 | | risc; |
| 376 | } |
| 377 | |
| 378 | return 0; |
| 379 | } |
| 380 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 381 | static int return_init_enet_entries(struct ucc_geth_private *ugeth, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 382 | volatile u32 *p_start, |
| 383 | u8 num_entries, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 384 | enum qe_risc_allocation risc, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 385 | int skip_page_for_first_entry) |
| 386 | { |
| 387 | u32 init_enet_offset; |
| 388 | u8 i; |
| 389 | int snum; |
| 390 | |
| 391 | for (i = 0; i < num_entries; i++) { |
| 392 | /* Check that this entry was actually valid -- |
| 393 | needed in case failed in allocations */ |
| 394 | if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) { |
| 395 | snum = |
| 396 | (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >> |
| 397 | ENET_INIT_PARAM_SNUM_SHIFT; |
| 398 | qe_put_snum((u8) snum); |
| 399 | if (!((i == 0) && skip_page_for_first_entry)) { |
| 400 | /* First entry of Rx does not have page */ |
| 401 | init_enet_offset = |
| 402 | (in_be32(p_start) & |
| 403 | ENET_INIT_PARAM_PTR_MASK); |
| 404 | qe_muram_free(init_enet_offset); |
| 405 | } |
| 406 | *(p_start++) = 0; /* Just for cosmetics */ |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | return 0; |
| 411 | } |
| 412 | |
| 413 | #ifdef DEBUG |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 414 | static int dump_init_enet_entries(struct ucc_geth_private *ugeth, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 415 | volatile u32 *p_start, |
| 416 | u8 num_entries, |
| 417 | u32 thread_size, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 418 | enum qe_risc_allocation risc, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 419 | int skip_page_for_first_entry) |
| 420 | { |
| 421 | u32 init_enet_offset; |
| 422 | u8 i; |
| 423 | int snum; |
| 424 | |
| 425 | for (i = 0; i < num_entries; i++) { |
| 426 | /* Check that this entry was actually valid -- |
| 427 | needed in case failed in allocations */ |
| 428 | if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) { |
| 429 | snum = |
| 430 | (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >> |
| 431 | ENET_INIT_PARAM_SNUM_SHIFT; |
| 432 | qe_put_snum((u8) snum); |
| 433 | if (!((i == 0) && skip_page_for_first_entry)) { |
| 434 | /* First entry of Rx does not have page */ |
| 435 | init_enet_offset = |
| 436 | (in_be32(p_start) & |
| 437 | ENET_INIT_PARAM_PTR_MASK); |
| 438 | ugeth_info("Init enet entry %d:", i); |
| 439 | ugeth_info("Base address: 0x%08x", |
| 440 | (u32) |
| 441 | qe_muram_addr(init_enet_offset)); |
| 442 | mem_disp(qe_muram_addr(init_enet_offset), |
| 443 | thread_size); |
| 444 | } |
| 445 | p_start++; |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | #endif |
| 452 | |
| 453 | #ifdef CONFIG_UGETH_FILTERING |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 454 | static struct enet_addr_container *get_enet_addr_container(void) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 455 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 456 | struct enet_addr_container *enet_addr_cont; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 457 | |
| 458 | /* allocate memory */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 459 | enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 460 | if (!enet_addr_cont) { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 461 | ugeth_err("%s: No memory for enet_addr_container object.", |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 462 | __FUNCTION__); |
| 463 | return NULL; |
| 464 | } |
| 465 | |
| 466 | return enet_addr_cont; |
| 467 | } |
| 468 | #endif /* CONFIG_UGETH_FILTERING */ |
| 469 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 470 | static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 471 | { |
| 472 | kfree(enet_addr_cont); |
| 473 | } |
| 474 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 475 | static int set_mac_addr(__be16 __iomem *reg, u8 *mac) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 476 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 477 | out_be16(®[0], ((u16)mac[5] << 8) | mac[4]); |
| 478 | out_be16(®[1], ((u16)mac[3] << 8) | mac[2]); |
| 479 | out_be16(®[2], ((u16)mac[1] << 8) | mac[0]); |
| 480 | } |
| 481 | |
| 482 | #ifdef CONFIG_UGETH_FILTERING |
| 483 | static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth, |
| 484 | u8 *p_enet_addr, u8 paddr_num) |
| 485 | { |
| 486 | struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 487 | |
| 488 | if (!(paddr_num < NUM_OF_PADDRS)) { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 489 | ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 490 | return -EINVAL; |
| 491 | } |
| 492 | |
| 493 | p_82xx_addr_filt = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 494 | (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 495 | addressfiltering; |
| 496 | |
| 497 | /* Ethernet frames are defined in Little Endian mode, */ |
| 498 | /* therefore to insert the address we reverse the bytes. */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 499 | set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 500 | return 0; |
| 501 | } |
| 502 | #endif /* CONFIG_UGETH_FILTERING */ |
| 503 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 504 | static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 505 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 506 | struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 507 | |
| 508 | if (!(paddr_num < NUM_OF_PADDRS)) { |
| 509 | ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__); |
| 510 | return -EINVAL; |
| 511 | } |
| 512 | |
| 513 | p_82xx_addr_filt = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 514 | (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 515 | addressfiltering; |
| 516 | |
| 517 | /* Writing address ff.ff.ff.ff.ff.ff disables address |
| 518 | recognition for this register */ |
| 519 | out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff); |
| 520 | out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff); |
| 521 | out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff); |
| 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 526 | static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth, |
| 527 | u8 *p_enet_addr) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 528 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 529 | struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 530 | u32 cecr_subblock; |
| 531 | |
| 532 | p_82xx_addr_filt = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 533 | (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 534 | addressfiltering; |
| 535 | |
| 536 | cecr_subblock = |
| 537 | ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); |
| 538 | |
| 539 | /* Ethernet frames are defined in Little Endian mode, |
| 540 | therefor to insert */ |
| 541 | /* the address to the hash (Big Endian mode), we reverse the bytes.*/ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 542 | |
| 543 | set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 544 | |
| 545 | qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 546 | QE_CR_PROTOCOL_ETHERNET, 0); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 547 | } |
| 548 | |
| 549 | #ifdef CONFIG_UGETH_MAGIC_PACKET |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 550 | static void magic_packet_detection_enable(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 551 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 552 | struct ucc_fast_private *uccf; |
| 553 | struct ucc_geth *ug_regs; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 554 | u32 maccfg2, uccm; |
| 555 | |
| 556 | uccf = ugeth->uccf; |
| 557 | ug_regs = ugeth->ug_regs; |
| 558 | |
| 559 | /* Enable interrupts for magic packet detection */ |
| 560 | uccm = in_be32(uccf->p_uccm); |
| 561 | uccm |= UCCE_MPD; |
| 562 | out_be32(uccf->p_uccm, uccm); |
| 563 | |
| 564 | /* Enable magic packet detection */ |
| 565 | maccfg2 = in_be32(&ug_regs->maccfg2); |
| 566 | maccfg2 |= MACCFG2_MPE; |
| 567 | out_be32(&ug_regs->maccfg2, maccfg2); |
| 568 | } |
| 569 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 570 | static void magic_packet_detection_disable(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 571 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 572 | struct ucc_fast_private *uccf; |
| 573 | struct ucc_geth *ug_regs; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 574 | u32 maccfg2, uccm; |
| 575 | |
| 576 | uccf = ugeth->uccf; |
| 577 | ug_regs = ugeth->ug_regs; |
| 578 | |
| 579 | /* Disable interrupts for magic packet detection */ |
| 580 | uccm = in_be32(uccf->p_uccm); |
| 581 | uccm &= ~UCCE_MPD; |
| 582 | out_be32(uccf->p_uccm, uccm); |
| 583 | |
| 584 | /* Disable magic packet detection */ |
| 585 | maccfg2 = in_be32(&ug_regs->maccfg2); |
| 586 | maccfg2 &= ~MACCFG2_MPE; |
| 587 | out_be32(&ug_regs->maccfg2, maccfg2); |
| 588 | } |
| 589 | #endif /* MAGIC_PACKET */ |
| 590 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 591 | static inline int compare_addr(u8 **addr1, u8 **addr2) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 592 | { |
| 593 | return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS); |
| 594 | } |
| 595 | |
| 596 | #ifdef DEBUG |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 597 | static void get_statistics(struct ucc_geth_private *ugeth, |
| 598 | struct ucc_geth_tx_firmware_statistics * |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 599 | tx_firmware_statistics, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 600 | struct ucc_geth_rx_firmware_statistics * |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 601 | rx_firmware_statistics, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 602 | struct ucc_geth_hardware_statistics *hardware_statistics) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 603 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 604 | struct ucc_fast *uf_regs; |
| 605 | struct ucc_geth *ug_regs; |
| 606 | struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; |
| 607 | struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 608 | |
| 609 | ug_regs = ugeth->ug_regs; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 610 | uf_regs = (struct ucc_fast *) ug_regs; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 611 | p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram; |
| 612 | p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram; |
| 613 | |
| 614 | /* Tx firmware only if user handed pointer and driver actually |
| 615 | gathers Tx firmware statistics */ |
| 616 | if (tx_firmware_statistics && p_tx_fw_statistics_pram) { |
| 617 | tx_firmware_statistics->sicoltx = |
| 618 | in_be32(&p_tx_fw_statistics_pram->sicoltx); |
| 619 | tx_firmware_statistics->mulcoltx = |
| 620 | in_be32(&p_tx_fw_statistics_pram->mulcoltx); |
| 621 | tx_firmware_statistics->latecoltxfr = |
| 622 | in_be32(&p_tx_fw_statistics_pram->latecoltxfr); |
| 623 | tx_firmware_statistics->frabortduecol = |
| 624 | in_be32(&p_tx_fw_statistics_pram->frabortduecol); |
| 625 | tx_firmware_statistics->frlostinmactxer = |
| 626 | in_be32(&p_tx_fw_statistics_pram->frlostinmactxer); |
| 627 | tx_firmware_statistics->carriersenseertx = |
| 628 | in_be32(&p_tx_fw_statistics_pram->carriersenseertx); |
| 629 | tx_firmware_statistics->frtxok = |
| 630 | in_be32(&p_tx_fw_statistics_pram->frtxok); |
| 631 | tx_firmware_statistics->txfrexcessivedefer = |
| 632 | in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer); |
| 633 | tx_firmware_statistics->txpkts256 = |
| 634 | in_be32(&p_tx_fw_statistics_pram->txpkts256); |
| 635 | tx_firmware_statistics->txpkts512 = |
| 636 | in_be32(&p_tx_fw_statistics_pram->txpkts512); |
| 637 | tx_firmware_statistics->txpkts1024 = |
| 638 | in_be32(&p_tx_fw_statistics_pram->txpkts1024); |
| 639 | tx_firmware_statistics->txpktsjumbo = |
| 640 | in_be32(&p_tx_fw_statistics_pram->txpktsjumbo); |
| 641 | } |
| 642 | |
| 643 | /* Rx firmware only if user handed pointer and driver actually |
| 644 | * gathers Rx firmware statistics */ |
| 645 | if (rx_firmware_statistics && p_rx_fw_statistics_pram) { |
| 646 | int i; |
| 647 | rx_firmware_statistics->frrxfcser = |
| 648 | in_be32(&p_rx_fw_statistics_pram->frrxfcser); |
| 649 | rx_firmware_statistics->fraligner = |
| 650 | in_be32(&p_rx_fw_statistics_pram->fraligner); |
| 651 | rx_firmware_statistics->inrangelenrxer = |
| 652 | in_be32(&p_rx_fw_statistics_pram->inrangelenrxer); |
| 653 | rx_firmware_statistics->outrangelenrxer = |
| 654 | in_be32(&p_rx_fw_statistics_pram->outrangelenrxer); |
| 655 | rx_firmware_statistics->frtoolong = |
| 656 | in_be32(&p_rx_fw_statistics_pram->frtoolong); |
| 657 | rx_firmware_statistics->runt = |
| 658 | in_be32(&p_rx_fw_statistics_pram->runt); |
| 659 | rx_firmware_statistics->verylongevent = |
| 660 | in_be32(&p_rx_fw_statistics_pram->verylongevent); |
| 661 | rx_firmware_statistics->symbolerror = |
| 662 | in_be32(&p_rx_fw_statistics_pram->symbolerror); |
| 663 | rx_firmware_statistics->dropbsy = |
| 664 | in_be32(&p_rx_fw_statistics_pram->dropbsy); |
| 665 | for (i = 0; i < 0x8; i++) |
| 666 | rx_firmware_statistics->res0[i] = |
| 667 | p_rx_fw_statistics_pram->res0[i]; |
| 668 | rx_firmware_statistics->mismatchdrop = |
| 669 | in_be32(&p_rx_fw_statistics_pram->mismatchdrop); |
| 670 | rx_firmware_statistics->underpkts = |
| 671 | in_be32(&p_rx_fw_statistics_pram->underpkts); |
| 672 | rx_firmware_statistics->pkts256 = |
| 673 | in_be32(&p_rx_fw_statistics_pram->pkts256); |
| 674 | rx_firmware_statistics->pkts512 = |
| 675 | in_be32(&p_rx_fw_statistics_pram->pkts512); |
| 676 | rx_firmware_statistics->pkts1024 = |
| 677 | in_be32(&p_rx_fw_statistics_pram->pkts1024); |
| 678 | rx_firmware_statistics->pktsjumbo = |
| 679 | in_be32(&p_rx_fw_statistics_pram->pktsjumbo); |
| 680 | rx_firmware_statistics->frlossinmacer = |
| 681 | in_be32(&p_rx_fw_statistics_pram->frlossinmacer); |
| 682 | rx_firmware_statistics->pausefr = |
| 683 | in_be32(&p_rx_fw_statistics_pram->pausefr); |
| 684 | for (i = 0; i < 0x4; i++) |
| 685 | rx_firmware_statistics->res1[i] = |
| 686 | p_rx_fw_statistics_pram->res1[i]; |
| 687 | rx_firmware_statistics->removevlan = |
| 688 | in_be32(&p_rx_fw_statistics_pram->removevlan); |
| 689 | rx_firmware_statistics->replacevlan = |
| 690 | in_be32(&p_rx_fw_statistics_pram->replacevlan); |
| 691 | rx_firmware_statistics->insertvlan = |
| 692 | in_be32(&p_rx_fw_statistics_pram->insertvlan); |
| 693 | } |
| 694 | |
| 695 | /* Hardware only if user handed pointer and driver actually |
| 696 | gathers hardware statistics */ |
| 697 | if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) { |
| 698 | hardware_statistics->tx64 = in_be32(&ug_regs->tx64); |
| 699 | hardware_statistics->tx127 = in_be32(&ug_regs->tx127); |
| 700 | hardware_statistics->tx255 = in_be32(&ug_regs->tx255); |
| 701 | hardware_statistics->rx64 = in_be32(&ug_regs->rx64); |
| 702 | hardware_statistics->rx127 = in_be32(&ug_regs->rx127); |
| 703 | hardware_statistics->rx255 = in_be32(&ug_regs->rx255); |
| 704 | hardware_statistics->txok = in_be32(&ug_regs->txok); |
| 705 | hardware_statistics->txcf = in_be16(&ug_regs->txcf); |
| 706 | hardware_statistics->tmca = in_be32(&ug_regs->tmca); |
| 707 | hardware_statistics->tbca = in_be32(&ug_regs->tbca); |
| 708 | hardware_statistics->rxfok = in_be32(&ug_regs->rxfok); |
| 709 | hardware_statistics->rxbok = in_be32(&ug_regs->rxbok); |
| 710 | hardware_statistics->rbyt = in_be32(&ug_regs->rbyt); |
| 711 | hardware_statistics->rmca = in_be32(&ug_regs->rmca); |
| 712 | hardware_statistics->rbca = in_be32(&ug_regs->rbca); |
| 713 | } |
| 714 | } |
| 715 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 716 | static void dump_bds(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 717 | { |
| 718 | int i; |
| 719 | int length; |
| 720 | |
| 721 | for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { |
| 722 | if (ugeth->p_tx_bd_ring[i]) { |
| 723 | length = |
| 724 | (ugeth->ug_info->bdRingLenTx[i] * |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 725 | sizeof(struct qe_bd)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 726 | ugeth_info("TX BDs[%d]", i); |
| 727 | mem_disp(ugeth->p_tx_bd_ring[i], length); |
| 728 | } |
| 729 | } |
| 730 | for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { |
| 731 | if (ugeth->p_rx_bd_ring[i]) { |
| 732 | length = |
| 733 | (ugeth->ug_info->bdRingLenRx[i] * |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 734 | sizeof(struct qe_bd)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 735 | ugeth_info("RX BDs[%d]", i); |
| 736 | mem_disp(ugeth->p_rx_bd_ring[i], length); |
| 737 | } |
| 738 | } |
| 739 | } |
| 740 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 741 | static void dump_regs(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 742 | { |
| 743 | int i; |
| 744 | |
| 745 | ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num); |
| 746 | ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs); |
| 747 | |
| 748 | ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x", |
| 749 | (u32) & ugeth->ug_regs->maccfg1, |
| 750 | in_be32(&ugeth->ug_regs->maccfg1)); |
| 751 | ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x", |
| 752 | (u32) & ugeth->ug_regs->maccfg2, |
| 753 | in_be32(&ugeth->ug_regs->maccfg2)); |
| 754 | ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x", |
| 755 | (u32) & ugeth->ug_regs->ipgifg, |
| 756 | in_be32(&ugeth->ug_regs->ipgifg)); |
| 757 | ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x", |
| 758 | (u32) & ugeth->ug_regs->hafdup, |
| 759 | in_be32(&ugeth->ug_regs->hafdup)); |
| 760 | ugeth_info("miimcfg : addr - 0x%08x, val - 0x%08x", |
| 761 | (u32) & ugeth->ug_regs->miimng.miimcfg, |
| 762 | in_be32(&ugeth->ug_regs->miimng.miimcfg)); |
| 763 | ugeth_info("miimcom : addr - 0x%08x, val - 0x%08x", |
| 764 | (u32) & ugeth->ug_regs->miimng.miimcom, |
| 765 | in_be32(&ugeth->ug_regs->miimng.miimcom)); |
| 766 | ugeth_info("miimadd : addr - 0x%08x, val - 0x%08x", |
| 767 | (u32) & ugeth->ug_regs->miimng.miimadd, |
| 768 | in_be32(&ugeth->ug_regs->miimng.miimadd)); |
| 769 | ugeth_info("miimcon : addr - 0x%08x, val - 0x%08x", |
| 770 | (u32) & ugeth->ug_regs->miimng.miimcon, |
| 771 | in_be32(&ugeth->ug_regs->miimng.miimcon)); |
| 772 | ugeth_info("miimstat : addr - 0x%08x, val - 0x%08x", |
| 773 | (u32) & ugeth->ug_regs->miimng.miimstat, |
| 774 | in_be32(&ugeth->ug_regs->miimng.miimstat)); |
| 775 | ugeth_info("miimmind : addr - 0x%08x, val - 0x%08x", |
| 776 | (u32) & ugeth->ug_regs->miimng.miimind, |
| 777 | in_be32(&ugeth->ug_regs->miimng.miimind)); |
| 778 | ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x", |
| 779 | (u32) & ugeth->ug_regs->ifctl, |
| 780 | in_be32(&ugeth->ug_regs->ifctl)); |
| 781 | ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x", |
| 782 | (u32) & ugeth->ug_regs->ifstat, |
| 783 | in_be32(&ugeth->ug_regs->ifstat)); |
| 784 | ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x", |
| 785 | (u32) & ugeth->ug_regs->macstnaddr1, |
| 786 | in_be32(&ugeth->ug_regs->macstnaddr1)); |
| 787 | ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x", |
| 788 | (u32) & ugeth->ug_regs->macstnaddr2, |
| 789 | in_be32(&ugeth->ug_regs->macstnaddr2)); |
| 790 | ugeth_info("uempr : addr - 0x%08x, val - 0x%08x", |
| 791 | (u32) & ugeth->ug_regs->uempr, |
| 792 | in_be32(&ugeth->ug_regs->uempr)); |
| 793 | ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x", |
| 794 | (u32) & ugeth->ug_regs->utbipar, |
| 795 | in_be32(&ugeth->ug_regs->utbipar)); |
| 796 | ugeth_info("uescr : addr - 0x%08x, val - 0x%04x", |
| 797 | (u32) & ugeth->ug_regs->uescr, |
| 798 | in_be16(&ugeth->ug_regs->uescr)); |
| 799 | ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x", |
| 800 | (u32) & ugeth->ug_regs->tx64, |
| 801 | in_be32(&ugeth->ug_regs->tx64)); |
| 802 | ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x", |
| 803 | (u32) & ugeth->ug_regs->tx127, |
| 804 | in_be32(&ugeth->ug_regs->tx127)); |
| 805 | ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x", |
| 806 | (u32) & ugeth->ug_regs->tx255, |
| 807 | in_be32(&ugeth->ug_regs->tx255)); |
| 808 | ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x", |
| 809 | (u32) & ugeth->ug_regs->rx64, |
| 810 | in_be32(&ugeth->ug_regs->rx64)); |
| 811 | ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x", |
| 812 | (u32) & ugeth->ug_regs->rx127, |
| 813 | in_be32(&ugeth->ug_regs->rx127)); |
| 814 | ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x", |
| 815 | (u32) & ugeth->ug_regs->rx255, |
| 816 | in_be32(&ugeth->ug_regs->rx255)); |
| 817 | ugeth_info("txok : addr - 0x%08x, val - 0x%08x", |
| 818 | (u32) & ugeth->ug_regs->txok, |
| 819 | in_be32(&ugeth->ug_regs->txok)); |
| 820 | ugeth_info("txcf : addr - 0x%08x, val - 0x%04x", |
| 821 | (u32) & ugeth->ug_regs->txcf, |
| 822 | in_be16(&ugeth->ug_regs->txcf)); |
| 823 | ugeth_info("tmca : addr - 0x%08x, val - 0x%08x", |
| 824 | (u32) & ugeth->ug_regs->tmca, |
| 825 | in_be32(&ugeth->ug_regs->tmca)); |
| 826 | ugeth_info("tbca : addr - 0x%08x, val - 0x%08x", |
| 827 | (u32) & ugeth->ug_regs->tbca, |
| 828 | in_be32(&ugeth->ug_regs->tbca)); |
| 829 | ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x", |
| 830 | (u32) & ugeth->ug_regs->rxfok, |
| 831 | in_be32(&ugeth->ug_regs->rxfok)); |
| 832 | ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x", |
| 833 | (u32) & ugeth->ug_regs->rxbok, |
| 834 | in_be32(&ugeth->ug_regs->rxbok)); |
| 835 | ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x", |
| 836 | (u32) & ugeth->ug_regs->rbyt, |
| 837 | in_be32(&ugeth->ug_regs->rbyt)); |
| 838 | ugeth_info("rmca : addr - 0x%08x, val - 0x%08x", |
| 839 | (u32) & ugeth->ug_regs->rmca, |
| 840 | in_be32(&ugeth->ug_regs->rmca)); |
| 841 | ugeth_info("rbca : addr - 0x%08x, val - 0x%08x", |
| 842 | (u32) & ugeth->ug_regs->rbca, |
| 843 | in_be32(&ugeth->ug_regs->rbca)); |
| 844 | ugeth_info("scar : addr - 0x%08x, val - 0x%08x", |
| 845 | (u32) & ugeth->ug_regs->scar, |
| 846 | in_be32(&ugeth->ug_regs->scar)); |
| 847 | ugeth_info("scam : addr - 0x%08x, val - 0x%08x", |
| 848 | (u32) & ugeth->ug_regs->scam, |
| 849 | in_be32(&ugeth->ug_regs->scam)); |
| 850 | |
| 851 | if (ugeth->p_thread_data_tx) { |
| 852 | int numThreadsTxNumerical; |
| 853 | switch (ugeth->ug_info->numThreadsTx) { |
| 854 | case UCC_GETH_NUM_OF_THREADS_1: |
| 855 | numThreadsTxNumerical = 1; |
| 856 | break; |
| 857 | case UCC_GETH_NUM_OF_THREADS_2: |
| 858 | numThreadsTxNumerical = 2; |
| 859 | break; |
| 860 | case UCC_GETH_NUM_OF_THREADS_4: |
| 861 | numThreadsTxNumerical = 4; |
| 862 | break; |
| 863 | case UCC_GETH_NUM_OF_THREADS_6: |
| 864 | numThreadsTxNumerical = 6; |
| 865 | break; |
| 866 | case UCC_GETH_NUM_OF_THREADS_8: |
| 867 | numThreadsTxNumerical = 8; |
| 868 | break; |
| 869 | default: |
| 870 | numThreadsTxNumerical = 0; |
| 871 | break; |
| 872 | } |
| 873 | |
| 874 | ugeth_info("Thread data TXs:"); |
| 875 | ugeth_info("Base address: 0x%08x", |
| 876 | (u32) ugeth->p_thread_data_tx); |
| 877 | for (i = 0; i < numThreadsTxNumerical; i++) { |
| 878 | ugeth_info("Thread data TX[%d]:", i); |
| 879 | ugeth_info("Base address: 0x%08x", |
| 880 | (u32) & ugeth->p_thread_data_tx[i]); |
| 881 | mem_disp((u8 *) & ugeth->p_thread_data_tx[i], |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 882 | sizeof(struct ucc_geth_thread_data_tx)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 883 | } |
| 884 | } |
| 885 | if (ugeth->p_thread_data_rx) { |
| 886 | int numThreadsRxNumerical; |
| 887 | switch (ugeth->ug_info->numThreadsRx) { |
| 888 | case UCC_GETH_NUM_OF_THREADS_1: |
| 889 | numThreadsRxNumerical = 1; |
| 890 | break; |
| 891 | case UCC_GETH_NUM_OF_THREADS_2: |
| 892 | numThreadsRxNumerical = 2; |
| 893 | break; |
| 894 | case UCC_GETH_NUM_OF_THREADS_4: |
| 895 | numThreadsRxNumerical = 4; |
| 896 | break; |
| 897 | case UCC_GETH_NUM_OF_THREADS_6: |
| 898 | numThreadsRxNumerical = 6; |
| 899 | break; |
| 900 | case UCC_GETH_NUM_OF_THREADS_8: |
| 901 | numThreadsRxNumerical = 8; |
| 902 | break; |
| 903 | default: |
| 904 | numThreadsRxNumerical = 0; |
| 905 | break; |
| 906 | } |
| 907 | |
| 908 | ugeth_info("Thread data RX:"); |
| 909 | ugeth_info("Base address: 0x%08x", |
| 910 | (u32) ugeth->p_thread_data_rx); |
| 911 | for (i = 0; i < numThreadsRxNumerical; i++) { |
| 912 | ugeth_info("Thread data RX[%d]:", i); |
| 913 | ugeth_info("Base address: 0x%08x", |
| 914 | (u32) & ugeth->p_thread_data_rx[i]); |
| 915 | mem_disp((u8 *) & ugeth->p_thread_data_rx[i], |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 916 | sizeof(struct ucc_geth_thread_data_rx)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 917 | } |
| 918 | } |
| 919 | if (ugeth->p_exf_glbl_param) { |
| 920 | ugeth_info("EXF global param:"); |
| 921 | ugeth_info("Base address: 0x%08x", |
| 922 | (u32) ugeth->p_exf_glbl_param); |
| 923 | mem_disp((u8 *) ugeth->p_exf_glbl_param, |
| 924 | sizeof(*ugeth->p_exf_glbl_param)); |
| 925 | } |
| 926 | if (ugeth->p_tx_glbl_pram) { |
| 927 | ugeth_info("TX global param:"); |
| 928 | ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram); |
| 929 | ugeth_info("temoder : addr - 0x%08x, val - 0x%04x", |
| 930 | (u32) & ugeth->p_tx_glbl_pram->temoder, |
| 931 | in_be16(&ugeth->p_tx_glbl_pram->temoder)); |
| 932 | ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x", |
| 933 | (u32) & ugeth->p_tx_glbl_pram->sqptr, |
| 934 | in_be32(&ugeth->p_tx_glbl_pram->sqptr)); |
| 935 | ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x", |
| 936 | (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer, |
| 937 | in_be32(&ugeth->p_tx_glbl_pram-> |
| 938 | schedulerbasepointer)); |
| 939 | ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x", |
| 940 | (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr, |
| 941 | in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr)); |
| 942 | ugeth_info("tstate : addr - 0x%08x, val - 0x%08x", |
| 943 | (u32) & ugeth->p_tx_glbl_pram->tstate, |
| 944 | in_be32(&ugeth->p_tx_glbl_pram->tstate)); |
| 945 | ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x", |
| 946 | (u32) & ugeth->p_tx_glbl_pram->iphoffset[0], |
| 947 | ugeth->p_tx_glbl_pram->iphoffset[0]); |
| 948 | ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x", |
| 949 | (u32) & ugeth->p_tx_glbl_pram->iphoffset[1], |
| 950 | ugeth->p_tx_glbl_pram->iphoffset[1]); |
| 951 | ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x", |
| 952 | (u32) & ugeth->p_tx_glbl_pram->iphoffset[2], |
| 953 | ugeth->p_tx_glbl_pram->iphoffset[2]); |
| 954 | ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x", |
| 955 | (u32) & ugeth->p_tx_glbl_pram->iphoffset[3], |
| 956 | ugeth->p_tx_glbl_pram->iphoffset[3]); |
| 957 | ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x", |
| 958 | (u32) & ugeth->p_tx_glbl_pram->iphoffset[4], |
| 959 | ugeth->p_tx_glbl_pram->iphoffset[4]); |
| 960 | ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x", |
| 961 | (u32) & ugeth->p_tx_glbl_pram->iphoffset[5], |
| 962 | ugeth->p_tx_glbl_pram->iphoffset[5]); |
| 963 | ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x", |
| 964 | (u32) & ugeth->p_tx_glbl_pram->iphoffset[6], |
| 965 | ugeth->p_tx_glbl_pram->iphoffset[6]); |
| 966 | ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x", |
| 967 | (u32) & ugeth->p_tx_glbl_pram->iphoffset[7], |
| 968 | ugeth->p_tx_glbl_pram->iphoffset[7]); |
| 969 | ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x", |
| 970 | (u32) & ugeth->p_tx_glbl_pram->vtagtable[0], |
| 971 | in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0])); |
| 972 | ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x", |
| 973 | (u32) & ugeth->p_tx_glbl_pram->vtagtable[1], |
| 974 | in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1])); |
| 975 | ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x", |
| 976 | (u32) & ugeth->p_tx_glbl_pram->vtagtable[2], |
| 977 | in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2])); |
| 978 | ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x", |
| 979 | (u32) & ugeth->p_tx_glbl_pram->vtagtable[3], |
| 980 | in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3])); |
| 981 | ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x", |
| 982 | (u32) & ugeth->p_tx_glbl_pram->vtagtable[4], |
| 983 | in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4])); |
| 984 | ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x", |
| 985 | (u32) & ugeth->p_tx_glbl_pram->vtagtable[5], |
| 986 | in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5])); |
| 987 | ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x", |
| 988 | (u32) & ugeth->p_tx_glbl_pram->vtagtable[6], |
| 989 | in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6])); |
| 990 | ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x", |
| 991 | (u32) & ugeth->p_tx_glbl_pram->vtagtable[7], |
| 992 | in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7])); |
| 993 | ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x", |
| 994 | (u32) & ugeth->p_tx_glbl_pram->tqptr, |
| 995 | in_be32(&ugeth->p_tx_glbl_pram->tqptr)); |
| 996 | } |
| 997 | if (ugeth->p_rx_glbl_pram) { |
| 998 | ugeth_info("RX global param:"); |
| 999 | ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram); |
| 1000 | ugeth_info("remoder : addr - 0x%08x, val - 0x%08x", |
| 1001 | (u32) & ugeth->p_rx_glbl_pram->remoder, |
| 1002 | in_be32(&ugeth->p_rx_glbl_pram->remoder)); |
| 1003 | ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x", |
| 1004 | (u32) & ugeth->p_rx_glbl_pram->rqptr, |
| 1005 | in_be32(&ugeth->p_rx_glbl_pram->rqptr)); |
| 1006 | ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x", |
| 1007 | (u32) & ugeth->p_rx_glbl_pram->typeorlen, |
| 1008 | in_be16(&ugeth->p_rx_glbl_pram->typeorlen)); |
| 1009 | ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x", |
| 1010 | (u32) & ugeth->p_rx_glbl_pram->rxgstpack, |
| 1011 | ugeth->p_rx_glbl_pram->rxgstpack); |
| 1012 | ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x", |
| 1013 | (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr, |
| 1014 | in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr)); |
| 1015 | ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x", |
| 1016 | (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr, |
| 1017 | in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr)); |
| 1018 | ugeth_info("rstate : addr - 0x%08x, val - 0x%02x", |
| 1019 | (u32) & ugeth->p_rx_glbl_pram->rstate, |
| 1020 | ugeth->p_rx_glbl_pram->rstate); |
| 1021 | ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x", |
| 1022 | (u32) & ugeth->p_rx_glbl_pram->mrblr, |
| 1023 | in_be16(&ugeth->p_rx_glbl_pram->mrblr)); |
| 1024 | ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x", |
| 1025 | (u32) & ugeth->p_rx_glbl_pram->rbdqptr, |
| 1026 | in_be32(&ugeth->p_rx_glbl_pram->rbdqptr)); |
| 1027 | ugeth_info("mflr : addr - 0x%08x, val - 0x%04x", |
| 1028 | (u32) & ugeth->p_rx_glbl_pram->mflr, |
| 1029 | in_be16(&ugeth->p_rx_glbl_pram->mflr)); |
| 1030 | ugeth_info("minflr : addr - 0x%08x, val - 0x%04x", |
| 1031 | (u32) & ugeth->p_rx_glbl_pram->minflr, |
| 1032 | in_be16(&ugeth->p_rx_glbl_pram->minflr)); |
| 1033 | ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x", |
| 1034 | (u32) & ugeth->p_rx_glbl_pram->maxd1, |
| 1035 | in_be16(&ugeth->p_rx_glbl_pram->maxd1)); |
| 1036 | ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x", |
| 1037 | (u32) & ugeth->p_rx_glbl_pram->maxd2, |
| 1038 | in_be16(&ugeth->p_rx_glbl_pram->maxd2)); |
| 1039 | ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x", |
| 1040 | (u32) & ugeth->p_rx_glbl_pram->ecamptr, |
| 1041 | in_be32(&ugeth->p_rx_glbl_pram->ecamptr)); |
| 1042 | ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x", |
| 1043 | (u32) & ugeth->p_rx_glbl_pram->l2qt, |
| 1044 | in_be32(&ugeth->p_rx_glbl_pram->l2qt)); |
| 1045 | ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x", |
| 1046 | (u32) & ugeth->p_rx_glbl_pram->l3qt[0], |
| 1047 | in_be32(&ugeth->p_rx_glbl_pram->l3qt[0])); |
| 1048 | ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x", |
| 1049 | (u32) & ugeth->p_rx_glbl_pram->l3qt[1], |
| 1050 | in_be32(&ugeth->p_rx_glbl_pram->l3qt[1])); |
| 1051 | ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x", |
| 1052 | (u32) & ugeth->p_rx_glbl_pram->l3qt[2], |
| 1053 | in_be32(&ugeth->p_rx_glbl_pram->l3qt[2])); |
| 1054 | ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x", |
| 1055 | (u32) & ugeth->p_rx_glbl_pram->l3qt[3], |
| 1056 | in_be32(&ugeth->p_rx_glbl_pram->l3qt[3])); |
| 1057 | ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x", |
| 1058 | (u32) & ugeth->p_rx_glbl_pram->l3qt[4], |
| 1059 | in_be32(&ugeth->p_rx_glbl_pram->l3qt[4])); |
| 1060 | ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x", |
| 1061 | (u32) & ugeth->p_rx_glbl_pram->l3qt[5], |
| 1062 | in_be32(&ugeth->p_rx_glbl_pram->l3qt[5])); |
| 1063 | ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x", |
| 1064 | (u32) & ugeth->p_rx_glbl_pram->l3qt[6], |
| 1065 | in_be32(&ugeth->p_rx_glbl_pram->l3qt[6])); |
| 1066 | ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x", |
| 1067 | (u32) & ugeth->p_rx_glbl_pram->l3qt[7], |
| 1068 | in_be32(&ugeth->p_rx_glbl_pram->l3qt[7])); |
| 1069 | ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x", |
| 1070 | (u32) & ugeth->p_rx_glbl_pram->vlantype, |
| 1071 | in_be16(&ugeth->p_rx_glbl_pram->vlantype)); |
| 1072 | ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x", |
| 1073 | (u32) & ugeth->p_rx_glbl_pram->vlantci, |
| 1074 | in_be16(&ugeth->p_rx_glbl_pram->vlantci)); |
| 1075 | for (i = 0; i < 64; i++) |
| 1076 | ugeth_info |
| 1077 | ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x", |
| 1078 | i, |
| 1079 | (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i], |
| 1080 | ugeth->p_rx_glbl_pram->addressfiltering[i]); |
| 1081 | ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x", |
| 1082 | (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam, |
| 1083 | in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam)); |
| 1084 | } |
| 1085 | if (ugeth->p_send_q_mem_reg) { |
| 1086 | ugeth_info("Send Q memory registers:"); |
| 1087 | ugeth_info("Base address: 0x%08x", |
| 1088 | (u32) ugeth->p_send_q_mem_reg); |
| 1089 | for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { |
| 1090 | ugeth_info("SQQD[%d]:", i); |
| 1091 | ugeth_info("Base address: 0x%08x", |
| 1092 | (u32) & ugeth->p_send_q_mem_reg->sqqd[i]); |
| 1093 | mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i], |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1094 | sizeof(struct ucc_geth_send_queue_qd)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1095 | } |
| 1096 | } |
| 1097 | if (ugeth->p_scheduler) { |
| 1098 | ugeth_info("Scheduler:"); |
| 1099 | ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler); |
| 1100 | mem_disp((u8 *) ugeth->p_scheduler, |
| 1101 | sizeof(*ugeth->p_scheduler)); |
| 1102 | } |
| 1103 | if (ugeth->p_tx_fw_statistics_pram) { |
| 1104 | ugeth_info("TX FW statistics pram:"); |
| 1105 | ugeth_info("Base address: 0x%08x", |
| 1106 | (u32) ugeth->p_tx_fw_statistics_pram); |
| 1107 | mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram, |
| 1108 | sizeof(*ugeth->p_tx_fw_statistics_pram)); |
| 1109 | } |
| 1110 | if (ugeth->p_rx_fw_statistics_pram) { |
| 1111 | ugeth_info("RX FW statistics pram:"); |
| 1112 | ugeth_info("Base address: 0x%08x", |
| 1113 | (u32) ugeth->p_rx_fw_statistics_pram); |
| 1114 | mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram, |
| 1115 | sizeof(*ugeth->p_rx_fw_statistics_pram)); |
| 1116 | } |
| 1117 | if (ugeth->p_rx_irq_coalescing_tbl) { |
| 1118 | ugeth_info("RX IRQ coalescing tables:"); |
| 1119 | ugeth_info("Base address: 0x%08x", |
| 1120 | (u32) ugeth->p_rx_irq_coalescing_tbl); |
| 1121 | for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { |
| 1122 | ugeth_info("RX IRQ coalescing table entry[%d]:", i); |
| 1123 | ugeth_info("Base address: 0x%08x", |
| 1124 | (u32) & ugeth->p_rx_irq_coalescing_tbl-> |
| 1125 | coalescingentry[i]); |
| 1126 | ugeth_info |
| 1127 | ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x", |
| 1128 | (u32) & ugeth->p_rx_irq_coalescing_tbl-> |
| 1129 | coalescingentry[i].interruptcoalescingmaxvalue, |
| 1130 | in_be32(&ugeth->p_rx_irq_coalescing_tbl-> |
| 1131 | coalescingentry[i]. |
| 1132 | interruptcoalescingmaxvalue)); |
| 1133 | ugeth_info |
| 1134 | ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x", |
| 1135 | (u32) & ugeth->p_rx_irq_coalescing_tbl-> |
| 1136 | coalescingentry[i].interruptcoalescingcounter, |
| 1137 | in_be32(&ugeth->p_rx_irq_coalescing_tbl-> |
| 1138 | coalescingentry[i]. |
| 1139 | interruptcoalescingcounter)); |
| 1140 | } |
| 1141 | } |
| 1142 | if (ugeth->p_rx_bd_qs_tbl) { |
| 1143 | ugeth_info("RX BD QS tables:"); |
| 1144 | ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl); |
| 1145 | for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { |
| 1146 | ugeth_info("RX BD QS table[%d]:", i); |
| 1147 | ugeth_info("Base address: 0x%08x", |
| 1148 | (u32) & ugeth->p_rx_bd_qs_tbl[i]); |
| 1149 | ugeth_info |
| 1150 | ("bdbaseptr : addr - 0x%08x, val - 0x%08x", |
| 1151 | (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr, |
| 1152 | in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr)); |
| 1153 | ugeth_info |
| 1154 | ("bdptr : addr - 0x%08x, val - 0x%08x", |
| 1155 | (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr, |
| 1156 | in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr)); |
| 1157 | ugeth_info |
| 1158 | ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x", |
| 1159 | (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, |
| 1160 | in_be32(&ugeth->p_rx_bd_qs_tbl[i]. |
| 1161 | externalbdbaseptr)); |
| 1162 | ugeth_info |
| 1163 | ("externalbdptr : addr - 0x%08x, val - 0x%08x", |
| 1164 | (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr, |
| 1165 | in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr)); |
| 1166 | ugeth_info("ucode RX Prefetched BDs:"); |
| 1167 | ugeth_info("Base address: 0x%08x", |
| 1168 | (u32) |
| 1169 | qe_muram_addr(in_be32 |
| 1170 | (&ugeth->p_rx_bd_qs_tbl[i]. |
| 1171 | bdbaseptr))); |
| 1172 | mem_disp((u8 *) |
| 1173 | qe_muram_addr(in_be32 |
| 1174 | (&ugeth->p_rx_bd_qs_tbl[i]. |
| 1175 | bdbaseptr)), |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1176 | sizeof(struct ucc_geth_rx_prefetched_bds)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1177 | } |
| 1178 | } |
| 1179 | if (ugeth->p_init_enet_param_shadow) { |
| 1180 | int size; |
| 1181 | ugeth_info("Init enet param shadow:"); |
| 1182 | ugeth_info("Base address: 0x%08x", |
| 1183 | (u32) ugeth->p_init_enet_param_shadow); |
| 1184 | mem_disp((u8 *) ugeth->p_init_enet_param_shadow, |
| 1185 | sizeof(*ugeth->p_init_enet_param_shadow)); |
| 1186 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1187 | size = sizeof(struct ucc_geth_thread_rx_pram); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1188 | if (ugeth->ug_info->rxExtendedFiltering) { |
| 1189 | size += |
| 1190 | THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; |
| 1191 | if (ugeth->ug_info->largestexternallookupkeysize == |
| 1192 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) |
| 1193 | size += |
| 1194 | THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; |
| 1195 | if (ugeth->ug_info->largestexternallookupkeysize == |
| 1196 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) |
| 1197 | size += |
| 1198 | THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; |
| 1199 | } |
| 1200 | |
| 1201 | dump_init_enet_entries(ugeth, |
| 1202 | &(ugeth->p_init_enet_param_shadow-> |
| 1203 | txthread[0]), |
| 1204 | ENET_INIT_PARAM_MAX_ENTRIES_TX, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1205 | sizeof(struct ucc_geth_thread_tx_pram), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1206 | ugeth->ug_info->riscTx, 0); |
| 1207 | dump_init_enet_entries(ugeth, |
| 1208 | &(ugeth->p_init_enet_param_shadow-> |
| 1209 | rxthread[0]), |
| 1210 | ENET_INIT_PARAM_MAX_ENTRIES_RX, size, |
| 1211 | ugeth->ug_info->riscRx, 1); |
| 1212 | } |
| 1213 | } |
| 1214 | #endif /* DEBUG */ |
| 1215 | |
| 1216 | static void init_default_reg_vals(volatile u32 *upsmr_register, |
| 1217 | volatile u32 *maccfg1_register, |
| 1218 | volatile u32 *maccfg2_register) |
| 1219 | { |
| 1220 | out_be32(upsmr_register, UCC_GETH_UPSMR_INIT); |
| 1221 | out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT); |
| 1222 | out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT); |
| 1223 | } |
| 1224 | |
| 1225 | static int init_half_duplex_params(int alt_beb, |
| 1226 | int back_pressure_no_backoff, |
| 1227 | int no_backoff, |
| 1228 | int excess_defer, |
| 1229 | u8 alt_beb_truncation, |
| 1230 | u8 max_retransmissions, |
| 1231 | u8 collision_window, |
| 1232 | volatile u32 *hafdup_register) |
| 1233 | { |
| 1234 | u32 value = 0; |
| 1235 | |
| 1236 | if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) || |
| 1237 | (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) || |
| 1238 | (collision_window > HALFDUP_COLLISION_WINDOW_MAX)) |
| 1239 | return -EINVAL; |
| 1240 | |
| 1241 | value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT); |
| 1242 | |
| 1243 | if (alt_beb) |
| 1244 | value |= HALFDUP_ALT_BEB; |
| 1245 | if (back_pressure_no_backoff) |
| 1246 | value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF; |
| 1247 | if (no_backoff) |
| 1248 | value |= HALFDUP_NO_BACKOFF; |
| 1249 | if (excess_defer) |
| 1250 | value |= HALFDUP_EXCESSIVE_DEFER; |
| 1251 | |
| 1252 | value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT); |
| 1253 | |
| 1254 | value |= collision_window; |
| 1255 | |
| 1256 | out_be32(hafdup_register, value); |
| 1257 | return 0; |
| 1258 | } |
| 1259 | |
| 1260 | static int init_inter_frame_gap_params(u8 non_btb_cs_ipg, |
| 1261 | u8 non_btb_ipg, |
| 1262 | u8 min_ifg, |
| 1263 | u8 btb_ipg, |
| 1264 | volatile u32 *ipgifg_register) |
| 1265 | { |
| 1266 | u32 value = 0; |
| 1267 | |
| 1268 | /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back |
| 1269 | IPG part 2 */ |
| 1270 | if (non_btb_cs_ipg > non_btb_ipg) |
| 1271 | return -EINVAL; |
| 1272 | |
| 1273 | if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) || |
| 1274 | (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) || |
| 1275 | /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */ |
| 1276 | (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX)) |
| 1277 | return -EINVAL; |
| 1278 | |
| 1279 | value |= |
| 1280 | ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) & |
| 1281 | IPGIFG_NBTB_CS_IPG_MASK); |
| 1282 | value |= |
| 1283 | ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) & |
| 1284 | IPGIFG_NBTB_IPG_MASK); |
| 1285 | value |= |
| 1286 | ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) & |
| 1287 | IPGIFG_MIN_IFG_MASK); |
| 1288 | value |= (btb_ipg & IPGIFG_BTB_IPG_MASK); |
| 1289 | |
| 1290 | out_be32(ipgifg_register, value); |
| 1291 | return 0; |
| 1292 | } |
| 1293 | |
| 1294 | static int init_flow_control_params(u32 automatic_flow_control_mode, |
| 1295 | int rx_flow_control_enable, |
| 1296 | int tx_flow_control_enable, |
| 1297 | u16 pause_period, |
| 1298 | u16 extension_field, |
| 1299 | volatile u32 *upsmr_register, |
| 1300 | volatile u32 *uempr_register, |
| 1301 | volatile u32 *maccfg1_register) |
| 1302 | { |
| 1303 | u32 value = 0; |
| 1304 | |
| 1305 | /* Set UEMPR register */ |
| 1306 | value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT; |
| 1307 | value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT; |
| 1308 | out_be32(uempr_register, value); |
| 1309 | |
| 1310 | /* Set UPSMR register */ |
| 1311 | value = in_be32(upsmr_register); |
| 1312 | value |= automatic_flow_control_mode; |
| 1313 | out_be32(upsmr_register, value); |
| 1314 | |
| 1315 | value = in_be32(maccfg1_register); |
| 1316 | if (rx_flow_control_enable) |
| 1317 | value |= MACCFG1_FLOW_RX; |
| 1318 | if (tx_flow_control_enable) |
| 1319 | value |= MACCFG1_FLOW_TX; |
| 1320 | out_be32(maccfg1_register, value); |
| 1321 | |
| 1322 | return 0; |
| 1323 | } |
| 1324 | |
| 1325 | static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, |
| 1326 | int auto_zero_hardware_statistics, |
| 1327 | volatile u32 *upsmr_register, |
| 1328 | volatile u16 *uescr_register) |
| 1329 | { |
| 1330 | u32 upsmr_value = 0; |
| 1331 | u16 uescr_value = 0; |
| 1332 | /* Enable hardware statistics gathering if requested */ |
| 1333 | if (enable_hardware_statistics) { |
| 1334 | upsmr_value = in_be32(upsmr_register); |
| 1335 | upsmr_value |= UPSMR_HSE; |
| 1336 | out_be32(upsmr_register, upsmr_value); |
| 1337 | } |
| 1338 | |
| 1339 | /* Clear hardware statistics counters */ |
| 1340 | uescr_value = in_be16(uescr_register); |
| 1341 | uescr_value |= UESCR_CLRCNT; |
| 1342 | /* Automatically zero hardware statistics counters on read, |
| 1343 | if requested */ |
| 1344 | if (auto_zero_hardware_statistics) |
| 1345 | uescr_value |= UESCR_AUTOZ; |
| 1346 | out_be16(uescr_register, uescr_value); |
| 1347 | |
| 1348 | return 0; |
| 1349 | } |
| 1350 | |
| 1351 | static int init_firmware_statistics_gathering_mode(int |
| 1352 | enable_tx_firmware_statistics, |
| 1353 | int enable_rx_firmware_statistics, |
| 1354 | volatile u32 *tx_rmon_base_ptr, |
| 1355 | u32 tx_firmware_statistics_structure_address, |
| 1356 | volatile u32 *rx_rmon_base_ptr, |
| 1357 | u32 rx_firmware_statistics_structure_address, |
| 1358 | volatile u16 *temoder_register, |
| 1359 | volatile u32 *remoder_register) |
| 1360 | { |
| 1361 | /* Note: this function does not check if */ |
| 1362 | /* the parameters it receives are NULL */ |
| 1363 | u16 temoder_value; |
| 1364 | u32 remoder_value; |
| 1365 | |
| 1366 | if (enable_tx_firmware_statistics) { |
| 1367 | out_be32(tx_rmon_base_ptr, |
| 1368 | tx_firmware_statistics_structure_address); |
| 1369 | temoder_value = in_be16(temoder_register); |
| 1370 | temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE; |
| 1371 | out_be16(temoder_register, temoder_value); |
| 1372 | } |
| 1373 | |
| 1374 | if (enable_rx_firmware_statistics) { |
| 1375 | out_be32(rx_rmon_base_ptr, |
| 1376 | rx_firmware_statistics_structure_address); |
| 1377 | remoder_value = in_be32(remoder_register); |
| 1378 | remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE; |
| 1379 | out_be32(remoder_register, remoder_value); |
| 1380 | } |
| 1381 | |
| 1382 | return 0; |
| 1383 | } |
| 1384 | |
| 1385 | static int init_mac_station_addr_regs(u8 address_byte_0, |
| 1386 | u8 address_byte_1, |
| 1387 | u8 address_byte_2, |
| 1388 | u8 address_byte_3, |
| 1389 | u8 address_byte_4, |
| 1390 | u8 address_byte_5, |
| 1391 | volatile u32 *macstnaddr1_register, |
| 1392 | volatile u32 *macstnaddr2_register) |
| 1393 | { |
| 1394 | u32 value = 0; |
| 1395 | |
| 1396 | /* Example: for a station address of 0x12345678ABCD, */ |
| 1397 | /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */ |
| 1398 | |
| 1399 | /* MACSTNADDR1 Register: */ |
| 1400 | |
| 1401 | /* 0 7 8 15 */ |
| 1402 | /* station address byte 5 station address byte 4 */ |
| 1403 | /* 16 23 24 31 */ |
| 1404 | /* station address byte 3 station address byte 2 */ |
| 1405 | value |= (u32) ((address_byte_2 << 0) & 0x000000FF); |
| 1406 | value |= (u32) ((address_byte_3 << 8) & 0x0000FF00); |
| 1407 | value |= (u32) ((address_byte_4 << 16) & 0x00FF0000); |
| 1408 | value |= (u32) ((address_byte_5 << 24) & 0xFF000000); |
| 1409 | |
| 1410 | out_be32(macstnaddr1_register, value); |
| 1411 | |
| 1412 | /* MACSTNADDR2 Register: */ |
| 1413 | |
| 1414 | /* 0 7 8 15 */ |
| 1415 | /* station address byte 1 station address byte 0 */ |
| 1416 | /* 16 23 24 31 */ |
| 1417 | /* reserved reserved */ |
| 1418 | value = 0; |
| 1419 | value |= (u32) ((address_byte_0 << 16) & 0x00FF0000); |
| 1420 | value |= (u32) ((address_byte_1 << 24) & 0xFF000000); |
| 1421 | |
| 1422 | out_be32(macstnaddr2_register, value); |
| 1423 | |
| 1424 | return 0; |
| 1425 | } |
| 1426 | |
| 1427 | static int init_mac_duplex_mode(int full_duplex, |
| 1428 | int limited_to_full_duplex, |
| 1429 | volatile u32 *maccfg2_register) |
| 1430 | { |
| 1431 | u32 value = 0; |
| 1432 | |
| 1433 | /* some interfaces must work in full duplex mode */ |
| 1434 | if ((full_duplex == 0) && (limited_to_full_duplex == 1)) |
| 1435 | return -EINVAL; |
| 1436 | |
| 1437 | value = in_be32(maccfg2_register); |
| 1438 | |
| 1439 | if (full_duplex) |
| 1440 | value |= MACCFG2_FDX; |
| 1441 | else |
| 1442 | value &= ~MACCFG2_FDX; |
| 1443 | |
| 1444 | out_be32(maccfg2_register, value); |
| 1445 | return 0; |
| 1446 | } |
| 1447 | |
| 1448 | static int init_check_frame_length_mode(int length_check, |
| 1449 | volatile u32 *maccfg2_register) |
| 1450 | { |
| 1451 | u32 value = 0; |
| 1452 | |
| 1453 | value = in_be32(maccfg2_register); |
| 1454 | |
| 1455 | if (length_check) |
| 1456 | value |= MACCFG2_LC; |
| 1457 | else |
| 1458 | value &= ~MACCFG2_LC; |
| 1459 | |
| 1460 | out_be32(maccfg2_register, value); |
| 1461 | return 0; |
| 1462 | } |
| 1463 | |
| 1464 | static int init_preamble_length(u8 preamble_length, |
| 1465 | volatile u32 *maccfg2_register) |
| 1466 | { |
| 1467 | u32 value = 0; |
| 1468 | |
| 1469 | if ((preamble_length < 3) || (preamble_length > 7)) |
| 1470 | return -EINVAL; |
| 1471 | |
| 1472 | value = in_be32(maccfg2_register); |
| 1473 | value &= ~MACCFG2_PREL_MASK; |
| 1474 | value |= (preamble_length << MACCFG2_PREL_SHIFT); |
| 1475 | out_be32(maccfg2_register, value); |
| 1476 | return 0; |
| 1477 | } |
| 1478 | |
| 1479 | static int init_mii_management_configuration(int reset_mgmt, |
| 1480 | int preamble_supress, |
| 1481 | volatile u32 *miimcfg_register, |
| 1482 | volatile u32 *miimind_register) |
| 1483 | { |
| 1484 | unsigned int timeout = PHY_INIT_TIMEOUT; |
| 1485 | u32 value = 0; |
| 1486 | |
| 1487 | value = in_be32(miimcfg_register); |
| 1488 | if (reset_mgmt) { |
| 1489 | value |= MIIMCFG_RESET_MANAGEMENT; |
| 1490 | out_be32(miimcfg_register, value); |
| 1491 | } |
| 1492 | |
| 1493 | value = 0; |
| 1494 | |
| 1495 | if (preamble_supress) |
| 1496 | value |= MIIMCFG_NO_PREAMBLE; |
| 1497 | |
| 1498 | value |= UCC_GETH_MIIMCFG_MNGMNT_CLC_DIV_INIT; |
| 1499 | out_be32(miimcfg_register, value); |
| 1500 | |
| 1501 | /* Wait until the bus is free */ |
| 1502 | while ((in_be32(miimind_register) & MIIMIND_BUSY) && timeout--) |
| 1503 | cpu_relax(); |
| 1504 | |
| 1505 | if (timeout <= 0) { |
| 1506 | ugeth_err("%s: The MII Bus is stuck!", __FUNCTION__); |
| 1507 | return -ETIMEDOUT; |
| 1508 | } |
| 1509 | |
| 1510 | return 0; |
| 1511 | } |
| 1512 | |
| 1513 | static int init_rx_parameters(int reject_broadcast, |
| 1514 | int receive_short_frames, |
| 1515 | int promiscuous, volatile u32 *upsmr_register) |
| 1516 | { |
| 1517 | u32 value = 0; |
| 1518 | |
| 1519 | value = in_be32(upsmr_register); |
| 1520 | |
| 1521 | if (reject_broadcast) |
| 1522 | value |= UPSMR_BRO; |
| 1523 | else |
| 1524 | value &= ~UPSMR_BRO; |
| 1525 | |
| 1526 | if (receive_short_frames) |
| 1527 | value |= UPSMR_RSH; |
| 1528 | else |
| 1529 | value &= ~UPSMR_RSH; |
| 1530 | |
| 1531 | if (promiscuous) |
| 1532 | value |= UPSMR_PRO; |
| 1533 | else |
| 1534 | value &= ~UPSMR_PRO; |
| 1535 | |
| 1536 | out_be32(upsmr_register, value); |
| 1537 | |
| 1538 | return 0; |
| 1539 | } |
| 1540 | |
| 1541 | static int init_max_rx_buff_len(u16 max_rx_buf_len, |
| 1542 | volatile u16 *mrblr_register) |
| 1543 | { |
| 1544 | /* max_rx_buf_len value must be a multiple of 128 */ |
| 1545 | if ((max_rx_buf_len == 0) |
| 1546 | || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT)) |
| 1547 | return -EINVAL; |
| 1548 | |
| 1549 | out_be16(mrblr_register, max_rx_buf_len); |
| 1550 | return 0; |
| 1551 | } |
| 1552 | |
| 1553 | static int init_min_frame_len(u16 min_frame_length, |
| 1554 | volatile u16 *minflr_register, |
| 1555 | volatile u16 *mrblr_register) |
| 1556 | { |
| 1557 | u16 mrblr_value = 0; |
| 1558 | |
| 1559 | mrblr_value = in_be16(mrblr_register); |
| 1560 | if (min_frame_length >= (mrblr_value - 4)) |
| 1561 | return -EINVAL; |
| 1562 | |
| 1563 | out_be16(minflr_register, min_frame_length); |
| 1564 | return 0; |
| 1565 | } |
| 1566 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1567 | static int adjust_enet_interface(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1568 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1569 | struct ucc_geth_info *ug_info; |
| 1570 | struct ucc_geth *ug_regs; |
| 1571 | struct ucc_fast *uf_regs; |
| 1572 | enum enet_speed speed; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1573 | int ret_val, rpm = 0, tbi = 0, r10m = 0, rmm = |
| 1574 | 0, limited_to_full_duplex = 0; |
| 1575 | u32 upsmr, maccfg2, utbipar, tbiBaseAddress; |
| 1576 | u16 value; |
| 1577 | |
| 1578 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 1579 | |
| 1580 | ug_info = ugeth->ug_info; |
| 1581 | ug_regs = ugeth->ug_regs; |
| 1582 | uf_regs = ugeth->uccf->uf_regs; |
| 1583 | |
| 1584 | /* Analyze enet_interface according to Interface Mode Configuration |
| 1585 | table */ |
| 1586 | ret_val = |
| 1587 | get_interface_details(ug_info->enet_interface, &speed, &r10m, &rmm, |
| 1588 | &rpm, &tbi, &limited_to_full_duplex); |
| 1589 | if (ret_val != 0) { |
| 1590 | ugeth_err |
| 1591 | ("%s: half duplex not supported in requested configuration.", |
| 1592 | __FUNCTION__); |
| 1593 | return ret_val; |
| 1594 | } |
| 1595 | |
| 1596 | /* Set MACCFG2 */ |
| 1597 | maccfg2 = in_be32(&ug_regs->maccfg2); |
| 1598 | maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; |
| 1599 | if ((speed == ENET_SPEED_10BT) || (speed == ENET_SPEED_100BT)) |
| 1600 | maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; |
| 1601 | else if (speed == ENET_SPEED_1000BT) |
| 1602 | maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; |
| 1603 | maccfg2 |= ug_info->padAndCrc; |
| 1604 | out_be32(&ug_regs->maccfg2, maccfg2); |
| 1605 | |
| 1606 | /* Set UPSMR */ |
| 1607 | upsmr = in_be32(&uf_regs->upsmr); |
| 1608 | upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM); |
| 1609 | if (rpm) |
| 1610 | upsmr |= UPSMR_RPM; |
| 1611 | if (r10m) |
| 1612 | upsmr |= UPSMR_R10M; |
| 1613 | if (tbi) |
| 1614 | upsmr |= UPSMR_TBIM; |
| 1615 | if (rmm) |
| 1616 | upsmr |= UPSMR_RMM; |
| 1617 | out_be32(&uf_regs->upsmr, upsmr); |
| 1618 | |
| 1619 | /* Set UTBIPAR */ |
| 1620 | utbipar = in_be32(&ug_regs->utbipar); |
| 1621 | utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; |
| 1622 | if (tbi) |
| 1623 | utbipar |= |
| 1624 | (ug_info->phy_address + |
| 1625 | ugeth->ug_info->uf_info. |
| 1626 | ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT; |
| 1627 | else |
| 1628 | utbipar |= |
| 1629 | (0x10 + |
| 1630 | ugeth->ug_info->uf_info. |
| 1631 | ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT; |
| 1632 | out_be32(&ug_regs->utbipar, utbipar); |
| 1633 | |
| 1634 | /* Disable autonegotiation in tbi mode, because by default it |
| 1635 | comes up in autonegotiation mode. */ |
| 1636 | /* Note that this depends on proper setting in utbipar register. */ |
| 1637 | if (tbi) { |
| 1638 | tbiBaseAddress = in_be32(&ug_regs->utbipar); |
| 1639 | tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK; |
| 1640 | tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT; |
| 1641 | value = |
| 1642 | ugeth->mii_info->mdio_read(ugeth->dev, (u8) tbiBaseAddress, |
| 1643 | ENET_TBI_MII_CR); |
| 1644 | value &= ~0x1000; /* Turn off autonegotiation */ |
| 1645 | ugeth->mii_info->mdio_write(ugeth->dev, (u8) tbiBaseAddress, |
| 1646 | ENET_TBI_MII_CR, value); |
| 1647 | } |
| 1648 | |
| 1649 | ret_val = init_mac_duplex_mode(1, |
| 1650 | limited_to_full_duplex, |
| 1651 | &ug_regs->maccfg2); |
| 1652 | if (ret_val != 0) { |
| 1653 | ugeth_err |
| 1654 | ("%s: half duplex not supported in requested configuration.", |
| 1655 | __FUNCTION__); |
| 1656 | return ret_val; |
| 1657 | } |
| 1658 | |
| 1659 | init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2); |
| 1660 | |
| 1661 | ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2); |
| 1662 | if (ret_val != 0) { |
| 1663 | ugeth_err |
| 1664 | ("%s: Preamble length must be between 3 and 7 inclusive.", |
| 1665 | __FUNCTION__); |
| 1666 | return ret_val; |
| 1667 | } |
| 1668 | |
| 1669 | return 0; |
| 1670 | } |
| 1671 | |
| 1672 | /* Called every time the controller might need to be made |
| 1673 | * aware of new link state. The PHY code conveys this |
| 1674 | * information through variables in the ugeth structure, and this |
| 1675 | * function converts those variables into the appropriate |
| 1676 | * register values, and can bring down the device if needed. |
| 1677 | */ |
| 1678 | static void adjust_link(struct net_device *dev) |
| 1679 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1680 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
| 1681 | struct ucc_geth *ug_regs; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1682 | u32 tempval; |
| 1683 | struct ugeth_mii_info *mii_info = ugeth->mii_info; |
| 1684 | |
| 1685 | ug_regs = ugeth->ug_regs; |
| 1686 | |
| 1687 | if (mii_info->link) { |
| 1688 | /* Now we make sure that we can be in full duplex mode. |
| 1689 | * If not, we operate in half-duplex mode. */ |
| 1690 | if (mii_info->duplex != ugeth->oldduplex) { |
| 1691 | if (!(mii_info->duplex)) { |
| 1692 | tempval = in_be32(&ug_regs->maccfg2); |
| 1693 | tempval &= ~(MACCFG2_FDX); |
| 1694 | out_be32(&ug_regs->maccfg2, tempval); |
| 1695 | |
| 1696 | ugeth_info("%s: Half Duplex", dev->name); |
| 1697 | } else { |
| 1698 | tempval = in_be32(&ug_regs->maccfg2); |
| 1699 | tempval |= MACCFG2_FDX; |
| 1700 | out_be32(&ug_regs->maccfg2, tempval); |
| 1701 | |
| 1702 | ugeth_info("%s: Full Duplex", dev->name); |
| 1703 | } |
| 1704 | |
| 1705 | ugeth->oldduplex = mii_info->duplex; |
| 1706 | } |
| 1707 | |
| 1708 | if (mii_info->speed != ugeth->oldspeed) { |
| 1709 | switch (mii_info->speed) { |
| 1710 | case 1000: |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1711 | #ifdef CONFIG_PPC_MPC836x |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1712 | /* FIXME: This code is for 100Mbs BUG fixing, |
| 1713 | remove this when it is fixed!!! */ |
| 1714 | if (ugeth->ug_info->enet_interface == |
| 1715 | ENET_1000_GMII) |
| 1716 | /* Run the commands which initialize the PHY */ |
| 1717 | { |
| 1718 | tempval = |
| 1719 | (u32) mii_info->mdio_read(ugeth-> |
| 1720 | dev, mii_info->mii_id, 0x1b); |
| 1721 | tempval |= 0x000f; |
| 1722 | mii_info->mdio_write(ugeth->dev, |
| 1723 | mii_info->mii_id, 0x1b, |
| 1724 | (u16) tempval); |
| 1725 | tempval = |
| 1726 | (u32) mii_info->mdio_read(ugeth-> |
| 1727 | dev, mii_info->mii_id, |
| 1728 | MII_BMCR); |
| 1729 | mii_info->mdio_write(ugeth->dev, |
| 1730 | mii_info->mii_id, MII_BMCR, |
| 1731 | (u16) (tempval | BMCR_RESET)); |
| 1732 | } else if (ugeth->ug_info->enet_interface == |
| 1733 | ENET_1000_RGMII) |
| 1734 | /* Run the commands which initialize the PHY */ |
| 1735 | { |
| 1736 | tempval = |
| 1737 | (u32) mii_info->mdio_read(ugeth-> |
| 1738 | dev, mii_info->mii_id, 0x1b); |
| 1739 | tempval = (tempval & ~0x000f) | 0x000b; |
| 1740 | mii_info->mdio_write(ugeth->dev, |
| 1741 | mii_info->mii_id, 0x1b, |
| 1742 | (u16) tempval); |
| 1743 | tempval = |
| 1744 | (u32) mii_info->mdio_read(ugeth-> |
| 1745 | dev, mii_info->mii_id, |
| 1746 | MII_BMCR); |
| 1747 | mii_info->mdio_write(ugeth->dev, |
| 1748 | mii_info->mii_id, MII_BMCR, |
| 1749 | (u16) (tempval | BMCR_RESET)); |
| 1750 | } |
| 1751 | msleep(4000); |
| 1752 | #endif /* CONFIG_MPC8360 */ |
| 1753 | adjust_enet_interface(ugeth); |
| 1754 | break; |
| 1755 | case 100: |
| 1756 | case 10: |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1757 | #ifdef CONFIG_PPC_MPC836x |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1758 | /* FIXME: This code is for 100Mbs BUG fixing, |
| 1759 | remove this lines when it will be fixed!!! */ |
| 1760 | ugeth->ug_info->enet_interface = ENET_100_RGMII; |
| 1761 | tempval = |
| 1762 | (u32) mii_info->mdio_read(ugeth->dev, |
| 1763 | mii_info->mii_id, |
| 1764 | 0x1b); |
| 1765 | tempval = (tempval & ~0x000f) | 0x000b; |
| 1766 | mii_info->mdio_write(ugeth->dev, |
| 1767 | mii_info->mii_id, 0x1b, |
| 1768 | (u16) tempval); |
| 1769 | tempval = |
| 1770 | (u32) mii_info->mdio_read(ugeth->dev, |
| 1771 | mii_info->mii_id, |
| 1772 | MII_BMCR); |
| 1773 | mii_info->mdio_write(ugeth->dev, |
| 1774 | mii_info->mii_id, MII_BMCR, |
| 1775 | (u16) (tempval | |
| 1776 | BMCR_RESET)); |
| 1777 | msleep(4000); |
| 1778 | #endif /* CONFIG_MPC8360 */ |
| 1779 | adjust_enet_interface(ugeth); |
| 1780 | break; |
| 1781 | default: |
| 1782 | ugeth_warn |
| 1783 | ("%s: Ack! Speed (%d) is not 10/100/1000!", |
| 1784 | dev->name, mii_info->speed); |
| 1785 | break; |
| 1786 | } |
| 1787 | |
| 1788 | ugeth_info("%s: Speed %dBT", dev->name, |
| 1789 | mii_info->speed); |
| 1790 | |
| 1791 | ugeth->oldspeed = mii_info->speed; |
| 1792 | } |
| 1793 | |
| 1794 | if (!ugeth->oldlink) { |
| 1795 | ugeth_info("%s: Link is up", dev->name); |
| 1796 | ugeth->oldlink = 1; |
| 1797 | netif_carrier_on(dev); |
| 1798 | netif_schedule(dev); |
| 1799 | } |
| 1800 | } else { |
| 1801 | if (ugeth->oldlink) { |
| 1802 | ugeth_info("%s: Link is down", dev->name); |
| 1803 | ugeth->oldlink = 0; |
| 1804 | ugeth->oldspeed = 0; |
| 1805 | ugeth->oldduplex = -1; |
| 1806 | netif_carrier_off(dev); |
| 1807 | } |
| 1808 | } |
| 1809 | } |
| 1810 | |
| 1811 | /* Configure the PHY for dev. |
| 1812 | * returns 0 if success. -1 if failure |
| 1813 | */ |
| 1814 | static int init_phy(struct net_device *dev) |
| 1815 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1816 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1817 | struct phy_info *curphy; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1818 | struct ucc_mii_mng *mii_regs; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1819 | struct ugeth_mii_info *mii_info; |
| 1820 | int err; |
| 1821 | |
| 1822 | mii_regs = &ugeth->ug_regs->miimng; |
| 1823 | |
| 1824 | ugeth->oldlink = 0; |
| 1825 | ugeth->oldspeed = 0; |
| 1826 | ugeth->oldduplex = -1; |
| 1827 | |
| 1828 | mii_info = kmalloc(sizeof(struct ugeth_mii_info), GFP_KERNEL); |
| 1829 | |
| 1830 | if (NULL == mii_info) { |
| 1831 | ugeth_err("%s: Could not allocate mii_info", dev->name); |
| 1832 | return -ENOMEM; |
| 1833 | } |
| 1834 | |
| 1835 | mii_info->mii_regs = mii_regs; |
| 1836 | mii_info->speed = SPEED_1000; |
| 1837 | mii_info->duplex = DUPLEX_FULL; |
| 1838 | mii_info->pause = 0; |
| 1839 | mii_info->link = 0; |
| 1840 | |
| 1841 | mii_info->advertising = (ADVERTISED_10baseT_Half | |
| 1842 | ADVERTISED_10baseT_Full | |
| 1843 | ADVERTISED_100baseT_Half | |
| 1844 | ADVERTISED_100baseT_Full | |
| 1845 | ADVERTISED_1000baseT_Full); |
| 1846 | mii_info->autoneg = 1; |
| 1847 | |
| 1848 | mii_info->mii_id = ugeth->ug_info->phy_address; |
| 1849 | |
| 1850 | mii_info->dev = dev; |
| 1851 | |
| 1852 | mii_info->mdio_read = &read_phy_reg; |
| 1853 | mii_info->mdio_write = &write_phy_reg; |
| 1854 | |
| 1855 | ugeth->mii_info = mii_info; |
| 1856 | |
| 1857 | spin_lock_irq(&ugeth->lock); |
| 1858 | |
| 1859 | /* Set this UCC to be the master of the MII managment */ |
| 1860 | ucc_set_qe_mux_mii_mng(ugeth->ug_info->uf_info.ucc_num); |
| 1861 | |
| 1862 | if (init_mii_management_configuration(1, |
| 1863 | ugeth->ug_info-> |
| 1864 | miiPreambleSupress, |
| 1865 | &mii_regs->miimcfg, |
| 1866 | &mii_regs->miimind)) { |
| 1867 | ugeth_err("%s: The MII Bus is stuck!", dev->name); |
| 1868 | err = -1; |
| 1869 | goto bus_fail; |
| 1870 | } |
| 1871 | |
| 1872 | spin_unlock_irq(&ugeth->lock); |
| 1873 | |
| 1874 | /* get info for this PHY */ |
| 1875 | curphy = get_phy_info(ugeth->mii_info); |
| 1876 | |
| 1877 | if (curphy == NULL) { |
| 1878 | ugeth_err("%s: No PHY found", dev->name); |
| 1879 | err = -1; |
| 1880 | goto no_phy; |
| 1881 | } |
| 1882 | |
| 1883 | mii_info->phyinfo = curphy; |
| 1884 | |
| 1885 | /* Run the commands which initialize the PHY */ |
| 1886 | if (curphy->init) { |
| 1887 | err = curphy->init(ugeth->mii_info); |
| 1888 | if (err) |
| 1889 | goto phy_init_fail; |
| 1890 | } |
| 1891 | |
| 1892 | return 0; |
| 1893 | |
| 1894 | phy_init_fail: |
| 1895 | no_phy: |
| 1896 | bus_fail: |
| 1897 | kfree(mii_info); |
| 1898 | |
| 1899 | return err; |
| 1900 | } |
| 1901 | |
| 1902 | #ifdef CONFIG_UGETH_TX_ON_DEMOND |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1903 | static int ugeth_transmit_on_demand(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1904 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1905 | struct ucc_fastransmit_on_demand(ugeth->uccf); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1906 | |
| 1907 | return 0; |
| 1908 | } |
| 1909 | #endif |
| 1910 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1911 | static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1912 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1913 | struct ucc_fast_private *uccf; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1914 | u32 cecr_subblock; |
| 1915 | u32 temp; |
| 1916 | |
| 1917 | uccf = ugeth->uccf; |
| 1918 | |
| 1919 | /* Mask GRACEFUL STOP TX interrupt bit and clear it */ |
| 1920 | temp = in_be32(uccf->p_uccm); |
| 1921 | temp &= ~UCCE_GRA; |
| 1922 | out_be32(uccf->p_uccm, temp); |
| 1923 | out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */ |
| 1924 | |
| 1925 | /* Issue host command */ |
| 1926 | cecr_subblock = |
| 1927 | ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); |
| 1928 | qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1929 | QE_CR_PROTOCOL_ETHERNET, 0); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1930 | |
| 1931 | /* Wait for command to complete */ |
| 1932 | do { |
| 1933 | temp = in_be32(uccf->p_ucce); |
| 1934 | } while (!(temp & UCCE_GRA)); |
| 1935 | |
| 1936 | uccf->stopped_tx = 1; |
| 1937 | |
| 1938 | return 0; |
| 1939 | } |
| 1940 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1941 | static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1942 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1943 | struct ucc_fast_private *uccf; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1944 | u32 cecr_subblock; |
| 1945 | u8 temp; |
| 1946 | |
| 1947 | uccf = ugeth->uccf; |
| 1948 | |
| 1949 | /* Clear acknowledge bit */ |
| 1950 | temp = ugeth->p_rx_glbl_pram->rxgstpack; |
| 1951 | temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; |
| 1952 | ugeth->p_rx_glbl_pram->rxgstpack = temp; |
| 1953 | |
| 1954 | /* Keep issuing command and checking acknowledge bit until |
| 1955 | it is asserted, according to spec */ |
| 1956 | do { |
| 1957 | /* Issue host command */ |
| 1958 | cecr_subblock = |
| 1959 | ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info. |
| 1960 | ucc_num); |
| 1961 | qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1962 | QE_CR_PROTOCOL_ETHERNET, 0); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1963 | |
| 1964 | temp = ugeth->p_rx_glbl_pram->rxgstpack; |
| 1965 | } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX)); |
| 1966 | |
| 1967 | uccf->stopped_rx = 1; |
| 1968 | |
| 1969 | return 0; |
| 1970 | } |
| 1971 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1972 | static int ugeth_restart_tx(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1973 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1974 | struct ucc_fast_private *uccf; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1975 | u32 cecr_subblock; |
| 1976 | |
| 1977 | uccf = ugeth->uccf; |
| 1978 | |
| 1979 | cecr_subblock = |
| 1980 | ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1981 | qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1982 | uccf->stopped_tx = 0; |
| 1983 | |
| 1984 | return 0; |
| 1985 | } |
| 1986 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1987 | static int ugeth_restart_rx(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1988 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1989 | struct ucc_fast_private *uccf; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1990 | u32 cecr_subblock; |
| 1991 | |
| 1992 | uccf = ugeth->uccf; |
| 1993 | |
| 1994 | cecr_subblock = |
| 1995 | ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 1996 | qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 1997 | 0); |
| 1998 | uccf->stopped_rx = 0; |
| 1999 | |
| 2000 | return 0; |
| 2001 | } |
| 2002 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2003 | static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2004 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2005 | struct ucc_fast_private *uccf; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2006 | int enabled_tx, enabled_rx; |
| 2007 | |
| 2008 | uccf = ugeth->uccf; |
| 2009 | |
| 2010 | /* check if the UCC number is in range. */ |
| 2011 | if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { |
| 2012 | ugeth_err("%s: ucc_num out of range.", __FUNCTION__); |
| 2013 | return -EINVAL; |
| 2014 | } |
| 2015 | |
| 2016 | enabled_tx = uccf->enabled_tx; |
| 2017 | enabled_rx = uccf->enabled_rx; |
| 2018 | |
| 2019 | /* Get Tx and Rx going again, in case this channel was actively |
| 2020 | disabled. */ |
| 2021 | if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx) |
| 2022 | ugeth_restart_tx(ugeth); |
| 2023 | if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx) |
| 2024 | ugeth_restart_rx(ugeth); |
| 2025 | |
| 2026 | ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */ |
| 2027 | |
| 2028 | return 0; |
| 2029 | |
| 2030 | } |
| 2031 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2032 | static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2033 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2034 | struct ucc_fast_private *uccf; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2035 | |
| 2036 | uccf = ugeth->uccf; |
| 2037 | |
| 2038 | /* check if the UCC number is in range. */ |
| 2039 | if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { |
| 2040 | ugeth_err("%s: ucc_num out of range.", __FUNCTION__); |
| 2041 | return -EINVAL; |
| 2042 | } |
| 2043 | |
| 2044 | /* Stop any transmissions */ |
| 2045 | if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx) |
| 2046 | ugeth_graceful_stop_tx(ugeth); |
| 2047 | |
| 2048 | /* Stop any receptions */ |
| 2049 | if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx) |
| 2050 | ugeth_graceful_stop_rx(ugeth); |
| 2051 | |
| 2052 | ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */ |
| 2053 | |
| 2054 | return 0; |
| 2055 | } |
| 2056 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2057 | static void ugeth_dump_regs(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2058 | { |
| 2059 | #ifdef DEBUG |
| 2060 | ucc_fast_dump_regs(ugeth->uccf); |
| 2061 | dump_regs(ugeth); |
| 2062 | dump_bds(ugeth); |
| 2063 | #endif |
| 2064 | } |
| 2065 | |
| 2066 | #ifdef CONFIG_UGETH_FILTERING |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2067 | static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params * |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2068 | p_UccGethTadParams, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2069 | struct qe_fltr_tad *qe_fltr_tad) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2070 | { |
| 2071 | u16 temp; |
| 2072 | |
| 2073 | /* Zero serialized TAD */ |
| 2074 | memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE); |
| 2075 | |
| 2076 | qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V; /* Must have this */ |
| 2077 | if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode || |
| 2078 | (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) |
| 2079 | || (p_UccGethTadParams->vnontag_op != |
| 2080 | UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP) |
| 2081 | ) |
| 2082 | qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF; |
| 2083 | if (p_UccGethTadParams->reject_frame) |
| 2084 | qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ; |
| 2085 | temp = |
| 2086 | (u16) (((u16) p_UccGethTadParams-> |
| 2087 | vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT); |
| 2088 | qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */ |
| 2089 | |
| 2090 | qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff); /* lower bits */ |
| 2091 | if (p_UccGethTadParams->vnontag_op == |
| 2092 | UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT) |
| 2093 | qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP; |
| 2094 | qe_fltr_tad->serialized[1] |= |
| 2095 | p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT; |
| 2096 | |
| 2097 | qe_fltr_tad->serialized[2] |= |
| 2098 | p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT; |
| 2099 | /* upper bits */ |
| 2100 | qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8); |
| 2101 | /* lower bits */ |
| 2102 | qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff); |
| 2103 | |
| 2104 | return 0; |
| 2105 | } |
| 2106 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2107 | static struct enet_addr_container_t |
| 2108 | *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth, |
| 2109 | struct enet_addr *p_enet_addr) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2110 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2111 | struct enet_addr_container *enet_addr_cont; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2112 | struct list_head *p_lh; |
| 2113 | u16 i, num; |
| 2114 | int32_t j; |
| 2115 | u8 *p_counter; |
| 2116 | |
| 2117 | if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) { |
| 2118 | p_lh = &ugeth->group_hash_q; |
| 2119 | p_counter = &(ugeth->numGroupAddrInHash); |
| 2120 | } else { |
| 2121 | p_lh = &ugeth->ind_hash_q; |
| 2122 | p_counter = &(ugeth->numIndAddrInHash); |
| 2123 | } |
| 2124 | |
| 2125 | if (!p_lh) |
| 2126 | return NULL; |
| 2127 | |
| 2128 | num = *p_counter; |
| 2129 | |
| 2130 | for (i = 0; i < num; i++) { |
| 2131 | enet_addr_cont = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2132 | (struct enet_addr_container *) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2133 | ENET_ADDR_CONT_ENTRY(dequeue(p_lh)); |
| 2134 | for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) { |
| 2135 | if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j]) |
| 2136 | break; |
| 2137 | if (j == 0) |
| 2138 | return enet_addr_cont; /* Found */ |
| 2139 | } |
| 2140 | enqueue(p_lh, &enet_addr_cont->node); /* Put it back */ |
| 2141 | } |
| 2142 | return NULL; |
| 2143 | } |
| 2144 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2145 | static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth, |
| 2146 | struct enet_addr *p_enet_addr) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2147 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2148 | enum ucc_geth_enet_address_recognition_location location; |
| 2149 | struct enet_addr_container *enet_addr_cont; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2150 | struct list_head *p_lh; |
| 2151 | u8 i; |
| 2152 | u32 limit; |
| 2153 | u8 *p_counter; |
| 2154 | |
| 2155 | if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) { |
| 2156 | p_lh = &ugeth->group_hash_q; |
| 2157 | limit = ugeth->ug_info->maxGroupAddrInHash; |
| 2158 | location = |
| 2159 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH; |
| 2160 | p_counter = &(ugeth->numGroupAddrInHash); |
| 2161 | } else { |
| 2162 | p_lh = &ugeth->ind_hash_q; |
| 2163 | limit = ugeth->ug_info->maxIndAddrInHash; |
| 2164 | location = |
| 2165 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH; |
| 2166 | p_counter = &(ugeth->numIndAddrInHash); |
| 2167 | } |
| 2168 | |
| 2169 | if ((enet_addr_cont = |
| 2170 | ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) { |
| 2171 | list_add(p_lh, &enet_addr_cont->node); /* Put it back */ |
| 2172 | return 0; |
| 2173 | } |
| 2174 | if ((!p_lh) || (!(*p_counter < limit))) |
| 2175 | return -EBUSY; |
| 2176 | if (!(enet_addr_cont = get_enet_addr_container())) |
| 2177 | return -ENOMEM; |
| 2178 | for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++) |
| 2179 | (enet_addr_cont->address)[i] = (*p_enet_addr)[i]; |
| 2180 | enet_addr_cont->location = location; |
| 2181 | enqueue(p_lh, &enet_addr_cont->node); /* Put it back */ |
| 2182 | ++(*p_counter); |
| 2183 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2184 | hw_add_addr_in_hash(ugeth, enet_addr_cont->address); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2185 | return 0; |
| 2186 | } |
| 2187 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2188 | static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth, |
| 2189 | struct enet_addr *p_enet_addr) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2190 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2191 | struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt; |
| 2192 | struct enet_addr_container *enet_addr_cont; |
| 2193 | struct ucc_fast_private *uccf; |
| 2194 | enum comm_dir comm_dir; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2195 | u16 i, num; |
| 2196 | struct list_head *p_lh; |
| 2197 | u32 *addr_h, *addr_l; |
| 2198 | u8 *p_counter; |
| 2199 | |
| 2200 | uccf = ugeth->uccf; |
| 2201 | |
| 2202 | p_82xx_addr_filt = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2203 | (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2204 | addressfiltering; |
| 2205 | |
| 2206 | if (! |
| 2207 | (enet_addr_cont = |
| 2208 | ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) |
| 2209 | return -ENOENT; |
| 2210 | |
| 2211 | /* It's been found and removed from the CQ. */ |
| 2212 | /* Now destroy its container */ |
| 2213 | put_enet_addr_container(enet_addr_cont); |
| 2214 | |
| 2215 | if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) { |
| 2216 | addr_h = &(p_82xx_addr_filt->gaddr_h); |
| 2217 | addr_l = &(p_82xx_addr_filt->gaddr_l); |
| 2218 | p_lh = &ugeth->group_hash_q; |
| 2219 | p_counter = &(ugeth->numGroupAddrInHash); |
| 2220 | } else { |
| 2221 | addr_h = &(p_82xx_addr_filt->iaddr_h); |
| 2222 | addr_l = &(p_82xx_addr_filt->iaddr_l); |
| 2223 | p_lh = &ugeth->ind_hash_q; |
| 2224 | p_counter = &(ugeth->numIndAddrInHash); |
| 2225 | } |
| 2226 | |
| 2227 | comm_dir = 0; |
| 2228 | if (uccf->enabled_tx) |
| 2229 | comm_dir |= COMM_DIR_TX; |
| 2230 | if (uccf->enabled_rx) |
| 2231 | comm_dir |= COMM_DIR_RX; |
| 2232 | if (comm_dir) |
| 2233 | ugeth_disable(ugeth, comm_dir); |
| 2234 | |
| 2235 | /* Clear the hash table. */ |
| 2236 | out_be32(addr_h, 0x00000000); |
| 2237 | out_be32(addr_l, 0x00000000); |
| 2238 | |
| 2239 | /* Add all remaining CQ elements back into hash */ |
| 2240 | num = --(*p_counter); |
| 2241 | for (i = 0; i < num; i++) { |
| 2242 | enet_addr_cont = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2243 | (struct enet_addr_container *) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2244 | ENET_ADDR_CONT_ENTRY(dequeue(p_lh)); |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2245 | hw_add_addr_in_hash(ugeth, enet_addr_cont->address); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2246 | enqueue(p_lh, &enet_addr_cont->node); /* Put it back */ |
| 2247 | } |
| 2248 | |
| 2249 | if (comm_dir) |
| 2250 | ugeth_enable(ugeth, comm_dir); |
| 2251 | |
| 2252 | return 0; |
| 2253 | } |
| 2254 | #endif /* CONFIG_UGETH_FILTERING */ |
| 2255 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2256 | static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private * |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2257 | ugeth, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2258 | enum enet_addr_type |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2259 | enet_addr_type) |
| 2260 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2261 | struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt; |
| 2262 | struct ucc_fast_private *uccf; |
| 2263 | enum comm_dir comm_dir; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2264 | struct list_head *p_lh; |
| 2265 | u16 i, num; |
| 2266 | u32 *addr_h, *addr_l; |
| 2267 | u8 *p_counter; |
| 2268 | |
| 2269 | uccf = ugeth->uccf; |
| 2270 | |
| 2271 | p_82xx_addr_filt = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2272 | (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2273 | addressfiltering; |
| 2274 | |
| 2275 | if (enet_addr_type == ENET_ADDR_TYPE_GROUP) { |
| 2276 | addr_h = &(p_82xx_addr_filt->gaddr_h); |
| 2277 | addr_l = &(p_82xx_addr_filt->gaddr_l); |
| 2278 | p_lh = &ugeth->group_hash_q; |
| 2279 | p_counter = &(ugeth->numGroupAddrInHash); |
| 2280 | } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) { |
| 2281 | addr_h = &(p_82xx_addr_filt->iaddr_h); |
| 2282 | addr_l = &(p_82xx_addr_filt->iaddr_l); |
| 2283 | p_lh = &ugeth->ind_hash_q; |
| 2284 | p_counter = &(ugeth->numIndAddrInHash); |
| 2285 | } else |
| 2286 | return -EINVAL; |
| 2287 | |
| 2288 | comm_dir = 0; |
| 2289 | if (uccf->enabled_tx) |
| 2290 | comm_dir |= COMM_DIR_TX; |
| 2291 | if (uccf->enabled_rx) |
| 2292 | comm_dir |= COMM_DIR_RX; |
| 2293 | if (comm_dir) |
| 2294 | ugeth_disable(ugeth, comm_dir); |
| 2295 | |
| 2296 | /* Clear the hash table. */ |
| 2297 | out_be32(addr_h, 0x00000000); |
| 2298 | out_be32(addr_l, 0x00000000); |
| 2299 | |
| 2300 | if (!p_lh) |
| 2301 | return 0; |
| 2302 | |
| 2303 | num = *p_counter; |
| 2304 | |
| 2305 | /* Delete all remaining CQ elements */ |
| 2306 | for (i = 0; i < num; i++) |
| 2307 | put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh))); |
| 2308 | |
| 2309 | *p_counter = 0; |
| 2310 | |
| 2311 | if (comm_dir) |
| 2312 | ugeth_enable(ugeth, comm_dir); |
| 2313 | |
| 2314 | return 0; |
| 2315 | } |
| 2316 | |
| 2317 | #ifdef CONFIG_UGETH_FILTERING |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2318 | static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth, |
| 2319 | struct enet_addr *p_enet_addr, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2320 | u8 paddr_num) |
| 2321 | { |
| 2322 | int i; |
| 2323 | |
| 2324 | if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) |
| 2325 | ugeth_warn |
| 2326 | ("%s: multicast address added to paddr will have no " |
| 2327 | "effect - is this what you wanted?", |
| 2328 | __FUNCTION__); |
| 2329 | |
| 2330 | ugeth->indAddrRegUsed[paddr_num] = 1; /* mark this paddr as used */ |
| 2331 | /* store address in our database */ |
| 2332 | for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++) |
| 2333 | ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i]; |
| 2334 | /* put in hardware */ |
| 2335 | return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num); |
| 2336 | } |
| 2337 | #endif /* CONFIG_UGETH_FILTERING */ |
| 2338 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2339 | static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2340 | u8 paddr_num) |
| 2341 | { |
| 2342 | ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */ |
| 2343 | return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */ |
| 2344 | } |
| 2345 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2346 | static void ucc_geth_memclean(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2347 | { |
| 2348 | u16 i, j; |
| 2349 | u8 *bd; |
| 2350 | |
| 2351 | if (!ugeth) |
| 2352 | return; |
| 2353 | |
| 2354 | if (ugeth->uccf) |
| 2355 | ucc_fast_free(ugeth->uccf); |
| 2356 | |
| 2357 | if (ugeth->p_thread_data_tx) { |
| 2358 | qe_muram_free(ugeth->thread_dat_tx_offset); |
| 2359 | ugeth->p_thread_data_tx = NULL; |
| 2360 | } |
| 2361 | if (ugeth->p_thread_data_rx) { |
| 2362 | qe_muram_free(ugeth->thread_dat_rx_offset); |
| 2363 | ugeth->p_thread_data_rx = NULL; |
| 2364 | } |
| 2365 | if (ugeth->p_exf_glbl_param) { |
| 2366 | qe_muram_free(ugeth->exf_glbl_param_offset); |
| 2367 | ugeth->p_exf_glbl_param = NULL; |
| 2368 | } |
| 2369 | if (ugeth->p_rx_glbl_pram) { |
| 2370 | qe_muram_free(ugeth->rx_glbl_pram_offset); |
| 2371 | ugeth->p_rx_glbl_pram = NULL; |
| 2372 | } |
| 2373 | if (ugeth->p_tx_glbl_pram) { |
| 2374 | qe_muram_free(ugeth->tx_glbl_pram_offset); |
| 2375 | ugeth->p_tx_glbl_pram = NULL; |
| 2376 | } |
| 2377 | if (ugeth->p_send_q_mem_reg) { |
| 2378 | qe_muram_free(ugeth->send_q_mem_reg_offset); |
| 2379 | ugeth->p_send_q_mem_reg = NULL; |
| 2380 | } |
| 2381 | if (ugeth->p_scheduler) { |
| 2382 | qe_muram_free(ugeth->scheduler_offset); |
| 2383 | ugeth->p_scheduler = NULL; |
| 2384 | } |
| 2385 | if (ugeth->p_tx_fw_statistics_pram) { |
| 2386 | qe_muram_free(ugeth->tx_fw_statistics_pram_offset); |
| 2387 | ugeth->p_tx_fw_statistics_pram = NULL; |
| 2388 | } |
| 2389 | if (ugeth->p_rx_fw_statistics_pram) { |
| 2390 | qe_muram_free(ugeth->rx_fw_statistics_pram_offset); |
| 2391 | ugeth->p_rx_fw_statistics_pram = NULL; |
| 2392 | } |
| 2393 | if (ugeth->p_rx_irq_coalescing_tbl) { |
| 2394 | qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset); |
| 2395 | ugeth->p_rx_irq_coalescing_tbl = NULL; |
| 2396 | } |
| 2397 | if (ugeth->p_rx_bd_qs_tbl) { |
| 2398 | qe_muram_free(ugeth->rx_bd_qs_tbl_offset); |
| 2399 | ugeth->p_rx_bd_qs_tbl = NULL; |
| 2400 | } |
| 2401 | if (ugeth->p_init_enet_param_shadow) { |
| 2402 | return_init_enet_entries(ugeth, |
| 2403 | &(ugeth->p_init_enet_param_shadow-> |
| 2404 | rxthread[0]), |
| 2405 | ENET_INIT_PARAM_MAX_ENTRIES_RX, |
| 2406 | ugeth->ug_info->riscRx, 1); |
| 2407 | return_init_enet_entries(ugeth, |
| 2408 | &(ugeth->p_init_enet_param_shadow-> |
| 2409 | txthread[0]), |
| 2410 | ENET_INIT_PARAM_MAX_ENTRIES_TX, |
| 2411 | ugeth->ug_info->riscTx, 0); |
| 2412 | kfree(ugeth->p_init_enet_param_shadow); |
| 2413 | ugeth->p_init_enet_param_shadow = NULL; |
| 2414 | } |
| 2415 | for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { |
| 2416 | bd = ugeth->p_tx_bd_ring[i]; |
| 2417 | for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) { |
| 2418 | if (ugeth->tx_skbuff[i][j]) { |
| 2419 | dma_unmap_single(NULL, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2420 | ((qe_bd_t *)bd)->buf, |
| 2421 | (in_be32((u32 *)bd) & |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2422 | BD_LENGTH_MASK), |
| 2423 | DMA_TO_DEVICE); |
| 2424 | dev_kfree_skb_any(ugeth->tx_skbuff[i][j]); |
| 2425 | ugeth->tx_skbuff[i][j] = NULL; |
| 2426 | } |
| 2427 | } |
| 2428 | |
| 2429 | kfree(ugeth->tx_skbuff[i]); |
| 2430 | |
| 2431 | if (ugeth->p_tx_bd_ring[i]) { |
| 2432 | if (ugeth->ug_info->uf_info.bd_mem_part == |
| 2433 | MEM_PART_SYSTEM) |
| 2434 | kfree((void *)ugeth->tx_bd_ring_offset[i]); |
| 2435 | else if (ugeth->ug_info->uf_info.bd_mem_part == |
| 2436 | MEM_PART_MURAM) |
| 2437 | qe_muram_free(ugeth->tx_bd_ring_offset[i]); |
| 2438 | ugeth->p_tx_bd_ring[i] = NULL; |
| 2439 | } |
| 2440 | } |
| 2441 | for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { |
| 2442 | if (ugeth->p_rx_bd_ring[i]) { |
| 2443 | /* Return existing data buffers in ring */ |
| 2444 | bd = ugeth->p_rx_bd_ring[i]; |
| 2445 | for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) { |
| 2446 | if (ugeth->rx_skbuff[i][j]) { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2447 | dma_unmap_single(NULL, |
| 2448 | ((struct qe_bd *)bd)->buf, |
| 2449 | ugeth->ug_info-> |
| 2450 | uf_info.max_rx_buf_length + |
| 2451 | UCC_GETH_RX_DATA_BUF_ALIGNMENT, |
| 2452 | DMA_FROM_DEVICE); |
| 2453 | dev_kfree_skb_any( |
| 2454 | ugeth->rx_skbuff[i][j]); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2455 | ugeth->rx_skbuff[i][j] = NULL; |
| 2456 | } |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2457 | bd += sizeof(struct qe_bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2458 | } |
| 2459 | |
| 2460 | kfree(ugeth->rx_skbuff[i]); |
| 2461 | |
| 2462 | if (ugeth->ug_info->uf_info.bd_mem_part == |
| 2463 | MEM_PART_SYSTEM) |
| 2464 | kfree((void *)ugeth->rx_bd_ring_offset[i]); |
| 2465 | else if (ugeth->ug_info->uf_info.bd_mem_part == |
| 2466 | MEM_PART_MURAM) |
| 2467 | qe_muram_free(ugeth->rx_bd_ring_offset[i]); |
| 2468 | ugeth->p_rx_bd_ring[i] = NULL; |
| 2469 | } |
| 2470 | } |
| 2471 | while (!list_empty(&ugeth->group_hash_q)) |
| 2472 | put_enet_addr_container(ENET_ADDR_CONT_ENTRY |
| 2473 | (dequeue(&ugeth->group_hash_q))); |
| 2474 | while (!list_empty(&ugeth->ind_hash_q)) |
| 2475 | put_enet_addr_container(ENET_ADDR_CONT_ENTRY |
| 2476 | (dequeue(&ugeth->ind_hash_q))); |
| 2477 | |
| 2478 | } |
| 2479 | |
| 2480 | static void ucc_geth_set_multi(struct net_device *dev) |
| 2481 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2482 | struct ucc_geth_private *ugeth; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2483 | struct dev_mc_list *dmi; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2484 | struct ucc_fast *uf_regs; |
| 2485 | struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt; |
| 2486 | u8 tempaddr[6]; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2487 | u8 *mcptr, *tdptr; |
| 2488 | int i, j; |
| 2489 | |
| 2490 | ugeth = netdev_priv(dev); |
| 2491 | |
| 2492 | uf_regs = ugeth->uccf->uf_regs; |
| 2493 | |
| 2494 | if (dev->flags & IFF_PROMISC) { |
| 2495 | |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2496 | uf_regs->upsmr |= UPSMR_PRO; |
| 2497 | |
| 2498 | } else { |
| 2499 | |
| 2500 | uf_regs->upsmr &= ~UPSMR_PRO; |
| 2501 | |
| 2502 | p_82xx_addr_filt = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2503 | (struct ucc_geth_82xx_address_filtering_pram *) ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2504 | p_rx_glbl_pram->addressfiltering; |
| 2505 | |
| 2506 | if (dev->flags & IFF_ALLMULTI) { |
| 2507 | /* Catch all multicast addresses, so set the |
| 2508 | * filter to all 1's. |
| 2509 | */ |
| 2510 | out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff); |
| 2511 | out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff); |
| 2512 | } else { |
| 2513 | /* Clear filter and add the addresses in the list. |
| 2514 | */ |
| 2515 | out_be32(&p_82xx_addr_filt->gaddr_h, 0x0); |
| 2516 | out_be32(&p_82xx_addr_filt->gaddr_l, 0x0); |
| 2517 | |
| 2518 | dmi = dev->mc_list; |
| 2519 | |
| 2520 | for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) { |
| 2521 | |
| 2522 | /* Only support group multicast for now. |
| 2523 | */ |
| 2524 | if (!(dmi->dmi_addr[0] & 1)) |
| 2525 | continue; |
| 2526 | |
| 2527 | /* The address in dmi_addr is LSB first, |
| 2528 | * and taddr is MSB first. We have to |
| 2529 | * copy bytes MSB first from dmi_addr. |
| 2530 | */ |
| 2531 | mcptr = (u8 *) dmi->dmi_addr + 5; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2532 | tdptr = (u8 *) tempaddr; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2533 | for (j = 0; j < 6; j++) |
| 2534 | *tdptr++ = *mcptr--; |
| 2535 | |
| 2536 | /* Ask CPM to run CRC and set bit in |
| 2537 | * filter mask. |
| 2538 | */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2539 | hw_add_addr_in_hash(ugeth, tempaddr); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2540 | } |
| 2541 | } |
| 2542 | } |
| 2543 | } |
| 2544 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2545 | static void ucc_geth_stop(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2546 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2547 | struct ucc_geth *ug_regs = ugeth->ug_regs; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2548 | u32 tempval; |
| 2549 | |
| 2550 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 2551 | |
| 2552 | /* Disable the controller */ |
| 2553 | ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); |
| 2554 | |
| 2555 | /* Tell the kernel the link is down */ |
| 2556 | ugeth->mii_info->link = 0; |
| 2557 | adjust_link(ugeth->dev); |
| 2558 | |
| 2559 | /* Mask all interrupts */ |
| 2560 | out_be32(ugeth->uccf->p_ucce, 0x00000000); |
| 2561 | |
| 2562 | /* Clear all interrupts */ |
| 2563 | out_be32(ugeth->uccf->p_ucce, 0xffffffff); |
| 2564 | |
| 2565 | /* Disable Rx and Tx */ |
| 2566 | tempval = in_be32(&ug_regs->maccfg1); |
| 2567 | tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); |
| 2568 | out_be32(&ug_regs->maccfg1, tempval); |
| 2569 | |
| 2570 | if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) { |
| 2571 | /* Clear any pending interrupts */ |
| 2572 | mii_clear_phy_interrupt(ugeth->mii_info); |
| 2573 | |
| 2574 | /* Disable PHY Interrupts */ |
| 2575 | mii_configure_phy_interrupt(ugeth->mii_info, |
| 2576 | MII_INTERRUPT_DISABLED); |
| 2577 | } |
| 2578 | |
| 2579 | free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev); |
| 2580 | |
| 2581 | if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) { |
| 2582 | free_irq(ugeth->ug_info->phy_interrupt, ugeth->dev); |
| 2583 | } else { |
| 2584 | del_timer_sync(&ugeth->phy_info_timer); |
| 2585 | } |
| 2586 | |
| 2587 | ucc_geth_memclean(ugeth); |
| 2588 | } |
| 2589 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2590 | static int ucc_geth_startup(struct ucc_geth_private *ugeth) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2591 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2592 | struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt; |
| 2593 | struct ucc_geth_init_pram *p_init_enet_pram; |
| 2594 | struct ucc_fast_private *uccf; |
| 2595 | struct ucc_geth_info *ug_info; |
| 2596 | struct ucc_fast_info *uf_info; |
| 2597 | struct ucc_fast *uf_regs; |
| 2598 | struct ucc_geth *ug_regs; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2599 | int ret_val = -EINVAL; |
| 2600 | u32 remoder = UCC_GETH_REMODER_INIT; |
| 2601 | u32 init_enet_pram_offset, cecr_subblock, command, maccfg1; |
| 2602 | u32 ifstat, i, j, size, l2qt, l3qt, length; |
| 2603 | u16 temoder = UCC_GETH_TEMODER_INIT; |
| 2604 | u16 test; |
| 2605 | u8 function_code = 0; |
| 2606 | u8 *bd, *endOfRing; |
| 2607 | u8 numThreadsRxNumerical, numThreadsTxNumerical; |
| 2608 | |
| 2609 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 2610 | |
| 2611 | ug_info = ugeth->ug_info; |
| 2612 | uf_info = &ug_info->uf_info; |
| 2613 | |
| 2614 | if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) || |
| 2615 | (uf_info->bd_mem_part == MEM_PART_MURAM))) { |
| 2616 | ugeth_err("%s: Bad memory partition value.", __FUNCTION__); |
| 2617 | return -EINVAL; |
| 2618 | } |
| 2619 | |
| 2620 | /* Rx BD lengths */ |
| 2621 | for (i = 0; i < ug_info->numQueuesRx; i++) { |
| 2622 | if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) || |
| 2623 | (ug_info->bdRingLenRx[i] % |
| 2624 | UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) { |
| 2625 | ugeth_err |
| 2626 | ("%s: Rx BD ring length must be multiple of 4," |
| 2627 | " no smaller than 8.", __FUNCTION__); |
| 2628 | return -EINVAL; |
| 2629 | } |
| 2630 | } |
| 2631 | |
| 2632 | /* Tx BD lengths */ |
| 2633 | for (i = 0; i < ug_info->numQueuesTx; i++) { |
| 2634 | if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) { |
| 2635 | ugeth_err |
| 2636 | ("%s: Tx BD ring length must be no smaller than 2.", |
| 2637 | __FUNCTION__); |
| 2638 | return -EINVAL; |
| 2639 | } |
| 2640 | } |
| 2641 | |
| 2642 | /* mrblr */ |
| 2643 | if ((uf_info->max_rx_buf_length == 0) || |
| 2644 | (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) { |
| 2645 | ugeth_err |
| 2646 | ("%s: max_rx_buf_length must be non-zero multiple of 128.", |
| 2647 | __FUNCTION__); |
| 2648 | return -EINVAL; |
| 2649 | } |
| 2650 | |
| 2651 | /* num Tx queues */ |
| 2652 | if (ug_info->numQueuesTx > NUM_TX_QUEUES) { |
| 2653 | ugeth_err("%s: number of tx queues too large.", __FUNCTION__); |
| 2654 | return -EINVAL; |
| 2655 | } |
| 2656 | |
| 2657 | /* num Rx queues */ |
| 2658 | if (ug_info->numQueuesRx > NUM_RX_QUEUES) { |
| 2659 | ugeth_err("%s: number of rx queues too large.", __FUNCTION__); |
| 2660 | return -EINVAL; |
| 2661 | } |
| 2662 | |
| 2663 | /* l2qt */ |
| 2664 | for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) { |
| 2665 | if (ug_info->l2qt[i] >= ug_info->numQueuesRx) { |
| 2666 | ugeth_err |
| 2667 | ("%s: VLAN priority table entry must not be" |
| 2668 | " larger than number of Rx queues.", |
| 2669 | __FUNCTION__); |
| 2670 | return -EINVAL; |
| 2671 | } |
| 2672 | } |
| 2673 | |
| 2674 | /* l3qt */ |
| 2675 | for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) { |
| 2676 | if (ug_info->l3qt[i] >= ug_info->numQueuesRx) { |
| 2677 | ugeth_err |
| 2678 | ("%s: IP priority table entry must not be" |
| 2679 | " larger than number of Rx queues.", |
| 2680 | __FUNCTION__); |
| 2681 | return -EINVAL; |
| 2682 | } |
| 2683 | } |
| 2684 | |
| 2685 | if (ug_info->cam && !ug_info->ecamptr) { |
| 2686 | ugeth_err("%s: If cam mode is chosen, must supply cam ptr.", |
| 2687 | __FUNCTION__); |
| 2688 | return -EINVAL; |
| 2689 | } |
| 2690 | |
| 2691 | if ((ug_info->numStationAddresses != |
| 2692 | UCC_GETH_NUM_OF_STATION_ADDRESSES_1) |
| 2693 | && ug_info->rxExtendedFiltering) { |
| 2694 | ugeth_err("%s: Number of station addresses greater than 1 " |
| 2695 | "not allowed in extended parsing mode.", |
| 2696 | __FUNCTION__); |
| 2697 | return -EINVAL; |
| 2698 | } |
| 2699 | |
| 2700 | /* Generate uccm_mask for receive */ |
| 2701 | uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ |
| 2702 | for (i = 0; i < ug_info->numQueuesRx; i++) |
| 2703 | uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i); |
| 2704 | |
| 2705 | for (i = 0; i < ug_info->numQueuesTx; i++) |
| 2706 | uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i); |
| 2707 | /* Initialize the general fast UCC block. */ |
| 2708 | if (ucc_fast_init(uf_info, &uccf)) { |
| 2709 | ugeth_err("%s: Failed to init uccf.", __FUNCTION__); |
| 2710 | ucc_geth_memclean(ugeth); |
| 2711 | return -ENOMEM; |
| 2712 | } |
| 2713 | ugeth->uccf = uccf; |
| 2714 | |
| 2715 | switch (ug_info->numThreadsRx) { |
| 2716 | case UCC_GETH_NUM_OF_THREADS_1: |
| 2717 | numThreadsRxNumerical = 1; |
| 2718 | break; |
| 2719 | case UCC_GETH_NUM_OF_THREADS_2: |
| 2720 | numThreadsRxNumerical = 2; |
| 2721 | break; |
| 2722 | case UCC_GETH_NUM_OF_THREADS_4: |
| 2723 | numThreadsRxNumerical = 4; |
| 2724 | break; |
| 2725 | case UCC_GETH_NUM_OF_THREADS_6: |
| 2726 | numThreadsRxNumerical = 6; |
| 2727 | break; |
| 2728 | case UCC_GETH_NUM_OF_THREADS_8: |
| 2729 | numThreadsRxNumerical = 8; |
| 2730 | break; |
| 2731 | default: |
| 2732 | ugeth_err("%s: Bad number of Rx threads value.", __FUNCTION__); |
| 2733 | ucc_geth_memclean(ugeth); |
| 2734 | return -EINVAL; |
| 2735 | break; |
| 2736 | } |
| 2737 | |
| 2738 | switch (ug_info->numThreadsTx) { |
| 2739 | case UCC_GETH_NUM_OF_THREADS_1: |
| 2740 | numThreadsTxNumerical = 1; |
| 2741 | break; |
| 2742 | case UCC_GETH_NUM_OF_THREADS_2: |
| 2743 | numThreadsTxNumerical = 2; |
| 2744 | break; |
| 2745 | case UCC_GETH_NUM_OF_THREADS_4: |
| 2746 | numThreadsTxNumerical = 4; |
| 2747 | break; |
| 2748 | case UCC_GETH_NUM_OF_THREADS_6: |
| 2749 | numThreadsTxNumerical = 6; |
| 2750 | break; |
| 2751 | case UCC_GETH_NUM_OF_THREADS_8: |
| 2752 | numThreadsTxNumerical = 8; |
| 2753 | break; |
| 2754 | default: |
| 2755 | ugeth_err("%s: Bad number of Tx threads value.", __FUNCTION__); |
| 2756 | ucc_geth_memclean(ugeth); |
| 2757 | return -EINVAL; |
| 2758 | break; |
| 2759 | } |
| 2760 | |
| 2761 | /* Calculate rx_extended_features */ |
| 2762 | ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck || |
| 2763 | ug_info->ipAddressAlignment || |
| 2764 | (ug_info->numStationAddresses != |
| 2765 | UCC_GETH_NUM_OF_STATION_ADDRESSES_1); |
| 2766 | |
| 2767 | ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features || |
| 2768 | (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) |
| 2769 | || (ug_info->vlanOperationNonTagged != |
| 2770 | UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP); |
| 2771 | |
| 2772 | uf_regs = uccf->uf_regs; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2773 | ug_regs = (struct ucc_geth *) (uccf->uf_regs); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2774 | ugeth->ug_regs = ug_regs; |
| 2775 | |
| 2776 | init_default_reg_vals(&uf_regs->upsmr, |
| 2777 | &ug_regs->maccfg1, &ug_regs->maccfg2); |
| 2778 | |
| 2779 | /* Set UPSMR */ |
| 2780 | /* For more details see the hardware spec. */ |
| 2781 | init_rx_parameters(ug_info->bro, |
| 2782 | ug_info->rsh, ug_info->pro, &uf_regs->upsmr); |
| 2783 | |
| 2784 | /* We're going to ignore other registers for now, */ |
| 2785 | /* except as needed to get up and running */ |
| 2786 | |
| 2787 | /* Set MACCFG1 */ |
| 2788 | /* For more details see the hardware spec. */ |
| 2789 | init_flow_control_params(ug_info->aufc, |
| 2790 | ug_info->receiveFlowControl, |
| 2791 | 1, |
| 2792 | ug_info->pausePeriod, |
| 2793 | ug_info->extensionField, |
| 2794 | &uf_regs->upsmr, |
| 2795 | &ug_regs->uempr, &ug_regs->maccfg1); |
| 2796 | |
| 2797 | maccfg1 = in_be32(&ug_regs->maccfg1); |
| 2798 | maccfg1 |= MACCFG1_ENABLE_RX; |
| 2799 | maccfg1 |= MACCFG1_ENABLE_TX; |
| 2800 | out_be32(&ug_regs->maccfg1, maccfg1); |
| 2801 | |
| 2802 | /* Set IPGIFG */ |
| 2803 | /* For more details see the hardware spec. */ |
| 2804 | ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1, |
| 2805 | ug_info->nonBackToBackIfgPart2, |
| 2806 | ug_info-> |
| 2807 | miminumInterFrameGapEnforcement, |
| 2808 | ug_info->backToBackInterFrameGap, |
| 2809 | &ug_regs->ipgifg); |
| 2810 | if (ret_val != 0) { |
| 2811 | ugeth_err("%s: IPGIFG initialization parameter too large.", |
| 2812 | __FUNCTION__); |
| 2813 | ucc_geth_memclean(ugeth); |
| 2814 | return ret_val; |
| 2815 | } |
| 2816 | |
| 2817 | /* Set HAFDUP */ |
| 2818 | /* For more details see the hardware spec. */ |
| 2819 | ret_val = init_half_duplex_params(ug_info->altBeb, |
| 2820 | ug_info->backPressureNoBackoff, |
| 2821 | ug_info->noBackoff, |
| 2822 | ug_info->excessDefer, |
| 2823 | ug_info->altBebTruncation, |
| 2824 | ug_info->maxRetransmission, |
| 2825 | ug_info->collisionWindow, |
| 2826 | &ug_regs->hafdup); |
| 2827 | if (ret_val != 0) { |
| 2828 | ugeth_err("%s: Half Duplex initialization parameter too large.", |
| 2829 | __FUNCTION__); |
| 2830 | ucc_geth_memclean(ugeth); |
| 2831 | return ret_val; |
| 2832 | } |
| 2833 | |
| 2834 | /* Set IFSTAT */ |
| 2835 | /* For more details see the hardware spec. */ |
| 2836 | /* Read only - resets upon read */ |
| 2837 | ifstat = in_be32(&ug_regs->ifstat); |
| 2838 | |
| 2839 | /* Clear UEMPR */ |
| 2840 | /* For more details see the hardware spec. */ |
| 2841 | out_be32(&ug_regs->uempr, 0); |
| 2842 | |
| 2843 | /* Set UESCR */ |
| 2844 | /* For more details see the hardware spec. */ |
| 2845 | init_hw_statistics_gathering_mode((ug_info->statisticsMode & |
| 2846 | UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE), |
| 2847 | 0, &uf_regs->upsmr, &ug_regs->uescr); |
| 2848 | |
| 2849 | /* Allocate Tx bds */ |
| 2850 | for (j = 0; j < ug_info->numQueuesTx; j++) { |
| 2851 | /* Allocate in multiple of |
| 2852 | UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT, |
| 2853 | according to spec */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2854 | length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2855 | / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) |
| 2856 | * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2857 | if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) % |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2858 | UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) |
| 2859 | length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; |
| 2860 | if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { |
| 2861 | u32 align = 4; |
| 2862 | if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4) |
| 2863 | align = UCC_GETH_TX_BD_RING_ALIGNMENT; |
| 2864 | ugeth->tx_bd_ring_offset[j] = |
| 2865 | (u32) (kmalloc((u32) (length + align), |
| 2866 | GFP_KERNEL)); |
| 2867 | if (ugeth->tx_bd_ring_offset[j] != 0) |
| 2868 | ugeth->p_tx_bd_ring[j] = |
| 2869 | (void*)((ugeth->tx_bd_ring_offset[j] + |
| 2870 | align) & ~(align - 1)); |
| 2871 | } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { |
| 2872 | ugeth->tx_bd_ring_offset[j] = |
| 2873 | qe_muram_alloc(length, |
| 2874 | UCC_GETH_TX_BD_RING_ALIGNMENT); |
| 2875 | if (!IS_MURAM_ERR(ugeth->tx_bd_ring_offset[j])) |
| 2876 | ugeth->p_tx_bd_ring[j] = |
| 2877 | (u8 *) qe_muram_addr(ugeth-> |
| 2878 | tx_bd_ring_offset[j]); |
| 2879 | } |
| 2880 | if (!ugeth->p_tx_bd_ring[j]) { |
| 2881 | ugeth_err |
| 2882 | ("%s: Can not allocate memory for Tx bd rings.", |
| 2883 | __FUNCTION__); |
| 2884 | ucc_geth_memclean(ugeth); |
| 2885 | return -ENOMEM; |
| 2886 | } |
| 2887 | /* Zero unused end of bd ring, according to spec */ |
| 2888 | memset(ugeth->p_tx_bd_ring[j] + |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2889 | ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0, |
| 2890 | length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2891 | } |
| 2892 | |
| 2893 | /* Allocate Rx bds */ |
| 2894 | for (j = 0; j < ug_info->numQueuesRx; j++) { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2895 | length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2896 | if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { |
| 2897 | u32 align = 4; |
| 2898 | if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4) |
| 2899 | align = UCC_GETH_RX_BD_RING_ALIGNMENT; |
| 2900 | ugeth->rx_bd_ring_offset[j] = |
| 2901 | (u32) (kmalloc((u32) (length + align), GFP_KERNEL)); |
| 2902 | if (ugeth->rx_bd_ring_offset[j] != 0) |
| 2903 | ugeth->p_rx_bd_ring[j] = |
| 2904 | (void*)((ugeth->rx_bd_ring_offset[j] + |
| 2905 | align) & ~(align - 1)); |
| 2906 | } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { |
| 2907 | ugeth->rx_bd_ring_offset[j] = |
| 2908 | qe_muram_alloc(length, |
| 2909 | UCC_GETH_RX_BD_RING_ALIGNMENT); |
| 2910 | if (!IS_MURAM_ERR(ugeth->rx_bd_ring_offset[j])) |
| 2911 | ugeth->p_rx_bd_ring[j] = |
| 2912 | (u8 *) qe_muram_addr(ugeth-> |
| 2913 | rx_bd_ring_offset[j]); |
| 2914 | } |
| 2915 | if (!ugeth->p_rx_bd_ring[j]) { |
| 2916 | ugeth_err |
| 2917 | ("%s: Can not allocate memory for Rx bd rings.", |
| 2918 | __FUNCTION__); |
| 2919 | ucc_geth_memclean(ugeth); |
| 2920 | return -ENOMEM; |
| 2921 | } |
| 2922 | } |
| 2923 | |
| 2924 | /* Init Tx bds */ |
| 2925 | for (j = 0; j < ug_info->numQueuesTx; j++) { |
| 2926 | /* Setup the skbuff rings */ |
| 2927 | ugeth->tx_skbuff[j] = |
| 2928 | (struct sk_buff **)kmalloc(sizeof(struct sk_buff *) * |
| 2929 | ugeth->ug_info->bdRingLenTx[j], |
| 2930 | GFP_KERNEL); |
| 2931 | |
| 2932 | if (ugeth->tx_skbuff[j] == NULL) { |
| 2933 | ugeth_err("%s: Could not allocate tx_skbuff", |
| 2934 | __FUNCTION__); |
| 2935 | ucc_geth_memclean(ugeth); |
| 2936 | return -ENOMEM; |
| 2937 | } |
| 2938 | |
| 2939 | for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++) |
| 2940 | ugeth->tx_skbuff[j][i] = NULL; |
| 2941 | |
| 2942 | ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0; |
| 2943 | bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j]; |
| 2944 | for (i = 0; i < ug_info->bdRingLenTx[j]; i++) { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2945 | /* clear bd buffer */ |
| 2946 | out_be32(&((struct qe_bd *)bd)->buf, 0); |
| 2947 | /* set bd status and length */ |
| 2948 | out_be32((u32 *)bd, 0); |
| 2949 | bd += sizeof(struct qe_bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2950 | } |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2951 | bd -= sizeof(struct qe_bd); |
| 2952 | /* set bd status and length */ |
| 2953 | out_be32((u32 *)bd, T_W); /* for last BD set Wrap bit */ |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2954 | } |
| 2955 | |
| 2956 | /* Init Rx bds */ |
| 2957 | for (j = 0; j < ug_info->numQueuesRx; j++) { |
| 2958 | /* Setup the skbuff rings */ |
| 2959 | ugeth->rx_skbuff[j] = |
| 2960 | (struct sk_buff **)kmalloc(sizeof(struct sk_buff *) * |
| 2961 | ugeth->ug_info->bdRingLenRx[j], |
| 2962 | GFP_KERNEL); |
| 2963 | |
| 2964 | if (ugeth->rx_skbuff[j] == NULL) { |
| 2965 | ugeth_err("%s: Could not allocate rx_skbuff", |
| 2966 | __FUNCTION__); |
| 2967 | ucc_geth_memclean(ugeth); |
| 2968 | return -ENOMEM; |
| 2969 | } |
| 2970 | |
| 2971 | for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++) |
| 2972 | ugeth->rx_skbuff[j][i] = NULL; |
| 2973 | |
| 2974 | ugeth->skb_currx[j] = 0; |
| 2975 | bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j]; |
| 2976 | for (i = 0; i < ug_info->bdRingLenRx[j]; i++) { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2977 | /* set bd status and length */ |
| 2978 | out_be32((u32 *)bd, R_I); |
| 2979 | /* clear bd buffer */ |
| 2980 | out_be32(&((struct qe_bd *)bd)->buf, 0); |
| 2981 | bd += sizeof(struct qe_bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2982 | } |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2983 | bd -= sizeof(struct qe_bd); |
| 2984 | /* set bd status and length */ |
| 2985 | out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */ |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2986 | } |
| 2987 | |
| 2988 | /* |
| 2989 | * Global PRAM |
| 2990 | */ |
| 2991 | /* Tx global PRAM */ |
| 2992 | /* Allocate global tx parameter RAM page */ |
| 2993 | ugeth->tx_glbl_pram_offset = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 2994 | qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 2995 | UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT); |
| 2996 | if (IS_MURAM_ERR(ugeth->tx_glbl_pram_offset)) { |
| 2997 | ugeth_err |
| 2998 | ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.", |
| 2999 | __FUNCTION__); |
| 3000 | ucc_geth_memclean(ugeth); |
| 3001 | return -ENOMEM; |
| 3002 | } |
| 3003 | ugeth->p_tx_glbl_pram = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3004 | (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3005 | tx_glbl_pram_offset); |
| 3006 | /* Zero out p_tx_glbl_pram */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3007 | memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3008 | |
| 3009 | /* Fill global PRAM */ |
| 3010 | |
| 3011 | /* TQPTR */ |
| 3012 | /* Size varies with number of Tx threads */ |
| 3013 | ugeth->thread_dat_tx_offset = |
| 3014 | qe_muram_alloc(numThreadsTxNumerical * |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3015 | sizeof(struct ucc_geth_thread_data_tx) + |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3016 | 32 * (numThreadsTxNumerical == 1), |
| 3017 | UCC_GETH_THREAD_DATA_ALIGNMENT); |
| 3018 | if (IS_MURAM_ERR(ugeth->thread_dat_tx_offset)) { |
| 3019 | ugeth_err |
| 3020 | ("%s: Can not allocate DPRAM memory for p_thread_data_tx.", |
| 3021 | __FUNCTION__); |
| 3022 | ucc_geth_memclean(ugeth); |
| 3023 | return -ENOMEM; |
| 3024 | } |
| 3025 | |
| 3026 | ugeth->p_thread_data_tx = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3027 | (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3028 | thread_dat_tx_offset); |
| 3029 | out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset); |
| 3030 | |
| 3031 | /* vtagtable */ |
| 3032 | for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++) |
| 3033 | out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i], |
| 3034 | ug_info->vtagtable[i]); |
| 3035 | |
| 3036 | /* iphoffset */ |
| 3037 | for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++) |
| 3038 | ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i]; |
| 3039 | |
| 3040 | /* SQPTR */ |
| 3041 | /* Size varies with number of Tx queues */ |
| 3042 | ugeth->send_q_mem_reg_offset = |
| 3043 | qe_muram_alloc(ug_info->numQueuesTx * |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3044 | sizeof(struct ucc_geth_send_queue_qd), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3045 | UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); |
| 3046 | if (IS_MURAM_ERR(ugeth->send_q_mem_reg_offset)) { |
| 3047 | ugeth_err |
| 3048 | ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.", |
| 3049 | __FUNCTION__); |
| 3050 | ucc_geth_memclean(ugeth); |
| 3051 | return -ENOMEM; |
| 3052 | } |
| 3053 | |
| 3054 | ugeth->p_send_q_mem_reg = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3055 | (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3056 | send_q_mem_reg_offset); |
| 3057 | out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset); |
| 3058 | |
| 3059 | /* Setup the table */ |
| 3060 | /* Assume BD rings are already established */ |
| 3061 | for (i = 0; i < ug_info->numQueuesTx; i++) { |
| 3062 | endOfRing = |
| 3063 | ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] - |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3064 | 1) * sizeof(struct qe_bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3065 | if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { |
| 3066 | out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, |
| 3067 | (u32) virt_to_phys(ugeth->p_tx_bd_ring[i])); |
| 3068 | out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. |
| 3069 | last_bd_completed_address, |
| 3070 | (u32) virt_to_phys(endOfRing)); |
| 3071 | } else if (ugeth->ug_info->uf_info.bd_mem_part == |
| 3072 | MEM_PART_MURAM) { |
| 3073 | out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, |
| 3074 | (u32) immrbar_virt_to_phys(ugeth-> |
| 3075 | p_tx_bd_ring[i])); |
| 3076 | out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. |
| 3077 | last_bd_completed_address, |
| 3078 | (u32) immrbar_virt_to_phys(endOfRing)); |
| 3079 | } |
| 3080 | } |
| 3081 | |
| 3082 | /* schedulerbasepointer */ |
| 3083 | |
| 3084 | if (ug_info->numQueuesTx > 1) { |
| 3085 | /* scheduler exists only if more than 1 tx queue */ |
| 3086 | ugeth->scheduler_offset = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3087 | qe_muram_alloc(sizeof(struct ucc_geth_scheduler), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3088 | UCC_GETH_SCHEDULER_ALIGNMENT); |
| 3089 | if (IS_MURAM_ERR(ugeth->scheduler_offset)) { |
| 3090 | ugeth_err |
| 3091 | ("%s: Can not allocate DPRAM memory for p_scheduler.", |
| 3092 | __FUNCTION__); |
| 3093 | ucc_geth_memclean(ugeth); |
| 3094 | return -ENOMEM; |
| 3095 | } |
| 3096 | |
| 3097 | ugeth->p_scheduler = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3098 | (struct ucc_geth_scheduler *) qe_muram_addr(ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3099 | scheduler_offset); |
| 3100 | out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer, |
| 3101 | ugeth->scheduler_offset); |
| 3102 | /* Zero out p_scheduler */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3103 | memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3104 | |
| 3105 | /* Set values in scheduler */ |
| 3106 | out_be32(&ugeth->p_scheduler->mblinterval, |
| 3107 | ug_info->mblinterval); |
| 3108 | out_be16(&ugeth->p_scheduler->nortsrbytetime, |
| 3109 | ug_info->nortsrbytetime); |
| 3110 | ugeth->p_scheduler->fracsiz = ug_info->fracsiz; |
| 3111 | ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq; |
| 3112 | ugeth->p_scheduler->txasap = ug_info->txasap; |
| 3113 | ugeth->p_scheduler->extrabw = ug_info->extrabw; |
| 3114 | for (i = 0; i < NUM_TX_QUEUES; i++) |
| 3115 | ugeth->p_scheduler->weightfactor[i] = |
| 3116 | ug_info->weightfactor[i]; |
| 3117 | |
| 3118 | /* Set pointers to cpucount registers in scheduler */ |
| 3119 | ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0); |
| 3120 | ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1); |
| 3121 | ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2); |
| 3122 | ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3); |
| 3123 | ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4); |
| 3124 | ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5); |
| 3125 | ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6); |
| 3126 | ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7); |
| 3127 | } |
| 3128 | |
| 3129 | /* schedulerbasepointer */ |
| 3130 | /* TxRMON_PTR (statistics) */ |
| 3131 | if (ug_info-> |
| 3132 | statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) { |
| 3133 | ugeth->tx_fw_statistics_pram_offset = |
| 3134 | qe_muram_alloc(sizeof |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3135 | (struct ucc_geth_tx_firmware_statistics_pram), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3136 | UCC_GETH_TX_STATISTICS_ALIGNMENT); |
| 3137 | if (IS_MURAM_ERR(ugeth->tx_fw_statistics_pram_offset)) { |
| 3138 | ugeth_err |
| 3139 | ("%s: Can not allocate DPRAM memory for" |
| 3140 | " p_tx_fw_statistics_pram.", __FUNCTION__); |
| 3141 | ucc_geth_memclean(ugeth); |
| 3142 | return -ENOMEM; |
| 3143 | } |
| 3144 | ugeth->p_tx_fw_statistics_pram = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3145 | (struct ucc_geth_tx_firmware_statistics_pram *) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3146 | qe_muram_addr(ugeth->tx_fw_statistics_pram_offset); |
| 3147 | /* Zero out p_tx_fw_statistics_pram */ |
| 3148 | memset(ugeth->p_tx_fw_statistics_pram, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3149 | 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3150 | } |
| 3151 | |
| 3152 | /* temoder */ |
| 3153 | /* Already has speed set */ |
| 3154 | |
| 3155 | if (ug_info->numQueuesTx > 1) |
| 3156 | temoder |= TEMODER_SCHEDULER_ENABLE; |
| 3157 | if (ug_info->ipCheckSumGenerate) |
| 3158 | temoder |= TEMODER_IP_CHECKSUM_GENERATE; |
| 3159 | temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT); |
| 3160 | out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder); |
| 3161 | |
| 3162 | test = in_be16(&ugeth->p_tx_glbl_pram->temoder); |
| 3163 | |
| 3164 | /* Function code register value to be used later */ |
| 3165 | function_code = QE_BMR_BYTE_ORDER_BO_MOT | UCC_FAST_FUNCTION_CODE_GBL; |
| 3166 | /* Required for QE */ |
| 3167 | |
| 3168 | /* function code register */ |
| 3169 | out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24); |
| 3170 | |
| 3171 | /* Rx global PRAM */ |
| 3172 | /* Allocate global rx parameter RAM page */ |
| 3173 | ugeth->rx_glbl_pram_offset = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3174 | qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3175 | UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT); |
| 3176 | if (IS_MURAM_ERR(ugeth->rx_glbl_pram_offset)) { |
| 3177 | ugeth_err |
| 3178 | ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.", |
| 3179 | __FUNCTION__); |
| 3180 | ucc_geth_memclean(ugeth); |
| 3181 | return -ENOMEM; |
| 3182 | } |
| 3183 | ugeth->p_rx_glbl_pram = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3184 | (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3185 | rx_glbl_pram_offset); |
| 3186 | /* Zero out p_rx_glbl_pram */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3187 | memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3188 | |
| 3189 | /* Fill global PRAM */ |
| 3190 | |
| 3191 | /* RQPTR */ |
| 3192 | /* Size varies with number of Rx threads */ |
| 3193 | ugeth->thread_dat_rx_offset = |
| 3194 | qe_muram_alloc(numThreadsRxNumerical * |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3195 | sizeof(struct ucc_geth_thread_data_rx), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3196 | UCC_GETH_THREAD_DATA_ALIGNMENT); |
| 3197 | if (IS_MURAM_ERR(ugeth->thread_dat_rx_offset)) { |
| 3198 | ugeth_err |
| 3199 | ("%s: Can not allocate DPRAM memory for p_thread_data_rx.", |
| 3200 | __FUNCTION__); |
| 3201 | ucc_geth_memclean(ugeth); |
| 3202 | return -ENOMEM; |
| 3203 | } |
| 3204 | |
| 3205 | ugeth->p_thread_data_rx = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3206 | (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3207 | thread_dat_rx_offset); |
| 3208 | out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset); |
| 3209 | |
| 3210 | /* typeorlen */ |
| 3211 | out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen); |
| 3212 | |
| 3213 | /* rxrmonbaseptr (statistics) */ |
| 3214 | if (ug_info-> |
| 3215 | statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) { |
| 3216 | ugeth->rx_fw_statistics_pram_offset = |
| 3217 | qe_muram_alloc(sizeof |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3218 | (struct ucc_geth_rx_firmware_statistics_pram), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3219 | UCC_GETH_RX_STATISTICS_ALIGNMENT); |
| 3220 | if (IS_MURAM_ERR(ugeth->rx_fw_statistics_pram_offset)) { |
| 3221 | ugeth_err |
| 3222 | ("%s: Can not allocate DPRAM memory for" |
| 3223 | " p_rx_fw_statistics_pram.", __FUNCTION__); |
| 3224 | ucc_geth_memclean(ugeth); |
| 3225 | return -ENOMEM; |
| 3226 | } |
| 3227 | ugeth->p_rx_fw_statistics_pram = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3228 | (struct ucc_geth_rx_firmware_statistics_pram *) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3229 | qe_muram_addr(ugeth->rx_fw_statistics_pram_offset); |
| 3230 | /* Zero out p_rx_fw_statistics_pram */ |
| 3231 | memset(ugeth->p_rx_fw_statistics_pram, 0, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3232 | sizeof(struct ucc_geth_rx_firmware_statistics_pram)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3233 | } |
| 3234 | |
| 3235 | /* intCoalescingPtr */ |
| 3236 | |
| 3237 | /* Size varies with number of Rx queues */ |
| 3238 | ugeth->rx_irq_coalescing_tbl_offset = |
| 3239 | qe_muram_alloc(ug_info->numQueuesRx * |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3240 | sizeof(struct ucc_geth_rx_interrupt_coalescing_entry), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3241 | UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT); |
| 3242 | if (IS_MURAM_ERR(ugeth->rx_irq_coalescing_tbl_offset)) { |
| 3243 | ugeth_err |
| 3244 | ("%s: Can not allocate DPRAM memory for" |
| 3245 | " p_rx_irq_coalescing_tbl.", __FUNCTION__); |
| 3246 | ucc_geth_memclean(ugeth); |
| 3247 | return -ENOMEM; |
| 3248 | } |
| 3249 | |
| 3250 | ugeth->p_rx_irq_coalescing_tbl = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3251 | (struct ucc_geth_rx_interrupt_coalescing_table *) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3252 | qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset); |
| 3253 | out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr, |
| 3254 | ugeth->rx_irq_coalescing_tbl_offset); |
| 3255 | |
| 3256 | /* Fill interrupt coalescing table */ |
| 3257 | for (i = 0; i < ug_info->numQueuesRx; i++) { |
| 3258 | out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. |
| 3259 | interruptcoalescingmaxvalue, |
| 3260 | ug_info->interruptcoalescingmaxvalue[i]); |
| 3261 | out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. |
| 3262 | interruptcoalescingcounter, |
| 3263 | ug_info->interruptcoalescingmaxvalue[i]); |
| 3264 | } |
| 3265 | |
| 3266 | /* MRBLR */ |
| 3267 | init_max_rx_buff_len(uf_info->max_rx_buf_length, |
| 3268 | &ugeth->p_rx_glbl_pram->mrblr); |
| 3269 | /* MFLR */ |
| 3270 | out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength); |
| 3271 | /* MINFLR */ |
| 3272 | init_min_frame_len(ug_info->minFrameLength, |
| 3273 | &ugeth->p_rx_glbl_pram->minflr, |
| 3274 | &ugeth->p_rx_glbl_pram->mrblr); |
| 3275 | /* MAXD1 */ |
| 3276 | out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length); |
| 3277 | /* MAXD2 */ |
| 3278 | out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length); |
| 3279 | |
| 3280 | /* l2qt */ |
| 3281 | l2qt = 0; |
| 3282 | for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) |
| 3283 | l2qt |= (ug_info->l2qt[i] << (28 - 4 * i)); |
| 3284 | out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt); |
| 3285 | |
| 3286 | /* l3qt */ |
| 3287 | for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) { |
| 3288 | l3qt = 0; |
| 3289 | for (i = 0; i < 8; i++) |
| 3290 | l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i)); |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3291 | out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3292 | } |
| 3293 | |
| 3294 | /* vlantype */ |
| 3295 | out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype); |
| 3296 | |
| 3297 | /* vlantci */ |
| 3298 | out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci); |
| 3299 | |
| 3300 | /* ecamptr */ |
| 3301 | out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr); |
| 3302 | |
| 3303 | /* RBDQPTR */ |
| 3304 | /* Size varies with number of Rx queues */ |
| 3305 | ugeth->rx_bd_qs_tbl_offset = |
| 3306 | qe_muram_alloc(ug_info->numQueuesRx * |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3307 | (sizeof(struct ucc_geth_rx_bd_queues_entry) + |
| 3308 | sizeof(struct ucc_geth_rx_prefetched_bds)), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3309 | UCC_GETH_RX_BD_QUEUES_ALIGNMENT); |
| 3310 | if (IS_MURAM_ERR(ugeth->rx_bd_qs_tbl_offset)) { |
| 3311 | ugeth_err |
| 3312 | ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.", |
| 3313 | __FUNCTION__); |
| 3314 | ucc_geth_memclean(ugeth); |
| 3315 | return -ENOMEM; |
| 3316 | } |
| 3317 | |
| 3318 | ugeth->p_rx_bd_qs_tbl = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3319 | (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3320 | rx_bd_qs_tbl_offset); |
| 3321 | out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset); |
| 3322 | /* Zero out p_rx_bd_qs_tbl */ |
| 3323 | memset(ugeth->p_rx_bd_qs_tbl, |
| 3324 | 0, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3325 | ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) + |
| 3326 | sizeof(struct ucc_geth_rx_prefetched_bds))); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3327 | |
| 3328 | /* Setup the table */ |
| 3329 | /* Assume BD rings are already established */ |
| 3330 | for (i = 0; i < ug_info->numQueuesRx; i++) { |
| 3331 | if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { |
| 3332 | out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, |
| 3333 | (u32) virt_to_phys(ugeth->p_rx_bd_ring[i])); |
| 3334 | } else if (ugeth->ug_info->uf_info.bd_mem_part == |
| 3335 | MEM_PART_MURAM) { |
| 3336 | out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, |
| 3337 | (u32) immrbar_virt_to_phys(ugeth-> |
| 3338 | p_rx_bd_ring[i])); |
| 3339 | } |
| 3340 | /* rest of fields handled by QE */ |
| 3341 | } |
| 3342 | |
| 3343 | /* remoder */ |
| 3344 | /* Already has speed set */ |
| 3345 | |
| 3346 | if (ugeth->rx_extended_features) |
| 3347 | remoder |= REMODER_RX_EXTENDED_FEATURES; |
| 3348 | if (ug_info->rxExtendedFiltering) |
| 3349 | remoder |= REMODER_RX_EXTENDED_FILTERING; |
| 3350 | if (ug_info->dynamicMaxFrameLength) |
| 3351 | remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH; |
| 3352 | if (ug_info->dynamicMinFrameLength) |
| 3353 | remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH; |
| 3354 | remoder |= |
| 3355 | ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT; |
| 3356 | remoder |= |
| 3357 | ug_info-> |
| 3358 | vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT; |
| 3359 | remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT; |
| 3360 | remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT); |
| 3361 | if (ug_info->ipCheckSumCheck) |
| 3362 | remoder |= REMODER_IP_CHECKSUM_CHECK; |
| 3363 | if (ug_info->ipAddressAlignment) |
| 3364 | remoder |= REMODER_IP_ADDRESS_ALIGNMENT; |
| 3365 | out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder); |
| 3366 | |
| 3367 | /* Note that this function must be called */ |
| 3368 | /* ONLY AFTER p_tx_fw_statistics_pram */ |
| 3369 | /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */ |
| 3370 | init_firmware_statistics_gathering_mode((ug_info-> |
| 3371 | statisticsMode & |
| 3372 | UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX), |
| 3373 | (ug_info->statisticsMode & |
| 3374 | UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX), |
| 3375 | &ugeth->p_tx_glbl_pram->txrmonbaseptr, |
| 3376 | ugeth->tx_fw_statistics_pram_offset, |
| 3377 | &ugeth->p_rx_glbl_pram->rxrmonbaseptr, |
| 3378 | ugeth->rx_fw_statistics_pram_offset, |
| 3379 | &ugeth->p_tx_glbl_pram->temoder, |
| 3380 | &ugeth->p_rx_glbl_pram->remoder); |
| 3381 | |
| 3382 | /* function code register */ |
| 3383 | ugeth->p_rx_glbl_pram->rstate = function_code; |
| 3384 | |
| 3385 | /* initialize extended filtering */ |
| 3386 | if (ug_info->rxExtendedFiltering) { |
| 3387 | if (!ug_info->extendedFilteringChainPointer) { |
| 3388 | ugeth_err("%s: Null Extended Filtering Chain Pointer.", |
| 3389 | __FUNCTION__); |
| 3390 | ucc_geth_memclean(ugeth); |
| 3391 | return -EINVAL; |
| 3392 | } |
| 3393 | |
| 3394 | /* Allocate memory for extended filtering Mode Global |
| 3395 | Parameters */ |
| 3396 | ugeth->exf_glbl_param_offset = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3397 | qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3398 | UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT); |
| 3399 | if (IS_MURAM_ERR(ugeth->exf_glbl_param_offset)) { |
| 3400 | ugeth_err |
| 3401 | ("%s: Can not allocate DPRAM memory for" |
| 3402 | " p_exf_glbl_param.", __FUNCTION__); |
| 3403 | ucc_geth_memclean(ugeth); |
| 3404 | return -ENOMEM; |
| 3405 | } |
| 3406 | |
| 3407 | ugeth->p_exf_glbl_param = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3408 | (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3409 | exf_glbl_param_offset); |
| 3410 | out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam, |
| 3411 | ugeth->exf_glbl_param_offset); |
| 3412 | out_be32(&ugeth->p_exf_glbl_param->l2pcdptr, |
| 3413 | (u32) ug_info->extendedFilteringChainPointer); |
| 3414 | |
| 3415 | } else { /* initialize 82xx style address filtering */ |
| 3416 | |
| 3417 | /* Init individual address recognition registers to disabled */ |
| 3418 | |
| 3419 | for (j = 0; j < NUM_OF_PADDRS; j++) |
| 3420 | ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j); |
| 3421 | |
| 3422 | /* Create CQs for hash tables */ |
| 3423 | if (ug_info->maxGroupAddrInHash > 0) { |
| 3424 | INIT_LIST_HEAD(&ugeth->group_hash_q); |
| 3425 | } |
| 3426 | if (ug_info->maxIndAddrInHash > 0) { |
| 3427 | INIT_LIST_HEAD(&ugeth->ind_hash_q); |
| 3428 | } |
| 3429 | p_82xx_addr_filt = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3430 | (struct ucc_geth_82xx_address_filtering_pram *) ugeth-> |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3431 | p_rx_glbl_pram->addressfiltering; |
| 3432 | |
| 3433 | ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, |
| 3434 | ENET_ADDR_TYPE_GROUP); |
| 3435 | ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, |
| 3436 | ENET_ADDR_TYPE_INDIVIDUAL); |
| 3437 | } |
| 3438 | |
| 3439 | /* |
| 3440 | * Initialize UCC at QE level |
| 3441 | */ |
| 3442 | |
| 3443 | command = QE_INIT_TX_RX; |
| 3444 | |
| 3445 | /* Allocate shadow InitEnet command parameter structure. |
| 3446 | * This is needed because after the InitEnet command is executed, |
| 3447 | * the structure in DPRAM is released, because DPRAM is a premium |
| 3448 | * resource. |
| 3449 | * This shadow structure keeps a copy of what was done so that the |
| 3450 | * allocated resources can be released when the channel is freed. |
| 3451 | */ |
| 3452 | if (!(ugeth->p_init_enet_param_shadow = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3453 | (struct ucc_geth_init_pram *) kmalloc(sizeof(struct ucc_geth_init_pram), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3454 | GFP_KERNEL))) { |
| 3455 | ugeth_err |
| 3456 | ("%s: Can not allocate memory for" |
| 3457 | " p_UccInitEnetParamShadows.", __FUNCTION__); |
| 3458 | ucc_geth_memclean(ugeth); |
| 3459 | return -ENOMEM; |
| 3460 | } |
| 3461 | /* Zero out *p_init_enet_param_shadow */ |
| 3462 | memset((char *)ugeth->p_init_enet_param_shadow, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3463 | 0, sizeof(struct ucc_geth_init_pram)); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3464 | |
| 3465 | /* Fill shadow InitEnet command parameter structure */ |
| 3466 | |
| 3467 | ugeth->p_init_enet_param_shadow->resinit1 = |
| 3468 | ENET_INIT_PARAM_MAGIC_RES_INIT1; |
| 3469 | ugeth->p_init_enet_param_shadow->resinit2 = |
| 3470 | ENET_INIT_PARAM_MAGIC_RES_INIT2; |
| 3471 | ugeth->p_init_enet_param_shadow->resinit3 = |
| 3472 | ENET_INIT_PARAM_MAGIC_RES_INIT3; |
| 3473 | ugeth->p_init_enet_param_shadow->resinit4 = |
| 3474 | ENET_INIT_PARAM_MAGIC_RES_INIT4; |
| 3475 | ugeth->p_init_enet_param_shadow->resinit5 = |
| 3476 | ENET_INIT_PARAM_MAGIC_RES_INIT5; |
| 3477 | ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= |
| 3478 | ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT; |
| 3479 | ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= |
| 3480 | ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT; |
| 3481 | |
| 3482 | ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= |
| 3483 | ugeth->rx_glbl_pram_offset | ug_info->riscRx; |
| 3484 | if ((ug_info->largestexternallookupkeysize != |
| 3485 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) |
| 3486 | && (ug_info->largestexternallookupkeysize != |
| 3487 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) |
| 3488 | && (ug_info->largestexternallookupkeysize != |
| 3489 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) { |
| 3490 | ugeth_err("%s: Invalid largest External Lookup Key Size.", |
| 3491 | __FUNCTION__); |
| 3492 | ucc_geth_memclean(ugeth); |
| 3493 | return -EINVAL; |
| 3494 | } |
| 3495 | ugeth->p_init_enet_param_shadow->largestexternallookupkeysize = |
| 3496 | ug_info->largestexternallookupkeysize; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3497 | size = sizeof(struct ucc_geth_thread_rx_pram); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3498 | if (ug_info->rxExtendedFiltering) { |
| 3499 | size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; |
| 3500 | if (ug_info->largestexternallookupkeysize == |
| 3501 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) |
| 3502 | size += |
| 3503 | THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; |
| 3504 | if (ug_info->largestexternallookupkeysize == |
| 3505 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) |
| 3506 | size += |
| 3507 | THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; |
| 3508 | } |
| 3509 | |
| 3510 | if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth-> |
| 3511 | p_init_enet_param_shadow->rxthread[0]), |
| 3512 | (u8) (numThreadsRxNumerical + 1) |
| 3513 | /* Rx needs one extra for terminator */ |
| 3514 | , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT, |
| 3515 | ug_info->riscRx, 1)) != 0) { |
| 3516 | ugeth_err("%s: Can not fill p_init_enet_param_shadow.", |
| 3517 | __FUNCTION__); |
| 3518 | ucc_geth_memclean(ugeth); |
| 3519 | return ret_val; |
| 3520 | } |
| 3521 | |
| 3522 | ugeth->p_init_enet_param_shadow->txglobal = |
| 3523 | ugeth->tx_glbl_pram_offset | ug_info->riscTx; |
| 3524 | if ((ret_val = |
| 3525 | fill_init_enet_entries(ugeth, |
| 3526 | &(ugeth->p_init_enet_param_shadow-> |
| 3527 | txthread[0]), numThreadsTxNumerical, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3528 | sizeof(struct ucc_geth_thread_tx_pram), |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3529 | UCC_GETH_THREAD_TX_PRAM_ALIGNMENT, |
| 3530 | ug_info->riscTx, 0)) != 0) { |
| 3531 | ugeth_err("%s: Can not fill p_init_enet_param_shadow.", |
| 3532 | __FUNCTION__); |
| 3533 | ucc_geth_memclean(ugeth); |
| 3534 | return ret_val; |
| 3535 | } |
| 3536 | |
| 3537 | /* Load Rx bds with buffers */ |
| 3538 | for (i = 0; i < ug_info->numQueuesRx; i++) { |
| 3539 | if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) { |
| 3540 | ugeth_err("%s: Can not fill Rx bds with buffers.", |
| 3541 | __FUNCTION__); |
| 3542 | ucc_geth_memclean(ugeth); |
| 3543 | return ret_val; |
| 3544 | } |
| 3545 | } |
| 3546 | |
| 3547 | /* Allocate InitEnet command parameter structure */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3548 | init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3549 | if (IS_MURAM_ERR(init_enet_pram_offset)) { |
| 3550 | ugeth_err |
| 3551 | ("%s: Can not allocate DPRAM memory for p_init_enet_pram.", |
| 3552 | __FUNCTION__); |
| 3553 | ucc_geth_memclean(ugeth); |
| 3554 | return -ENOMEM; |
| 3555 | } |
| 3556 | p_init_enet_pram = |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3557 | (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3558 | |
| 3559 | /* Copy shadow InitEnet command parameter structure into PRAM */ |
| 3560 | p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1; |
| 3561 | p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2; |
| 3562 | p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3; |
| 3563 | p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4; |
| 3564 | out_be16(&p_init_enet_pram->resinit5, |
| 3565 | ugeth->p_init_enet_param_shadow->resinit5); |
| 3566 | p_init_enet_pram->largestexternallookupkeysize = |
| 3567 | ugeth->p_init_enet_param_shadow->largestexternallookupkeysize; |
| 3568 | out_be32(&p_init_enet_pram->rgftgfrxglobal, |
| 3569 | ugeth->p_init_enet_param_shadow->rgftgfrxglobal); |
| 3570 | for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++) |
| 3571 | out_be32(&p_init_enet_pram->rxthread[i], |
| 3572 | ugeth->p_init_enet_param_shadow->rxthread[i]); |
| 3573 | out_be32(&p_init_enet_pram->txglobal, |
| 3574 | ugeth->p_init_enet_param_shadow->txglobal); |
| 3575 | for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++) |
| 3576 | out_be32(&p_init_enet_pram->txthread[i], |
| 3577 | ugeth->p_init_enet_param_shadow->txthread[i]); |
| 3578 | |
| 3579 | /* Issue QE command */ |
| 3580 | cecr_subblock = |
| 3581 | ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3582 | qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3583 | init_enet_pram_offset); |
| 3584 | |
| 3585 | /* Free InitEnet command parameter */ |
| 3586 | qe_muram_free(init_enet_pram_offset); |
| 3587 | |
| 3588 | return 0; |
| 3589 | } |
| 3590 | |
| 3591 | /* returns a net_device_stats structure pointer */ |
| 3592 | static struct net_device_stats *ucc_geth_get_stats(struct net_device *dev) |
| 3593 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3594 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3595 | |
| 3596 | return &(ugeth->stats); |
| 3597 | } |
| 3598 | |
| 3599 | /* ucc_geth_timeout gets called when a packet has not been |
| 3600 | * transmitted after a set amount of time. |
| 3601 | * For now, assume that clearing out all the structures, and |
| 3602 | * starting over will fix the problem. */ |
| 3603 | static void ucc_geth_timeout(struct net_device *dev) |
| 3604 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3605 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3606 | |
| 3607 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 3608 | |
| 3609 | ugeth->stats.tx_errors++; |
| 3610 | |
| 3611 | ugeth_dump_regs(ugeth); |
| 3612 | |
| 3613 | if (dev->flags & IFF_UP) { |
| 3614 | ucc_geth_stop(ugeth); |
| 3615 | ucc_geth_startup(ugeth); |
| 3616 | } |
| 3617 | |
| 3618 | netif_schedule(dev); |
| 3619 | } |
| 3620 | |
| 3621 | /* This is called by the kernel when a frame is ready for transmission. */ |
| 3622 | /* It is pointed to by the dev->hard_start_xmit function pointer */ |
| 3623 | static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 3624 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3625 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3626 | u8 *bd; /* BD pointer */ |
| 3627 | u32 bd_status; |
| 3628 | u8 txQ = 0; |
| 3629 | |
| 3630 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 3631 | |
| 3632 | spin_lock_irq(&ugeth->lock); |
| 3633 | |
| 3634 | ugeth->stats.tx_bytes += skb->len; |
| 3635 | |
| 3636 | /* Start from the next BD that should be filled */ |
| 3637 | bd = ugeth->txBd[txQ]; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3638 | bd_status = in_be32((u32 *)bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3639 | /* Save the skb pointer so we can free it later */ |
| 3640 | ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb; |
| 3641 | |
| 3642 | /* Update the current skb pointer (wrapping if this was the last) */ |
| 3643 | ugeth->skb_curtx[txQ] = |
| 3644 | (ugeth->skb_curtx[txQ] + |
| 3645 | 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); |
| 3646 | |
| 3647 | /* set up the buffer descriptor */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3648 | out_be32(&((struct qe_bd *)bd)->buf, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3649 | dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE)); |
| 3650 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3651 | /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */ |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3652 | |
| 3653 | bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len; |
| 3654 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3655 | /* set bd status and length */ |
| 3656 | out_be32((u32 *)bd, bd_status); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3657 | |
| 3658 | dev->trans_start = jiffies; |
| 3659 | |
| 3660 | /* Move to next BD in the ring */ |
| 3661 | if (!(bd_status & T_W)) |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3662 | ugeth->txBd[txQ] = bd + sizeof(struct qe_bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3663 | else |
| 3664 | ugeth->txBd[txQ] = ugeth->p_tx_bd_ring[txQ]; |
| 3665 | |
| 3666 | /* If the next BD still needs to be cleaned up, then the bds |
| 3667 | are full. We need to tell the kernel to stop sending us stuff. */ |
| 3668 | if (bd == ugeth->confBd[txQ]) { |
| 3669 | if (!netif_queue_stopped(dev)) |
| 3670 | netif_stop_queue(dev); |
| 3671 | } |
| 3672 | |
| 3673 | if (ugeth->p_scheduler) { |
| 3674 | ugeth->cpucount[txQ]++; |
| 3675 | /* Indicate to QE that there are more Tx bds ready for |
| 3676 | transmission */ |
| 3677 | /* This is done by writing a running counter of the bd |
| 3678 | count to the scheduler PRAM. */ |
| 3679 | out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]); |
| 3680 | } |
| 3681 | |
| 3682 | spin_unlock_irq(&ugeth->lock); |
| 3683 | |
| 3684 | return 0; |
| 3685 | } |
| 3686 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3687 | static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3688 | { |
| 3689 | struct sk_buff *skb; |
| 3690 | u8 *bd; |
| 3691 | u16 length, howmany = 0; |
| 3692 | u32 bd_status; |
| 3693 | u8 *bdBuffer; |
| 3694 | |
| 3695 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 3696 | |
| 3697 | spin_lock(&ugeth->lock); |
| 3698 | /* collect received buffers */ |
| 3699 | bd = ugeth->rxBd[rxQ]; |
| 3700 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3701 | bd_status = in_be32((u32 *)bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3702 | |
| 3703 | /* while there are received buffers and BD is full (~R_E) */ |
| 3704 | while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3705 | bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3706 | length = (u16) ((bd_status & BD_LENGTH_MASK) - 4); |
| 3707 | skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]]; |
| 3708 | |
| 3709 | /* determine whether buffer is first, last, first and last |
| 3710 | (single buffer frame) or middle (not first and not last) */ |
| 3711 | if (!skb || |
| 3712 | (!(bd_status & (R_F | R_L))) || |
| 3713 | (bd_status & R_ERRORS_FATAL)) { |
| 3714 | ugeth_vdbg("%s, %d: ERROR!!! skb - 0x%08x", |
| 3715 | __FUNCTION__, __LINE__, (u32) skb); |
| 3716 | if (skb) |
| 3717 | dev_kfree_skb_any(skb); |
| 3718 | |
| 3719 | ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL; |
| 3720 | ugeth->stats.rx_dropped++; |
| 3721 | } else { |
| 3722 | ugeth->stats.rx_packets++; |
| 3723 | howmany++; |
| 3724 | |
| 3725 | /* Prep the skb for the packet */ |
| 3726 | skb_put(skb, length); |
| 3727 | |
| 3728 | /* Tell the skb what kind of packet this is */ |
| 3729 | skb->protocol = eth_type_trans(skb, ugeth->dev); |
| 3730 | |
| 3731 | ugeth->stats.rx_bytes += length; |
| 3732 | /* Send the packet up the stack */ |
| 3733 | #ifdef CONFIG_UGETH_NAPI |
| 3734 | netif_receive_skb(skb); |
| 3735 | #else |
| 3736 | netif_rx(skb); |
| 3737 | #endif /* CONFIG_UGETH_NAPI */ |
| 3738 | } |
| 3739 | |
| 3740 | ugeth->dev->last_rx = jiffies; |
| 3741 | |
| 3742 | skb = get_new_skb(ugeth, bd); |
| 3743 | if (!skb) { |
| 3744 | ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__); |
| 3745 | spin_unlock(&ugeth->lock); |
| 3746 | ugeth->stats.rx_dropped++; |
| 3747 | break; |
| 3748 | } |
| 3749 | |
| 3750 | ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb; |
| 3751 | |
| 3752 | /* update to point at the next skb */ |
| 3753 | ugeth->skb_currx[rxQ] = |
| 3754 | (ugeth->skb_currx[rxQ] + |
| 3755 | 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]); |
| 3756 | |
| 3757 | if (bd_status & R_W) |
| 3758 | bd = ugeth->p_rx_bd_ring[rxQ]; |
| 3759 | else |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3760 | bd += sizeof(struct qe_bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3761 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3762 | bd_status = in_be32((u32 *)bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3763 | } |
| 3764 | |
| 3765 | ugeth->rxBd[rxQ] = bd; |
| 3766 | spin_unlock(&ugeth->lock); |
| 3767 | return howmany; |
| 3768 | } |
| 3769 | |
| 3770 | static int ucc_geth_tx(struct net_device *dev, u8 txQ) |
| 3771 | { |
| 3772 | /* Start from the next BD that should be filled */ |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3773 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3774 | u8 *bd; /* BD pointer */ |
| 3775 | u32 bd_status; |
| 3776 | |
| 3777 | bd = ugeth->confBd[txQ]; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3778 | bd_status = in_be32((u32 *)bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3779 | |
| 3780 | /* Normal processing. */ |
| 3781 | while ((bd_status & T_R) == 0) { |
| 3782 | /* BD contains already transmitted buffer. */ |
| 3783 | /* Handle the transmitted buffer and release */ |
| 3784 | /* the BD to be used with the current frame */ |
| 3785 | |
| 3786 | if ((bd = ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0)) |
| 3787 | break; |
| 3788 | |
| 3789 | ugeth->stats.tx_packets++; |
| 3790 | |
| 3791 | /* Free the sk buffer associated with this TxBD */ |
| 3792 | dev_kfree_skb_irq(ugeth-> |
| 3793 | tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]); |
| 3794 | ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL; |
| 3795 | ugeth->skb_dirtytx[txQ] = |
| 3796 | (ugeth->skb_dirtytx[txQ] + |
| 3797 | 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); |
| 3798 | |
| 3799 | /* We freed a buffer, so now we can restart transmission */ |
| 3800 | if (netif_queue_stopped(dev)) |
| 3801 | netif_wake_queue(dev); |
| 3802 | |
| 3803 | /* Advance the confirmation BD pointer */ |
| 3804 | if (!(bd_status & T_W)) |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3805 | ugeth->confBd[txQ] += sizeof(struct qe_bd); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3806 | else |
| 3807 | ugeth->confBd[txQ] = ugeth->p_tx_bd_ring[txQ]; |
| 3808 | } |
| 3809 | return 0; |
| 3810 | } |
| 3811 | |
| 3812 | #ifdef CONFIG_UGETH_NAPI |
| 3813 | static int ucc_geth_poll(struct net_device *dev, int *budget) |
| 3814 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3815 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3816 | int howmany; |
| 3817 | int rx_work_limit = *budget; |
| 3818 | u8 rxQ = 0; |
| 3819 | |
| 3820 | if (rx_work_limit > dev->quota) |
| 3821 | rx_work_limit = dev->quota; |
| 3822 | |
| 3823 | howmany = ucc_geth_rx(ugeth, rxQ, rx_work_limit); |
| 3824 | |
| 3825 | dev->quota -= howmany; |
| 3826 | rx_work_limit -= howmany; |
| 3827 | *budget -= howmany; |
| 3828 | |
| 3829 | if (rx_work_limit >= 0) |
| 3830 | netif_rx_complete(dev); |
| 3831 | |
| 3832 | return (rx_work_limit < 0) ? 1 : 0; |
| 3833 | } |
| 3834 | #endif /* CONFIG_UGETH_NAPI */ |
| 3835 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 3836 | static irqreturn_t ucc_geth_irq_handler(int irq, void *info) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3837 | { |
| 3838 | struct net_device *dev = (struct net_device *)info; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3839 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
| 3840 | struct ucc_fast_private *uccf; |
| 3841 | struct ucc_geth_info *ug_info; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3842 | register u32 ucce = 0; |
| 3843 | register u32 bit_mask = UCCE_RXBF_SINGLE_MASK; |
| 3844 | register u32 tx_mask = UCCE_TXBF_SINGLE_MASK; |
| 3845 | register u8 i; |
| 3846 | |
| 3847 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 3848 | |
| 3849 | if (!ugeth) |
| 3850 | return IRQ_NONE; |
| 3851 | |
| 3852 | uccf = ugeth->uccf; |
| 3853 | ug_info = ugeth->ug_info; |
| 3854 | |
| 3855 | do { |
| 3856 | ucce |= (u32) (in_be32(uccf->p_ucce) & in_be32(uccf->p_uccm)); |
| 3857 | |
| 3858 | /* clear event bits for next time */ |
| 3859 | /* Side effect here is to mask ucce variable |
| 3860 | for future processing below. */ |
| 3861 | out_be32(uccf->p_ucce, ucce); /* Clear with ones, |
| 3862 | but only bits in UCCM */ |
| 3863 | |
| 3864 | /* We ignore Tx interrupts because Tx confirmation is |
| 3865 | done inside Tx routine */ |
| 3866 | |
| 3867 | for (i = 0; i < ug_info->numQueuesRx; i++) { |
| 3868 | if (ucce & bit_mask) |
| 3869 | ucc_geth_rx(ugeth, i, |
| 3870 | (int)ugeth->ug_info-> |
| 3871 | bdRingLenRx[i]); |
| 3872 | ucce &= ~bit_mask; |
| 3873 | bit_mask <<= 1; |
| 3874 | } |
| 3875 | |
| 3876 | for (i = 0; i < ug_info->numQueuesTx; i++) { |
| 3877 | if (ucce & tx_mask) |
| 3878 | ucc_geth_tx(dev, i); |
| 3879 | ucce &= ~tx_mask; |
| 3880 | tx_mask <<= 1; |
| 3881 | } |
| 3882 | |
| 3883 | /* Exceptions */ |
| 3884 | if (ucce & UCCE_BSY) { |
| 3885 | ugeth_vdbg("Got BUSY irq!!!!"); |
| 3886 | ugeth->stats.rx_errors++; |
| 3887 | ucce &= ~UCCE_BSY; |
| 3888 | } |
| 3889 | if (ucce & UCCE_OTHER) { |
| 3890 | ugeth_vdbg("Got frame with error (ucce - 0x%08x)!!!!", |
| 3891 | ucce); |
| 3892 | ugeth->stats.rx_errors++; |
| 3893 | ucce &= ~ucce; |
| 3894 | } |
| 3895 | } |
| 3896 | while (ucce); |
| 3897 | |
| 3898 | return IRQ_HANDLED; |
| 3899 | } |
| 3900 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 3901 | static irqreturn_t phy_interrupt(int irq, void *dev_id) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3902 | { |
| 3903 | struct net_device *dev = (struct net_device *)dev_id; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3904 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3905 | |
| 3906 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 3907 | |
| 3908 | /* Clear the interrupt */ |
| 3909 | mii_clear_phy_interrupt(ugeth->mii_info); |
| 3910 | |
| 3911 | /* Disable PHY interrupts */ |
| 3912 | mii_configure_phy_interrupt(ugeth->mii_info, MII_INTERRUPT_DISABLED); |
| 3913 | |
| 3914 | /* Schedule the phy change */ |
| 3915 | schedule_work(&ugeth->tq); |
| 3916 | |
| 3917 | return IRQ_HANDLED; |
| 3918 | } |
| 3919 | |
| 3920 | /* Scheduled by the phy_interrupt/timer to handle PHY changes */ |
| 3921 | static void ugeth_phy_change(void *data) |
| 3922 | { |
| 3923 | struct net_device *dev = (struct net_device *)data; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3924 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
| 3925 | struct ucc_geth *ug_regs; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3926 | int result = 0; |
| 3927 | |
| 3928 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 3929 | |
| 3930 | ug_regs = ugeth->ug_regs; |
| 3931 | |
| 3932 | /* Delay to give the PHY a chance to change the |
| 3933 | * register state */ |
| 3934 | msleep(1); |
| 3935 | |
| 3936 | /* Update the link, speed, duplex */ |
| 3937 | result = ugeth->mii_info->phyinfo->read_status(ugeth->mii_info); |
| 3938 | |
| 3939 | /* Adjust the known status as long as the link |
| 3940 | * isn't still coming up */ |
| 3941 | if ((0 == result) || (ugeth->mii_info->link == 0)) |
| 3942 | adjust_link(dev); |
| 3943 | |
| 3944 | /* Reenable interrupts, if needed */ |
| 3945 | if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) |
| 3946 | mii_configure_phy_interrupt(ugeth->mii_info, |
| 3947 | MII_INTERRUPT_ENABLED); |
| 3948 | } |
| 3949 | |
| 3950 | /* Called every so often on systems that don't interrupt |
| 3951 | * the core for PHY changes */ |
| 3952 | static void ugeth_phy_timer(unsigned long data) |
| 3953 | { |
| 3954 | struct net_device *dev = (struct net_device *)data; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3955 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3956 | |
| 3957 | schedule_work(&ugeth->tq); |
| 3958 | |
| 3959 | mod_timer(&ugeth->phy_info_timer, jiffies + PHY_CHANGE_TIME * HZ); |
| 3960 | } |
| 3961 | |
| 3962 | /* Keep trying aneg for some time |
| 3963 | * If, after GFAR_AN_TIMEOUT seconds, it has not |
| 3964 | * finished, we switch to forced. |
| 3965 | * Either way, once the process has completed, we either |
| 3966 | * request the interrupt, or switch the timer over to |
| 3967 | * using ugeth_phy_timer to check status */ |
| 3968 | static void ugeth_phy_startup_timer(unsigned long data) |
| 3969 | { |
| 3970 | struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 3971 | struct ucc_geth_private *ugeth = netdev_priv(mii_info->dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 3972 | static int secondary = UGETH_AN_TIMEOUT; |
| 3973 | int result; |
| 3974 | |
| 3975 | /* Configure the Auto-negotiation */ |
| 3976 | result = mii_info->phyinfo->config_aneg(mii_info); |
| 3977 | |
| 3978 | /* If autonegotiation failed to start, and |
| 3979 | * we haven't timed out, reset the timer, and return */ |
| 3980 | if (result && secondary--) { |
| 3981 | mod_timer(&ugeth->phy_info_timer, jiffies + HZ); |
| 3982 | return; |
| 3983 | } else if (result) { |
| 3984 | /* Couldn't start autonegotiation. |
| 3985 | * Try switching to forced */ |
| 3986 | mii_info->autoneg = 0; |
| 3987 | result = mii_info->phyinfo->config_aneg(mii_info); |
| 3988 | |
| 3989 | /* Forcing failed! Give up */ |
| 3990 | if (result) { |
| 3991 | ugeth_err("%s: Forcing failed!", mii_info->dev->name); |
| 3992 | return; |
| 3993 | } |
| 3994 | } |
| 3995 | |
| 3996 | /* Kill the timer so it can be restarted */ |
| 3997 | del_timer_sync(&ugeth->phy_info_timer); |
| 3998 | |
| 3999 | /* Grab the PHY interrupt, if necessary/possible */ |
| 4000 | if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) { |
| 4001 | if (request_irq(ugeth->ug_info->phy_interrupt, |
| 4002 | phy_interrupt, |
| 4003 | SA_SHIRQ, "phy_interrupt", mii_info->dev) < 0) { |
| 4004 | ugeth_err("%s: Can't get IRQ %d (PHY)", |
| 4005 | mii_info->dev->name, |
| 4006 | ugeth->ug_info->phy_interrupt); |
| 4007 | } else { |
| 4008 | mii_configure_phy_interrupt(ugeth->mii_info, |
| 4009 | MII_INTERRUPT_ENABLED); |
| 4010 | return; |
| 4011 | } |
| 4012 | } |
| 4013 | |
| 4014 | /* Start the timer again, this time in order to |
| 4015 | * handle a change in status */ |
| 4016 | init_timer(&ugeth->phy_info_timer); |
| 4017 | ugeth->phy_info_timer.function = &ugeth_phy_timer; |
| 4018 | ugeth->phy_info_timer.data = (unsigned long)mii_info->dev; |
| 4019 | mod_timer(&ugeth->phy_info_timer, jiffies + PHY_CHANGE_TIME * HZ); |
| 4020 | } |
| 4021 | |
| 4022 | /* Called when something needs to use the ethernet device */ |
| 4023 | /* Returns 0 for success. */ |
| 4024 | static int ucc_geth_open(struct net_device *dev) |
| 4025 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4026 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4027 | int err; |
| 4028 | |
| 4029 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 4030 | |
| 4031 | /* Test station address */ |
| 4032 | if (dev->dev_addr[0] & ENET_GROUP_ADDR) { |
| 4033 | ugeth_err("%s: Multicast address used for station address" |
| 4034 | " - is this what you wanted?", __FUNCTION__); |
| 4035 | return -EINVAL; |
| 4036 | } |
| 4037 | |
| 4038 | err = ucc_geth_startup(ugeth); |
| 4039 | if (err) { |
| 4040 | ugeth_err("%s: Cannot configure net device, aborting.", |
| 4041 | dev->name); |
| 4042 | return err; |
| 4043 | } |
| 4044 | |
| 4045 | err = adjust_enet_interface(ugeth); |
| 4046 | if (err) { |
| 4047 | ugeth_err("%s: Cannot configure net device, aborting.", |
| 4048 | dev->name); |
| 4049 | return err; |
| 4050 | } |
| 4051 | |
| 4052 | /* Set MACSTNADDR1, MACSTNADDR2 */ |
| 4053 | /* For more details see the hardware spec. */ |
| 4054 | init_mac_station_addr_regs(dev->dev_addr[0], |
| 4055 | dev->dev_addr[1], |
| 4056 | dev->dev_addr[2], |
| 4057 | dev->dev_addr[3], |
| 4058 | dev->dev_addr[4], |
| 4059 | dev->dev_addr[5], |
| 4060 | &ugeth->ug_regs->macstnaddr1, |
| 4061 | &ugeth->ug_regs->macstnaddr2); |
| 4062 | |
| 4063 | err = init_phy(dev); |
| 4064 | if (err) { |
| 4065 | ugeth_err("%s: Cannot initialzie PHY, aborting.", dev->name); |
| 4066 | return err; |
| 4067 | } |
| 4068 | #ifndef CONFIG_UGETH_NAPI |
| 4069 | err = |
| 4070 | request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0, |
| 4071 | "UCC Geth", dev); |
| 4072 | if (err) { |
| 4073 | ugeth_err("%s: Cannot get IRQ for net device, aborting.", |
| 4074 | dev->name); |
| 4075 | ucc_geth_stop(ugeth); |
| 4076 | return err; |
| 4077 | } |
| 4078 | #endif /* CONFIG_UGETH_NAPI */ |
| 4079 | |
| 4080 | /* Set up the PHY change work queue */ |
| 4081 | INIT_WORK(&ugeth->tq, ugeth_phy_change, dev); |
| 4082 | |
| 4083 | init_timer(&ugeth->phy_info_timer); |
| 4084 | ugeth->phy_info_timer.function = &ugeth_phy_startup_timer; |
| 4085 | ugeth->phy_info_timer.data = (unsigned long)ugeth->mii_info; |
| 4086 | mod_timer(&ugeth->phy_info_timer, jiffies + HZ); |
| 4087 | |
| 4088 | err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); |
| 4089 | if (err) { |
| 4090 | ugeth_err("%s: Cannot enable net device, aborting.", dev->name); |
| 4091 | ucc_geth_stop(ugeth); |
| 4092 | return err; |
| 4093 | } |
| 4094 | |
| 4095 | netif_start_queue(dev); |
| 4096 | |
| 4097 | return err; |
| 4098 | } |
| 4099 | |
| 4100 | /* Stops the kernel queue, and halts the controller */ |
| 4101 | static int ucc_geth_close(struct net_device *dev) |
| 4102 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4103 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4104 | |
| 4105 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 4106 | |
| 4107 | ucc_geth_stop(ugeth); |
| 4108 | |
| 4109 | /* Shutdown the PHY */ |
| 4110 | if (ugeth->mii_info->phyinfo->close) |
| 4111 | ugeth->mii_info->phyinfo->close(ugeth->mii_info); |
| 4112 | |
| 4113 | kfree(ugeth->mii_info); |
| 4114 | |
| 4115 | netif_stop_queue(dev); |
| 4116 | |
| 4117 | return 0; |
| 4118 | } |
| 4119 | |
Jeff Garzik | 7282d49 | 2006-09-13 14:30:00 -0400 | [diff] [blame] | 4120 | const struct ethtool_ops ucc_geth_ethtool_ops = { }; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4121 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4122 | static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4123 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4124 | struct device *device = &ofdev->dev; |
| 4125 | struct device_node *np = ofdev->node; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4126 | struct net_device *dev = NULL; |
| 4127 | struct ucc_geth_private *ugeth = NULL; |
| 4128 | struct ucc_geth_info *ug_info; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4129 | struct resource res; |
| 4130 | struct device_node *phy; |
| 4131 | int err, ucc_num, phy_interface; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4132 | static int mii_mng_configured = 0; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4133 | const phandle *ph; |
| 4134 | const unsigned int *prop; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4135 | |
| 4136 | ugeth_vdbg("%s: IN", __FUNCTION__); |
| 4137 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4138 | prop = get_property(np, "device-id", NULL); |
| 4139 | ucc_num = *prop - 1; |
| 4140 | if ((ucc_num < 0) || (ucc_num > 7)) |
| 4141 | return -ENODEV; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4142 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4143 | ug_info = &ugeth_info[ucc_num]; |
| 4144 | ug_info->uf_info.ucc_num = ucc_num; |
| 4145 | prop = get_property(np, "rx-clock", NULL); |
| 4146 | ug_info->uf_info.rx_clock = *prop; |
| 4147 | prop = get_property(np, "tx-clock", NULL); |
| 4148 | ug_info->uf_info.tx_clock = *prop; |
| 4149 | err = of_address_to_resource(np, 0, &res); |
| 4150 | if (err) |
| 4151 | return -EINVAL; |
| 4152 | |
| 4153 | ug_info->uf_info.regs = res.start; |
| 4154 | ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); |
| 4155 | |
| 4156 | ph = get_property(np, "phy-handle", NULL); |
| 4157 | phy = of_find_node_by_phandle(*ph); |
| 4158 | |
| 4159 | if (phy == NULL) |
| 4160 | return -ENODEV; |
| 4161 | |
| 4162 | prop = get_property(phy, "reg", NULL); |
| 4163 | ug_info->phy_address = *prop; |
| 4164 | prop = get_property(phy, "interface", NULL); |
| 4165 | ug_info->enet_interface = *prop; |
| 4166 | ug_info->phy_interrupt = irq_of_parse_and_map(phy, 0); |
| 4167 | ug_info->board_flags = (ug_info->phy_interrupt == NO_IRQ)? |
| 4168 | 0:FSL_UGETH_BRD_HAS_PHY_INTR; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4169 | |
| 4170 | printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n", |
| 4171 | ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs, |
| 4172 | ug_info->uf_info.irq); |
| 4173 | |
| 4174 | if (ug_info == NULL) { |
| 4175 | ugeth_err("%s: [%d] Missing additional data!", __FUNCTION__, |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4176 | ucc_num); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4177 | return -ENODEV; |
| 4178 | } |
| 4179 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4180 | /* FIXME: Work around for early chip rev. */ |
| 4181 | /* There's a bug in initial chip rev(s) in the RGMII ac */ |
| 4182 | /* timing. */ |
| 4183 | /* The following compensates by writing to the reserved */ |
| 4184 | /* QE Port Output Hold Registers (CPOH1?). */ |
| 4185 | prop = get_property(phy, "interface", NULL); |
| 4186 | phy_interface = *prop; |
| 4187 | if ((phy_interface == ENET_1000_RGMII) || |
| 4188 | (phy_interface == ENET_100_RGMII) || |
| 4189 | (phy_interface == ENET_10_RGMII)) { |
| 4190 | struct device_node *soc; |
| 4191 | phys_addr_t immrbase = -1; |
| 4192 | u32 *tmp_reg; |
| 4193 | u32 tmp_val; |
| 4194 | |
| 4195 | soc = of_find_node_by_type(NULL, "soc"); |
| 4196 | if (soc) { |
| 4197 | unsigned int size; |
| 4198 | const void *prop = get_property(soc, "reg", &size); |
| 4199 | immrbase = of_translate_address(soc, prop); |
| 4200 | of_node_put(soc); |
| 4201 | }; |
| 4202 | |
| 4203 | tmp_reg = (u32 *) ioremap(immrbase + 0x14A8, 0x4); |
| 4204 | tmp_val = in_be32(tmp_reg); |
| 4205 | if (ucc_num == 1) |
| 4206 | out_be32(tmp_reg, tmp_val | 0x00003000); |
| 4207 | else if (ucc_num == 2) |
| 4208 | out_be32(tmp_reg, tmp_val | 0x0c000000); |
| 4209 | iounmap(tmp_reg); |
| 4210 | } |
| 4211 | |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4212 | if (!mii_mng_configured) { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4213 | ucc_set_qe_mux_mii_mng(ucc_num); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4214 | mii_mng_configured = 1; |
| 4215 | } |
| 4216 | |
| 4217 | /* Create an ethernet device instance */ |
| 4218 | dev = alloc_etherdev(sizeof(*ugeth)); |
| 4219 | |
| 4220 | if (dev == NULL) |
| 4221 | return -ENOMEM; |
| 4222 | |
| 4223 | ugeth = netdev_priv(dev); |
| 4224 | spin_lock_init(&ugeth->lock); |
| 4225 | |
| 4226 | dev_set_drvdata(device, dev); |
| 4227 | |
| 4228 | /* Set the dev->base_addr to the gfar reg region */ |
| 4229 | dev->base_addr = (unsigned long)(ug_info->uf_info.regs); |
| 4230 | |
| 4231 | SET_MODULE_OWNER(dev); |
| 4232 | SET_NETDEV_DEV(dev, device); |
| 4233 | |
| 4234 | /* Fill in the dev structure */ |
| 4235 | dev->open = ucc_geth_open; |
| 4236 | dev->hard_start_xmit = ucc_geth_start_xmit; |
| 4237 | dev->tx_timeout = ucc_geth_timeout; |
| 4238 | dev->watchdog_timeo = TX_TIMEOUT; |
| 4239 | #ifdef CONFIG_UGETH_NAPI |
| 4240 | dev->poll = ucc_geth_poll; |
| 4241 | dev->weight = UCC_GETH_DEV_WEIGHT; |
| 4242 | #endif /* CONFIG_UGETH_NAPI */ |
| 4243 | dev->stop = ucc_geth_close; |
| 4244 | dev->get_stats = ucc_geth_get_stats; |
| 4245 | // dev->change_mtu = ucc_geth_change_mtu; |
| 4246 | dev->mtu = 1500; |
| 4247 | dev->set_multicast_list = ucc_geth_set_multi; |
| 4248 | dev->ethtool_ops = &ucc_geth_ethtool_ops; |
| 4249 | |
| 4250 | err = register_netdev(dev); |
| 4251 | if (err) { |
| 4252 | ugeth_err("%s: Cannot register net device, aborting.", |
| 4253 | dev->name); |
| 4254 | free_netdev(dev); |
| 4255 | return err; |
| 4256 | } |
| 4257 | |
| 4258 | ugeth->ug_info = ug_info; |
| 4259 | ugeth->dev = dev; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4260 | memcpy(dev->dev_addr, get_property(np, "mac-address", NULL), 6); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4261 | |
| 4262 | return 0; |
| 4263 | } |
| 4264 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4265 | static int ucc_geth_remove(struct of_device* ofdev) |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4266 | { |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4267 | struct device *device = &ofdev->dev; |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4268 | struct net_device *dev = dev_get_drvdata(device); |
| 4269 | struct ucc_geth_private *ugeth = netdev_priv(dev); |
| 4270 | |
| 4271 | dev_set_drvdata(device, NULL); |
| 4272 | ucc_geth_memclean(ugeth); |
| 4273 | free_netdev(dev); |
| 4274 | |
| 4275 | return 0; |
| 4276 | } |
| 4277 | |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4278 | static struct of_device_id ucc_geth_match[] = { |
| 4279 | { |
| 4280 | .type = "network", |
| 4281 | .compatible = "ucc_geth", |
| 4282 | }, |
| 4283 | {}, |
| 4284 | }; |
| 4285 | |
| 4286 | MODULE_DEVICE_TABLE(of, ucc_geth_match); |
| 4287 | |
| 4288 | static struct of_platform_driver ucc_geth_driver = { |
| 4289 | .name = DRV_NAME, |
| 4290 | .match_table = ucc_geth_match, |
| 4291 | .probe = ucc_geth_probe, |
| 4292 | .remove = ucc_geth_remove, |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4293 | }; |
| 4294 | |
| 4295 | static int __init ucc_geth_init(void) |
| 4296 | { |
| 4297 | int i; |
Li Yang | 18a8e86 | 2006-10-19 21:07:34 -0500 | [diff] [blame] | 4298 | |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4299 | printk(KERN_INFO "ucc_geth: " DRV_DESC "\n"); |
| 4300 | for (i = 0; i < 8; i++) |
| 4301 | memcpy(&(ugeth_info[i]), &ugeth_primary_info, |
| 4302 | sizeof(ugeth_primary_info)); |
| 4303 | |
Kim Phillips | a4f0c2c | 2006-11-15 12:29:35 -0600 | [diff] [blame] | 4304 | return of_register_platform_driver(&ucc_geth_driver); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4305 | } |
| 4306 | |
| 4307 | static void __exit ucc_geth_exit(void) |
| 4308 | { |
Kim Phillips | a4f0c2c | 2006-11-15 12:29:35 -0600 | [diff] [blame] | 4309 | of_unregister_platform_driver(&ucc_geth_driver); |
Li Yang | ce973b1 | 2006-08-14 23:00:11 -0700 | [diff] [blame] | 4310 | } |
| 4311 | |
| 4312 | module_init(ucc_geth_init); |
| 4313 | module_exit(ucc_geth_exit); |
| 4314 | |
| 4315 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
| 4316 | MODULE_DESCRIPTION(DRV_DESC); |
| 4317 | MODULE_LICENSE("GPL"); |