Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | This is the driver for the MAC 10/100 on-chip Ethernet controller |
| 3 | currently tested on all the ST boards based on STb7109 and stx7200 SoCs. |
| 4 | |
| 5 | DWC Ether MAC 10/100 Universal version 4.0 has been used for developing |
| 6 | this code. |
| 7 | |
Giuseppe CAVALLARO | 56b106a | 2010-04-13 20:21:12 +0000 | [diff] [blame] | 8 | This contains the functions to handle the dma. |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 9 | |
| 10 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
| 11 | |
| 12 | This program is free software; you can redistribute it and/or modify it |
| 13 | under the terms and conditions of the GNU General Public License, |
| 14 | version 2, as published by the Free Software Foundation. |
| 15 | |
| 16 | This program is distributed in the hope it will be useful, but WITHOUT |
| 17 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 18 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 19 | more details. |
| 20 | |
| 21 | You should have received a copy of the GNU General Public License along with |
| 22 | this program; if not, write to the Free Software Foundation, Inc., |
| 23 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 24 | |
| 25 | The full GNU General Public License is included in this distribution in |
| 26 | the file called "COPYING". |
| 27 | |
| 28 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
| 29 | *******************************************************************************/ |
| 30 | |
| 31 | #include "dwmac100.h" |
| 32 | #include "dwmac_dma.h" |
| 33 | |
Giuseppe CAVALLARO | ad01b7d | 2010-08-23 20:40:42 +0000 | [diff] [blame] | 34 | static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 35 | u32 dma_rx) |
| 36 | { |
| 37 | u32 value = readl(ioaddr + DMA_BUS_MODE); |
Giuseppe CAVALLARO | c629882 | 2010-09-17 03:23:41 +0000 | [diff] [blame] | 38 | int limit; |
| 39 | |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 40 | /* DMA SW reset */ |
| 41 | value |= DMA_BUS_MODE_SFT_RESET; |
| 42 | writel(value, ioaddr + DMA_BUS_MODE); |
Giuseppe CAVALLARO | c629882 | 2010-09-17 03:23:41 +0000 | [diff] [blame] | 43 | limit = 15000; |
| 44 | while (limit--) { |
| 45 | if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) |
| 46 | break; |
| 47 | } |
| 48 | if (limit < 0) |
| 49 | return -EBUSY; |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 50 | |
| 51 | /* Enable Application Access by writing to DMA CSR0 */ |
| 52 | writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), |
| 53 | ioaddr + DMA_BUS_MODE); |
| 54 | |
| 55 | /* Mask interrupts by writing to CSR7 */ |
| 56 | writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); |
| 57 | |
| 58 | /* The base address of the RX/TX descriptor lists must be written into |
| 59 | * DMA CSR3 and CSR4, respectively. */ |
| 60 | writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); |
| 61 | writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | /* Store and Forward capability is not used at all.. |
| 67 | * The transmit threshold can be programmed by |
| 68 | * setting the TTC bits in the DMA control register.*/ |
Giuseppe CAVALLARO | ad01b7d | 2010-08-23 20:40:42 +0000 | [diff] [blame] | 69 | static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode, |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 70 | int rxmode) |
| 71 | { |
| 72 | u32 csr6 = readl(ioaddr + DMA_CONTROL); |
| 73 | |
| 74 | if (txmode <= 32) |
| 75 | csr6 |= DMA_CONTROL_TTC_32; |
| 76 | else if (txmode <= 64) |
| 77 | csr6 |= DMA_CONTROL_TTC_64; |
| 78 | else |
| 79 | csr6 |= DMA_CONTROL_TTC_128; |
| 80 | |
| 81 | writel(csr6, ioaddr + DMA_CONTROL); |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 82 | } |
| 83 | |
Giuseppe CAVALLARO | ad01b7d | 2010-08-23 20:40:42 +0000 | [diff] [blame] | 84 | static void dwmac100_dump_dma_regs(void __iomem *ioaddr) |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 85 | { |
| 86 | int i; |
| 87 | |
Giuseppe CAVALLARO | 56b106a | 2010-04-13 20:21:12 +0000 | [diff] [blame] | 88 | CHIP_DBG(KERN_DEBUG "DWMAC 100 DMA CSR\n"); |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 89 | for (i = 0; i < 9; i++) |
| 90 | pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i, |
| 91 | (DMA_BUS_MODE + i * 4), |
| 92 | readl(ioaddr + DMA_BUS_MODE + i * 4)); |
Giuseppe CAVALLARO | 56b106a | 2010-04-13 20:21:12 +0000 | [diff] [blame] | 93 | CHIP_DBG(KERN_DEBUG "\t CSR20 (offset 0x%x): 0x%08x\n", |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 94 | DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR)); |
Giuseppe CAVALLARO | 56b106a | 2010-04-13 20:21:12 +0000 | [diff] [blame] | 95 | CHIP_DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n", |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 96 | DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR)); |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | /* DMA controller has two counters to track the number of |
| 100 | * the receive missed frames. */ |
| 101 | static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, |
Giuseppe CAVALLARO | ad01b7d | 2010-08-23 20:40:42 +0000 | [diff] [blame] | 102 | void __iomem *ioaddr) |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 103 | { |
| 104 | struct net_device_stats *stats = (struct net_device_stats *)data; |
| 105 | u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR); |
| 106 | |
| 107 | if (unlikely(csr8)) { |
| 108 | if (csr8 & DMA_MISSED_FRAME_OVE) { |
| 109 | stats->rx_over_errors += 0x800; |
| 110 | x->rx_overflow_cntr += 0x800; |
| 111 | } else { |
| 112 | unsigned int ove_cntr; |
| 113 | ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17); |
| 114 | stats->rx_over_errors += ove_cntr; |
| 115 | x->rx_overflow_cntr += ove_cntr; |
| 116 | } |
| 117 | |
| 118 | if (csr8 & DMA_MISSED_FRAME_OVE_M) { |
| 119 | stats->rx_missed_errors += 0xffff; |
| 120 | x->rx_missed_cntr += 0xffff; |
| 121 | } else { |
| 122 | unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR); |
| 123 | stats->rx_missed_errors += miss_f; |
| 124 | x->rx_missed_cntr += miss_f; |
| 125 | } |
| 126 | } |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 127 | } |
| 128 | |
stephen hemminger | cadb792 | 2010-10-13 14:51:25 +0000 | [diff] [blame] | 129 | const struct stmmac_dma_ops dwmac100_dma_ops = { |
Giuseppe CAVALLARO | 3c32be6 | 2010-04-13 20:21:11 +0000 | [diff] [blame] | 130 | .init = dwmac100_dma_init, |
| 131 | .dump_regs = dwmac100_dump_dma_regs, |
| 132 | .dma_mode = dwmac100_dma_operation_mode, |
| 133 | .dma_diagnostic_fr = dwmac100_dma_diagnostic_fr, |
| 134 | .enable_dma_transmission = dwmac_enable_dma_transmission, |
| 135 | .enable_dma_irq = dwmac_enable_dma_irq, |
| 136 | .disable_dma_irq = dwmac_disable_dma_irq, |
| 137 | .start_tx = dwmac_dma_start_tx, |
| 138 | .stop_tx = dwmac_dma_stop_tx, |
| 139 | .start_rx = dwmac_dma_start_rx, |
| 140 | .stop_rx = dwmac_dma_stop_rx, |
| 141 | .dma_interrupt = dwmac_dma_interrupt, |
| 142 | }; |