Patrick Glass | 9fa32c6 | 2008-08-18 14:41:30 -0700 | [diff] [blame] | 1 | /* |
| 2 | * @file /arch/mips/pmc-sierra/msp71xx/gpio.c |
| 3 | * |
| 4 | * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two |
| 5 | * types of registers. The data register sets the output level when in output |
| 6 | * mode and when in input mode will contain the value at the input. The config |
| 7 | * register sets the various modes for each gpio. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * @author Patrick Glass <patrickglass@gmail.com> |
| 14 | */ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/gpio.h> |
| 20 | #include <linux/spinlock.h> |
| 21 | #include <linux/io.h> |
| 22 | |
| 23 | #define MSP71XX_CFG_OFFSET(gpio) (4 * (gpio)) |
| 24 | #define CONF_MASK 0x0F |
| 25 | #define MSP71XX_GPIO_INPUT 0x01 |
| 26 | #define MSP71XX_GPIO_OUTPUT 0x08 |
| 27 | |
| 28 | #define MSP71XX_GPIO_BASE 0x0B8400000L |
| 29 | |
| 30 | #define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip) |
| 31 | |
| 32 | static spinlock_t gpio_lock; |
| 33 | |
| 34 | /* |
| 35 | * struct msp71xx_gpio_chip - container for gpio chip and registers |
| 36 | * @chip: chip structure for the specified gpio bank |
| 37 | * @data_reg: register for reading and writing the gpio pin value |
| 38 | * @config_reg: register to set the mode for the gpio pin bank |
| 39 | * @out_drive_reg: register to set the output drive mode for the gpio pin bank |
| 40 | */ |
| 41 | struct msp71xx_gpio_chip { |
| 42 | struct gpio_chip chip; |
| 43 | void __iomem *data_reg; |
| 44 | void __iomem *config_reg; |
| 45 | void __iomem *out_drive_reg; |
| 46 | }; |
| 47 | |
| 48 | /* |
| 49 | * msp71xx_gpio_get() - return the chip's gpio value |
| 50 | * @chip: chip structure which controls the specified gpio |
| 51 | * @offset: gpio whose value will be returned |
| 52 | * |
| 53 | * It will return 0 if gpio value is low and other if high. |
| 54 | */ |
| 55 | static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 56 | { |
| 57 | struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip); |
| 58 | |
| 59 | return __raw_readl(msp_chip->data_reg) & (1 << offset); |
| 60 | } |
| 61 | |
| 62 | /* |
| 63 | * msp71xx_gpio_set() - set the output value for the gpio |
| 64 | * @chip: chip structure who controls the specified gpio |
| 65 | * @offset: gpio whose value will be assigned |
| 66 | * @value: logic level to assign to the gpio initially |
| 67 | * |
| 68 | * This will set the gpio bit specified to the desired value. It will set the |
| 69 | * gpio pin low if value is 0 otherwise it will be high. |
| 70 | */ |
| 71 | static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 72 | { |
| 73 | struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip); |
| 74 | unsigned long flags; |
| 75 | u32 data; |
| 76 | |
| 77 | spin_lock_irqsave(&gpio_lock, flags); |
| 78 | |
| 79 | data = __raw_readl(msp_chip->data_reg); |
| 80 | if (value) |
| 81 | data |= (1 << offset); |
| 82 | else |
| 83 | data &= ~(1 << offset); |
| 84 | __raw_writel(data, msp_chip->data_reg); |
| 85 | |
| 86 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 87 | } |
| 88 | |
| 89 | /* |
| 90 | * msp71xx_set_gpio_mode() - declare the mode for a gpio |
| 91 | * @chip: chip structure which controls the specified gpio |
| 92 | * @offset: gpio whose value will be assigned |
| 93 | * @mode: desired configuration for the gpio (see datasheet) |
| 94 | * |
| 95 | * It will set the gpio pin config to the @mode value passed in. |
| 96 | */ |
| 97 | static int msp71xx_set_gpio_mode(struct gpio_chip *chip, |
| 98 | unsigned offset, int mode) |
| 99 | { |
| 100 | struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip); |
| 101 | const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset); |
| 102 | unsigned long flags; |
| 103 | u32 cfg; |
| 104 | |
| 105 | spin_lock_irqsave(&gpio_lock, flags); |
| 106 | |
| 107 | cfg = __raw_readl(msp_chip->config_reg); |
| 108 | cfg &= ~(CONF_MASK << bit_offset); |
| 109 | cfg |= (mode << bit_offset); |
| 110 | __raw_writel(cfg, msp_chip->config_reg); |
| 111 | |
| 112 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 113 | |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | /* |
| 118 | * msp71xx_direction_output() - declare the direction mode for a gpio |
| 119 | * @chip: chip structure which controls the specified gpio |
| 120 | * @offset: gpio whose value will be assigned |
| 121 | * @value: logic level to assign to the gpio initially |
| 122 | * |
| 123 | * This call will set the mode for the @gpio to output. It will set the |
| 124 | * gpio pin low if value is 0 otherwise it will be high. |
| 125 | */ |
| 126 | static int msp71xx_direction_output(struct gpio_chip *chip, |
| 127 | unsigned offset, int value) |
| 128 | { |
| 129 | msp71xx_gpio_set(chip, offset, value); |
| 130 | |
| 131 | return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT); |
| 132 | } |
| 133 | |
| 134 | /* |
| 135 | * msp71xx_direction_input() - declare the direction mode for a gpio |
| 136 | * @chip: chip structure which controls the specified gpio |
| 137 | * @offset: gpio whose to which the value will be assigned |
| 138 | * |
| 139 | * This call will set the mode for the @gpio to input. |
| 140 | */ |
| 141 | static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset) |
| 142 | { |
| 143 | return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT); |
| 144 | } |
| 145 | |
| 146 | /* |
| 147 | * msp71xx_set_output_drive() - declare the output drive for the gpio line |
| 148 | * @gpio: gpio pin whose output drive you wish to modify |
| 149 | * @value: zero for active drain 1 for open drain drive |
| 150 | * |
| 151 | * This call will set the output drive mode for the @gpio to output. |
| 152 | */ |
| 153 | int msp71xx_set_output_drive(unsigned gpio, int value) |
| 154 | { |
| 155 | unsigned long flags; |
| 156 | u32 data; |
| 157 | |
| 158 | if (gpio > 15 || gpio < 0) |
| 159 | return -EINVAL; |
| 160 | |
| 161 | spin_lock_irqsave(&gpio_lock, flags); |
| 162 | |
| 163 | data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190)); |
| 164 | if (value) |
| 165 | data |= (1 << gpio); |
| 166 | else |
| 167 | data &= ~(1 << gpio); |
| 168 | __raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190)); |
| 169 | |
| 170 | spin_unlock_irqrestore(&gpio_lock, flags); |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | EXPORT_SYMBOL(msp71xx_set_output_drive); |
| 175 | |
| 176 | #define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \ |
| 177 | { \ |
| 178 | .chip = { \ |
| 179 | .label = name, \ |
| 180 | .direction_input = msp71xx_direction_input, \ |
| 181 | .direction_output = msp71xx_direction_output, \ |
| 182 | .get = msp71xx_gpio_get, \ |
| 183 | .set = msp71xx_gpio_set, \ |
| 184 | .base = base_gpio, \ |
| 185 | .ngpio = num_gpio \ |
| 186 | }, \ |
| 187 | .data_reg = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \ |
| 188 | .config_reg = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \ |
| 189 | .out_drive_reg = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \ |
| 190 | } |
| 191 | |
| 192 | /* |
| 193 | * struct msp71xx_gpio_banks[] - container array of gpio banks |
| 194 | * @chip: chip structure for the specified gpio bank |
| 195 | * @data_reg: register for reading and writing the gpio pin value |
| 196 | * @config_reg: register to set the mode for the gpio pin bank |
| 197 | * |
| 198 | * This array structure defines the gpio banks for the PMC MIPS Processor. |
| 199 | * We specify the bank name, the data register, the config register, base |
| 200 | * starting gpio number, and the number of gpios exposed by the bank. |
| 201 | */ |
| 202 | static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = { |
| 203 | |
| 204 | MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2), |
| 205 | MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4), |
| 206 | MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4), |
| 207 | MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6), |
| 208 | }; |
| 209 | |
| 210 | void __init msp71xx_init_gpio(void) |
| 211 | { |
| 212 | int i; |
| 213 | |
| 214 | spin_lock_init(&gpio_lock); |
| 215 | |
| 216 | for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++) |
| 217 | gpiochip_add(&msp71xx_gpio_banks[i].chip); |
| 218 | } |