| /* |
| * P5040DS Device Tree Source |
| * |
| * Copyright 2012 - 2015 Freescale Semiconductor Inc. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * * Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * * Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * * Neither the name of Freescale Semiconductor nor the |
| * names of its contributors may be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * |
| * ALTERNATIVELY, this software may be distributed under the terms of the |
| * GNU General Public License ("GPL") as published by the Free Software |
| * Foundation, either version 2 of that License or (at your option) any |
| * later version. |
| * |
| * This software is provided by Freescale Semiconductor "as is" and any |
| * express or implied warranties, including, but not limited to, the implied |
| * warranties of merchantability and fitness for a particular purpose are |
| * disclaimed. In no event shall Freescale Semiconductor be liable for any |
| * direct, indirect, incidental, special, exemplary, or consequential damages |
| * (including, but not limited to, procurement of substitute goods or services; |
| * loss of use, data, or profits; or business interruption) however caused and |
| * on any theory of liability, whether in contract, strict liability, or tort |
| * (including negligence or otherwise) arising in any way out of the use of this |
| * software, even if advised of the possibility of such damage. |
| */ |
| |
| /include/ "p5040si-pre.dtsi" |
| |
| / { |
| model = "fsl,P5040DS"; |
| compatible = "fsl,P5040DS"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-parent = <&mpic>; |
| |
| aliases{ |
| phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c; |
| phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d; |
| phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e; |
| phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f; |
| phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c; |
| phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d; |
| phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e; |
| phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f; |
| phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c; |
| phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d; |
| phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e; |
| phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f; |
| phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c; |
| phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d; |
| phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e; |
| phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f; |
| hydra_rg = &hydra_rg; |
| hydra_sg_slot2 = &hydra_sg_slot2; |
| hydra_sg_slot3 = &hydra_sg_slot3; |
| hydra_sg_slot5 = &hydra_sg_slot5; |
| hydra_sg_slot6 = &hydra_sg_slot6; |
| hydra_xg_slot1 = &hydra_xg_slot1; |
| hydra_xg_slot2 = &hydra_xg_slot2; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| bman_fbpr: bman-fbpr { |
| size = <0 0x1000000>; |
| alignment = <0 0x1000000>; |
| }; |
| qman_fqd: qman-fqd { |
| size = <0 0x400000>; |
| alignment = <0 0x400000>; |
| }; |
| qman_pfdr: qman-pfdr { |
| size = <0 0x2000000>; |
| alignment = <0 0x2000000>; |
| }; |
| }; |
| |
| dcsr: dcsr@f00000000 { |
| ranges = <0x00000000 0xf 0x00000000 0x01008000>; |
| }; |
| |
| bportals: bman-portals@ff4000000 { |
| ranges = <0x0 0xf 0xf4000000 0x200000>; |
| }; |
| |
| qportals: qman-portals@ff4200000 { |
| ranges = <0x0 0xf 0xf4200000 0x200000>; |
| }; |
| |
| soc: soc@ffe000000 { |
| ranges = <0x00000000 0xf 0xfe000000 0x1000000>; |
| reg = <0xf 0xfe000000 0 0x00001000>; |
| spi@110000 { |
| flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "spansion,s25sl12801", "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <40000000>; /* input clock */ |
| partition@u-boot { |
| label = "u-boot"; |
| reg = <0x00000000 0x00100000>; |
| }; |
| partition@kernel { |
| label = "kernel"; |
| reg = <0x00100000 0x00500000>; |
| }; |
| partition@dtb { |
| label = "dtb"; |
| reg = <0x00600000 0x00100000>; |
| }; |
| partition@fs { |
| label = "file system"; |
| reg = <0x00700000 0x00900000>; |
| }; |
| }; |
| }; |
| |
| i2c@118100 { |
| eeprom@51 { |
| compatible = "atmel,24c256"; |
| reg = <0x51>; |
| }; |
| eeprom@52 { |
| compatible = "atmel,24c256"; |
| reg = <0x52>; |
| }; |
| }; |
| |
| i2c@119100 { |
| rtc@68 { |
| compatible = "dallas,ds3232"; |
| reg = <0x68>; |
| interrupts = <0x1 0x1 0 0>; |
| }; |
| ina220@40 { |
| compatible = "ti,ina220"; |
| reg = <0x40>; |
| shunt-resistor = <1000>; |
| }; |
| ina220@41 { |
| compatible = "ti,ina220"; |
| reg = <0x41>; |
| shunt-resistor = <1000>; |
| }; |
| ina220@44 { |
| compatible = "ti,ina220"; |
| reg = <0x44>; |
| shunt-resistor = <1000>; |
| }; |
| ina220@45 { |
| compatible = "ti,ina220"; |
| reg = <0x45>; |
| shunt-resistor = <1000>; |
| }; |
| adt7461@4c { |
| compatible = "adi,adt7461"; |
| reg = <0x4c>; |
| }; |
| }; |
| |
| fman@400000 { |
| ethernet@e0000 { |
| phy-connection-type = "sgmii"; |
| }; |
| |
| ethernet@e2000 { |
| phy-connection-type = "sgmii"; |
| }; |
| |
| ethernet@e4000 { |
| phy-connection-type = "sgmii"; |
| }; |
| |
| ethernet@e6000 { |
| phy-connection-type = "sgmii"; |
| }; |
| |
| ethernet@e8000 { |
| phy-handle = <&phy_rgmii_0>; |
| phy-connection-type = "rgmii"; |
| }; |
| |
| ethernet@f0000 { |
| phy-handle = <&phy_xgmii_slot_2>; |
| phy-connection-type = "xgmii"; |
| }; |
| }; |
| |
| fman@500000 { |
| ethernet@e0000 { |
| phy-connection-type = "sgmii"; |
| }; |
| |
| ethernet@e2000 { |
| phy-connection-type = "sgmii"; |
| }; |
| |
| ethernet@e4000 { |
| phy-connection-type = "sgmii"; |
| }; |
| |
| ethernet@e6000 { |
| phy-connection-type = "sgmii"; |
| }; |
| |
| ethernet@e8000 { |
| phy-handle = <&phy_rgmii_1>; |
| phy-connection-type = "rgmii"; |
| }; |
| |
| ethernet@f0000 { |
| phy-handle = <&phy_xgmii_slot_1>; |
| phy-connection-type = "xgmii"; |
| }; |
| }; |
| }; |
| |
| lbc: localbus@ffe124000 { |
| reg = <0xf 0xfe124000 0 0x1000>; |
| ranges = <0 0 0xf 0xe8000000 0x08000000 |
| 2 0 0xf 0xffa00000 0x00040000 |
| 3 0 0xf 0xffdf0000 0x00008000>; |
| |
| flash@0,0 { |
| compatible = "cfi-flash"; |
| reg = <0 0 0x08000000>; |
| bank-width = <2>; |
| device-width = <2>; |
| }; |
| |
| nand@2,0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,elbc-fcm-nand"; |
| reg = <0x2 0x0 0x40000>; |
| |
| partition@0 { |
| label = "NAND U-Boot Image"; |
| reg = <0x0 0x02000000>; |
| }; |
| |
| partition@2000000 { |
| label = "NAND Root File System"; |
| reg = <0x02000000 0x10000000>; |
| }; |
| |
| partition@12000000 { |
| label = "NAND Compressed RFS Image"; |
| reg = <0x12000000 0x08000000>; |
| }; |
| |
| partition@1a000000 { |
| label = "NAND Linux Kernel Image"; |
| reg = <0x1a000000 0x04000000>; |
| }; |
| |
| partition@1e000000 { |
| label = "NAND DTB Image"; |
| reg = <0x1e000000 0x01000000>; |
| }; |
| |
| partition@1f000000 { |
| label = "NAND Writable User area"; |
| reg = <0x1f000000 0x01000000>; |
| }; |
| }; |
| |
| board-control@3,0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis"; |
| reg = <3 0 0x40>; |
| ranges = <0 3 0 0x40>; |
| |
| mdio-mux-emi1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "mdio-mux-mmioreg", "mdio-mux"; |
| mdio-parent-bus = <&mdio0>; |
| reg = <9 1>; |
| mux-mask = <0x78>; |
| |
| hydra_rg:rgmii-mdio@8 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <8>; |
| status = "disabled"; |
| |
| phy_rgmii_0: ethernet-phy@0 { |
| reg = <0x0>; |
| }; |
| |
| phy_rgmii_1: ethernet-phy@1 { |
| reg = <0x1>; |
| }; |
| }; |
| |
| hydra_sg_slot2: sgmii-mdio@28 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x28>; |
| status = "disabled"; |
| |
| phy_sgmii_slot2_1c: ethernet-phy@1c { |
| reg = <0x1c>; |
| }; |
| |
| phy_sgmii_slot2_1d: ethernet-phy@1d { |
| reg = <0x1d>; |
| }; |
| |
| phy_sgmii_slot2_1e: ethernet-phy@1e { |
| reg = <0x1e>; |
| }; |
| |
| phy_sgmii_slot2_1f: ethernet-phy@1f { |
| reg = <0x1f>; |
| }; |
| }; |
| |
| hydra_sg_slot3: sgmii-mdio@68 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x68>; |
| status = "disabled"; |
| |
| phy_sgmii_slot3_1c: ethernet-phy@1c { |
| reg = <0x1c>; |
| }; |
| |
| phy_sgmii_slot3_1d: ethernet-phy@1d { |
| reg = <0x1d>; |
| }; |
| |
| phy_sgmii_slot3_1e: ethernet-phy@1e { |
| reg = <0x1e>; |
| }; |
| |
| phy_sgmii_slot3_1f: ethernet-phy@1f { |
| reg = <0x1f>; |
| }; |
| }; |
| |
| hydra_sg_slot5: sgmii-mdio@38 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x38>; |
| status = "disabled"; |
| |
| phy_sgmii_slot5_1c: ethernet-phy@1c { |
| reg = <0x1c>; |
| }; |
| |
| phy_sgmii_slot5_1d: ethernet-phy@1d { |
| reg = <0x1d>; |
| }; |
| |
| phy_sgmii_slot5_1e: ethernet-phy@1e { |
| reg = <0x1e>; |
| }; |
| |
| phy_sgmii_slot5_1f: ethernet-phy@1f { |
| reg = <0x1f>; |
| }; |
| }; |
| hydra_sg_slot6: sgmii-mdio@48 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x48>; |
| status = "disabled"; |
| |
| phy_sgmii_slot6_1c: ethernet-phy@1c { |
| reg = <0x1c>; |
| }; |
| |
| phy_sgmii_slot6_1d: ethernet-phy@1d { |
| reg = <0x1d>; |
| }; |
| |
| phy_sgmii_slot6_1e: ethernet-phy@1e { |
| reg = <0x1e>; |
| }; |
| |
| phy_sgmii_slot6_1f: ethernet-phy@1f { |
| reg = <0x1f>; |
| }; |
| }; |
| }; |
| |
| mdio-mux-emi2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "mdio-mux-mmioreg", "mdio-mux"; |
| mdio-parent-bus = <&xmdio0>; |
| reg = <9 1>; |
| mux-mask = <0x06>; |
| |
| hydra_xg_slot1: hydra-xg-slot1@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| status = "disabled"; |
| |
| phy_xgmii_slot_1: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| reg = <4>; |
| }; |
| }; |
| |
| hydra_xg_slot2: hydra-xg-slot2@2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <2>; |
| |
| phy_xgmii_slot_2: ethernet-phy@4 { |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| reg = <0>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| pci0: pcie@ffe200000 { |
| reg = <0xf 0xfe200000 0 0x1000>; |
| ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 |
| 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; |
| pcie@0 { |
| ranges = <0x02000000 0 0xe0000000 |
| 0x02000000 0 0xe0000000 |
| 0 0x20000000 |
| |
| 0x01000000 0 0x00000000 |
| 0x01000000 0 0x00000000 |
| 0 0x00010000>; |
| }; |
| }; |
| |
| pci1: pcie@ffe201000 { |
| reg = <0xf 0xfe201000 0 0x1000>; |
| ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 |
| 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; |
| pcie@0 { |
| ranges = <0x02000000 0 0xe0000000 |
| 0x02000000 0 0xe0000000 |
| 0 0x20000000 |
| |
| 0x01000000 0 0x00000000 |
| 0x01000000 0 0x00000000 |
| 0 0x00010000>; |
| }; |
| }; |
| |
| pci2: pcie@ffe202000 { |
| reg = <0xf 0xfe202000 0 0x1000>; |
| ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 |
| 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; |
| pcie@0 { |
| ranges = <0x02000000 0 0xe0000000 |
| 0x02000000 0 0xe0000000 |
| 0 0x20000000 |
| |
| 0x01000000 0 0x00000000 |
| 0x01000000 0 0x00000000 |
| 0 0x00010000>; |
| }; |
| }; |
| }; |
| |
| /include/ "p5040si-post.dtsi" |
