| /* |
| * T4240 Silicon/SoC Device Tree Source (post include) |
| * |
| * Copyright 2012 - 2015 Freescale Semiconductor Inc. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * * Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * * Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * * Neither the name of Freescale Semiconductor nor the |
| * names of its contributors may be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * |
| * ALTERNATIVELY, this software may be distributed under the terms of the |
| * GNU General Public License ("GPL") as published by the Free Software |
| * Foundation, either version 2 of that License or (at your option) any |
| * later version. |
| * |
| * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
| * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
| * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| &bman_fbpr { |
| compatible = "fsl,bman-fbpr"; |
| alloc-ranges = <0 0 0x10000 0>; |
| }; |
| |
| &qman_fqd { |
| compatible = "fsl,qman-fqd"; |
| alloc-ranges = <0 0 0x10000 0>; |
| }; |
| |
| &qman_pfdr { |
| compatible = "fsl,qman-pfdr"; |
| alloc-ranges = <0 0 0x10000 0>; |
| }; |
| |
| &ifc { |
| #address-cells = <2>; |
| #size-cells = <1>; |
| compatible = "fsl,ifc", "simple-bus"; |
| interrupts = <25 2 0 0>; |
| }; |
| |
| /* controller at 0x240000 */ |
| &pci0 { |
| compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; |
| device_type = "pci"; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| bus-range = <0x0 0xff>; |
| interrupts = <20 2 0 0>; |
| pcie@0 { |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| reg = <0 0 0 0 0>; |
| interrupts = <20 2 0 0>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 40 1 0 0 |
| 0000 0 0 2 &mpic 1 1 0 0 |
| 0000 0 0 3 &mpic 2 1 0 0 |
| 0000 0 0 4 &mpic 3 1 0 0 |
| >; |
| }; |
| }; |
| |
| /* controller at 0x250000 */ |
| &pci1 { |
| compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; |
| device_type = "pci"; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| bus-range = <0 0xff>; |
| interrupts = <21 2 0 0>; |
| pcie@0 { |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| reg = <0 0 0 0 0>; |
| interrupts = <21 2 0 0>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 41 1 0 0 |
| 0000 0 0 2 &mpic 5 1 0 0 |
| 0000 0 0 3 &mpic 6 1 0 0 |
| 0000 0 0 4 &mpic 7 1 0 0 |
| >; |
| }; |
| }; |
| |
| /* controller at 0x260000 */ |
| &pci2 { |
| compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; |
| device_type = "pci"; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| bus-range = <0x0 0xff>; |
| interrupts = <22 2 0 0>; |
| pcie@0 { |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| reg = <0 0 0 0 0>; |
| interrupts = <22 2 0 0>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 42 1 0 0 |
| 0000 0 0 2 &mpic 9 1 0 0 |
| 0000 0 0 3 &mpic 10 1 0 0 |
| 0000 0 0 4 &mpic 11 1 0 0 |
| >; |
| }; |
| }; |
| |
| /* controller at 0x270000 */ |
| &pci3 { |
| compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; |
| device_type = "pci"; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| bus-range = <0x0 0xff>; |
| interrupts = <23 2 0 0>; |
| pcie@0 { |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| reg = <0 0 0 0 0>; |
| interrupts = <23 2 0 0>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 43 1 0 0 |
| 0000 0 0 2 &mpic 0 1 0 0 |
| 0000 0 0 3 &mpic 4 1 0 0 |
| 0000 0 0 4 &mpic 8 1 0 0 |
| >; |
| }; |
| }; |
| |
| &rio { |
| compatible = "fsl,srio"; |
| interrupts = <16 2 1 11>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| port1 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| cell-index = <1>; |
| }; |
| |
| port2 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| cell-index = <2>; |
| }; |
| }; |
| |
| &dcsr { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,dcsr", "simple-bus"; |
| |
| dcsr-epu@0 { |
| compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu"; |
| interrupts = <52 2 0 0 |
| 84 2 0 0 |
| 85 2 0 0 |
| 94 2 0 0 |
| 95 2 0 0>; |
| reg = <0x0 0x1000>; |
| }; |
| dcsr-npc { |
| compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc"; |
| reg = <0x1000 0x1000 0x1002000 0x10000>; |
| }; |
| dcsr-nxc@2000 { |
| compatible = "fsl,dcsr-nxc"; |
| reg = <0x2000 0x1000>; |
| }; |
| dcsr-corenet { |
| compatible = "fsl,dcsr-corenet"; |
| reg = <0x8000 0x1000 0x1A000 0x1000>; |
| }; |
| dcsr-dpaa@9000 { |
| compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa"; |
| reg = <0x9000 0x1000>; |
| }; |
| dcsr-ocn@11000 { |
| compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn"; |
| reg = <0x11000 0x1000>; |
| }; |
| dcsr-ddr@12000 { |
| compatible = "fsl,dcsr-ddr"; |
| dev-handle = <&ddr1>; |
| reg = <0x12000 0x1000>; |
| }; |
| dcsr-ddr@13000 { |
| compatible = "fsl,dcsr-ddr"; |
| dev-handle = <&ddr2>; |
| reg = <0x13000 0x1000>; |
| }; |
| dcsr-ddr@14000 { |
| compatible = "fsl,dcsr-ddr"; |
| dev-handle = <&ddr3>; |
| reg = <0x14000 0x1000>; |
| }; |
| dcsr-nal@18000 { |
| compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal"; |
| reg = <0x18000 0x1000>; |
| }; |
| dcsr-rcpm@22000 { |
| compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm"; |
| reg = <0x22000 0x1000>; |
| }; |
| dcsr-snpc@30000 { |
| compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; |
| reg = <0x30000 0x1000 0x1022000 0x10000>; |
| }; |
| dcsr-snpc@31000 { |
| compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; |
| reg = <0x31000 0x1000 0x1042000 0x10000>; |
| }; |
| dcsr-snpc@32000 { |
| compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc"; |
| reg = <0x32000 0x1000 0x1062000 0x10000>; |
| }; |
| dcsr-cpu-sb-proxy@100000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu0>; |
| reg = <0x100000 0x1000 0x101000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@108000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu1>; |
| reg = <0x108000 0x1000 0x109000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@110000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu2>; |
| reg = <0x110000 0x1000 0x111000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@118000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu3>; |
| reg = <0x118000 0x1000 0x119000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@120000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu4>; |
| reg = <0x120000 0x1000 0x121000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@128000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu5>; |
| reg = <0x128000 0x1000 0x129000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@130000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu6>; |
| reg = <0x130000 0x1000 0x131000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@138000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu7>; |
| reg = <0x138000 0x1000 0x139000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@140000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu8>; |
| reg = <0x140000 0x1000 0x141000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@148000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu9>; |
| reg = <0x148000 0x1000 0x149000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@150000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu10>; |
| reg = <0x150000 0x1000 0x151000 0x1000>; |
| }; |
| dcsr-cpu-sb-proxy@158000 { |
| compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; |
| cpu-handle = <&cpu11>; |
| reg = <0x158000 0x1000 0x159000 0x1000>; |
| }; |
| }; |
| |
| &bportals { |
| #address-cells = <0x1>; |
| #size-cells = <0x1>; |
| compatible = "simple-bus"; |
| |
| bman-portal@0 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x0 0x4000>, <0x1000000 0x1000>; |
| interrupts = <105 2 0 0>; |
| }; |
| bman-portal@4000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x4000 0x4000>, <0x1001000 0x1000>; |
| interrupts = <107 2 0 0>; |
| }; |
| bman-portal@8000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x8000 0x4000>, <0x1002000 0x1000>; |
| interrupts = <109 2 0 0>; |
| }; |
| bman-portal@c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xc000 0x4000>, <0x1003000 0x1000>; |
| interrupts = <111 2 0 0>; |
| }; |
| bman-portal@10000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x10000 0x4000>, <0x1004000 0x1000>; |
| interrupts = <113 2 0 0>; |
| }; |
| bman-portal@14000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x14000 0x4000>, <0x1005000 0x1000>; |
| interrupts = <115 2 0 0>; |
| }; |
| bman-portal@18000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x18000 0x4000>, <0x1006000 0x1000>; |
| interrupts = <117 2 0 0>; |
| }; |
| bman-portal@1c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x1c000 0x4000>, <0x1007000 0x1000>; |
| interrupts = <119 2 0 0>; |
| }; |
| bman-portal@20000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x20000 0x4000>, <0x1008000 0x1000>; |
| interrupts = <121 2 0 0>; |
| }; |
| bman-portal@24000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x24000 0x4000>, <0x1009000 0x1000>; |
| interrupts = <123 2 0 0>; |
| }; |
| bman-portal@28000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x28000 0x4000>, <0x100a000 0x1000>; |
| interrupts = <125 2 0 0>; |
| }; |
| bman-portal@2c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x2c000 0x4000>, <0x100b000 0x1000>; |
| interrupts = <127 2 0 0>; |
| }; |
| bman-portal@30000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x30000 0x4000>, <0x100c000 0x1000>; |
| interrupts = <129 2 0 0>; |
| }; |
| bman-portal@34000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x34000 0x4000>, <0x100d000 0x1000>; |
| interrupts = <131 2 0 0>; |
| }; |
| bman-portal@38000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x38000 0x4000>, <0x100e000 0x1000>; |
| interrupts = <133 2 0 0>; |
| }; |
| bman-portal@3c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x3c000 0x4000>, <0x100f000 0x1000>; |
| interrupts = <135 2 0 0>; |
| }; |
| bman-portal@40000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x40000 0x4000>, <0x1010000 0x1000>; |
| interrupts = <137 2 0 0>; |
| }; |
| bman-portal@44000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x44000 0x4000>, <0x1011000 0x1000>; |
| interrupts = <139 2 0 0>; |
| }; |
| bman-portal@48000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x48000 0x4000>, <0x1012000 0x1000>; |
| interrupts = <141 2 0 0>; |
| }; |
| bman-portal@4c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x4c000 0x4000>, <0x1013000 0x1000>; |
| interrupts = <143 2 0 0>; |
| }; |
| bman-portal@50000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x50000 0x4000>, <0x1014000 0x1000>; |
| interrupts = <145 2 0 0>; |
| }; |
| bman-portal@54000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x54000 0x4000>, <0x1015000 0x1000>; |
| interrupts = <147 2 0 0>; |
| }; |
| bman-portal@58000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x58000 0x4000>, <0x1016000 0x1000>; |
| interrupts = <149 2 0 0>; |
| }; |
| bman-portal@5c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x5c000 0x4000>, <0x1017000 0x1000>; |
| interrupts = <151 2 0 0>; |
| }; |
| bman-portal@60000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x60000 0x4000>, <0x1018000 0x1000>; |
| interrupts = <153 2 0 0>; |
| }; |
| bman-portal@64000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x64000 0x4000>, <0x1019000 0x1000>; |
| interrupts = <155 2 0 0>; |
| }; |
| bman-portal@68000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x68000 0x4000>, <0x101a000 0x1000>; |
| interrupts = <157 2 0 0>; |
| }; |
| bman-portal@6c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x6c000 0x4000>, <0x101b000 0x1000>; |
| interrupts = <159 2 0 0>; |
| }; |
| bman-portal@70000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x70000 0x4000>, <0x101c000 0x1000>; |
| interrupts = <161 2 0 0>; |
| }; |
| bman-portal@74000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x74000 0x4000>, <0x101d000 0x1000>; |
| interrupts = <163 2 0 0>; |
| }; |
| bman-portal@78000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x78000 0x4000>, <0x101e000 0x1000>; |
| interrupts = <165 2 0 0>; |
| }; |
| bman-portal@7c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x7c000 0x4000>, <0x101f000 0x1000>; |
| interrupts = <167 2 0 0>; |
| }; |
| bman-portal@80000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x80000 0x4000>, <0x1020000 0x1000>; |
| interrupts = <169 2 0 0>; |
| }; |
| bman-portal@84000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x84000 0x4000>, <0x1021000 0x1000>; |
| interrupts = <171 2 0 0>; |
| }; |
| bman-portal@88000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x88000 0x4000>, <0x1022000 0x1000>; |
| interrupts = <173 2 0 0>; |
| }; |
| bman-portal@8c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x8c000 0x4000>, <0x1023000 0x1000>; |
| interrupts = <175 2 0 0>; |
| }; |
| bman-portal@90000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x90000 0x4000>, <0x1024000 0x1000>; |
| interrupts = <385 2 0 0>; |
| }; |
| bman-portal@94000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x94000 0x4000>, <0x1025000 0x1000>; |
| interrupts = <387 2 0 0>; |
| }; |
| bman-portal@98000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x98000 0x4000>, <0x1026000 0x1000>; |
| interrupts = <389 2 0 0>; |
| }; |
| bman-portal@9c000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0x9c000 0x4000>, <0x1027000 0x1000>; |
| interrupts = <391 2 0 0>; |
| }; |
| bman-portal@a0000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xa0000 0x4000>, <0x1028000 0x1000>; |
| interrupts = <393 2 0 0>; |
| }; |
| bman-portal@a4000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xa4000 0x4000>, <0x1029000 0x1000>; |
| interrupts = <395 2 0 0>; |
| }; |
| bman-portal@a8000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xa8000 0x4000>, <0x102a000 0x1000>; |
| interrupts = <397 2 0 0>; |
| }; |
| bman-portal@ac000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xac000 0x4000>, <0x102b000 0x1000>; |
| interrupts = <399 2 0 0>; |
| }; |
| bman-portal@b0000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xb0000 0x4000>, <0x102c000 0x1000>; |
| interrupts = <401 2 0 0>; |
| }; |
| bman-portal@b4000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xb4000 0x4000>, <0x102d000 0x1000>; |
| interrupts = <403 2 0 0>; |
| }; |
| bman-portal@b8000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xb8000 0x4000>, <0x102e000 0x1000>; |
| interrupts = <405 2 0 0>; |
| }; |
| bman-portal@bc000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xbc000 0x4000>, <0x102f000 0x1000>; |
| interrupts = <407 2 0 0>; |
| }; |
| bman-portal@c0000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xc0000 0x4000>, <0x1030000 0x1000>; |
| interrupts = <409 2 0 0>; |
| }; |
| bman-portal@c4000 { |
| compatible = "fsl,bman-portal"; |
| reg = <0xc4000 0x4000>, <0x1031000 0x1000>; |
| interrupts = <411 2 0 0>; |
| }; |
| }; |
| |
| &qportals { |
| #address-cells = <0x1>; |
| #size-cells = <0x1>; |
| compatible = "simple-bus"; |
| |
| qportal0: qman-portal@0 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x0 0x4000>, <0x1000000 0x1000>; |
| interrupts = <104 0x2 0 0>; |
| cell-index = <0x0>; |
| }; |
| qportal1: qman-portal@4000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x4000 0x4000>, <0x1001000 0x1000>; |
| interrupts = <106 0x2 0 0>; |
| cell-index = <0x1>; |
| }; |
| qportal2: qman-portal@8000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x8000 0x4000>, <0x1002000 0x1000>; |
| interrupts = <108 0x2 0 0>; |
| cell-index = <0x2>; |
| }; |
| qportal3: qman-portal@c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xc000 0x4000>, <0x1003000 0x1000>; |
| interrupts = <110 0x2 0 0>; |
| cell-index = <0x3>; |
| }; |
| qportal4: qman-portal@10000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x10000 0x4000>, <0x1004000 0x1000>; |
| interrupts = <112 0x2 0 0>; |
| cell-index = <0x4>; |
| }; |
| qportal5: qman-portal@14000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x14000 0x4000>, <0x1005000 0x1000>; |
| interrupts = <114 0x2 0 0>; |
| cell-index = <0x5>; |
| }; |
| qportal6: qman-portal@18000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x18000 0x4000>, <0x1006000 0x1000>; |
| interrupts = <116 0x2 0 0>; |
| cell-index = <0x6>; |
| }; |
| qportal7: qman-portal@1c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x1c000 0x4000>, <0x1007000 0x1000>; |
| interrupts = <118 0x2 0 0>; |
| cell-index = <0x7>; |
| }; |
| qportal8: qman-portal@20000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x20000 0x4000>, <0x1008000 0x1000>; |
| interrupts = <120 0x2 0 0>; |
| cell-index = <0x8>; |
| }; |
| qportal9: qman-portal@24000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x24000 0x4000>, <0x1009000 0x1000>; |
| interrupts = <122 0x2 0 0>; |
| cell-index = <0x9>; |
| }; |
| qportal10: qman-portal@28000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x28000 0x4000>, <0x100a000 0x1000>; |
| interrupts = <124 0x2 0 0>; |
| cell-index = <0xa>; |
| }; |
| qportal11: qman-portal@2c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x2c000 0x4000>, <0x100b000 0x1000>; |
| interrupts = <126 0x2 0 0>; |
| cell-index = <0xb>; |
| }; |
| qportal12: qman-portal@30000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x30000 0x4000>, <0x100c000 0x1000>; |
| interrupts = <128 0x2 0 0>; |
| cell-index = <0xc>; |
| }; |
| qportal13: qman-portal@34000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x34000 0x4000>, <0x100d000 0x1000>; |
| interrupts = <130 0x2 0 0>; |
| cell-index = <0xd>; |
| }; |
| qportal14: qman-portal@38000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x38000 0x4000>, <0x100e000 0x1000>; |
| interrupts = <132 0x2 0 0>; |
| cell-index = <0xe>; |
| }; |
| qportal15: qman-portal@3c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x3c000 0x4000>, <0x100f000 0x1000>; |
| interrupts = <134 0x2 0 0>; |
| cell-index = <0xf>; |
| }; |
| qportal16: qman-portal@40000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x40000 0x4000>, <0x1010000 0x1000>; |
| interrupts = <136 0x2 0 0>; |
| cell-index = <0x10>; |
| }; |
| qportal17: qman-portal@44000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x44000 0x4000>, <0x1011000 0x1000>; |
| interrupts = <138 0x2 0 0>; |
| cell-index = <0x11>; |
| }; |
| qportal18: qman-portal@48000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x48000 0x4000>, <0x1012000 0x1000>; |
| interrupts = <140 0x2 0 0>; |
| cell-index = <0x12>; |
| }; |
| qportal19: qman-portal@4c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x4c000 0x4000>, <0x1013000 0x1000>; |
| interrupts = <142 0x2 0 0>; |
| cell-index = <0x13>; |
| }; |
| qportal20: qman-portal@50000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x50000 0x4000>, <0x1014000 0x1000>; |
| interrupts = <144 0x2 0 0>; |
| cell-index = <0x14>; |
| }; |
| qportal21: qman-portal@54000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x54000 0x4000>, <0x1015000 0x1000>; |
| interrupts = <146 0x2 0 0>; |
| cell-index = <0x15>; |
| }; |
| qportal22: qman-portal@58000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x58000 0x4000>, <0x1016000 0x1000>; |
| interrupts = <148 0x2 0 0>; |
| cell-index = <0x16>; |
| }; |
| qportal23: qman-portal@5c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x5c000 0x4000>, <0x1017000 0x1000>; |
| interrupts = <150 0x2 0 0>; |
| cell-index = <0x17>; |
| }; |
| qportal24: qman-portal@60000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x60000 0x4000>, <0x1018000 0x1000>; |
| interrupts = <152 0x2 0 0>; |
| cell-index = <0x18>; |
| }; |
| qportal25: qman-portal@64000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x64000 0x4000>, <0x1019000 0x1000>; |
| interrupts = <154 0x2 0 0>; |
| cell-index = <0x19>; |
| }; |
| qportal26: qman-portal@68000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x68000 0x4000>, <0x101a000 0x1000>; |
| interrupts = <156 0x2 0 0>; |
| cell-index = <0x1a>; |
| }; |
| qportal27: qman-portal@6c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x6c000 0x4000>, <0x101b000 0x1000>; |
| interrupts = <158 0x2 0 0>; |
| cell-index = <0x1b>; |
| }; |
| qportal28: qman-portal@70000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x70000 0x4000>, <0x101c000 0x1000>; |
| interrupts = <160 0x2 0 0>; |
| cell-index = <0x1c>; |
| }; |
| qportal29: qman-portal@74000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x74000 0x4000>, <0x101d000 0x1000>; |
| interrupts = <162 0x2 0 0>; |
| cell-index = <0x1d>; |
| }; |
| qportal30: qman-portal@78000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x78000 0x4000>, <0x101e000 0x1000>; |
| interrupts = <164 0x2 0 0>; |
| cell-index = <0x1e>; |
| }; |
| qportal31: qman-portal@7c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x7c000 0x4000>, <0x101f000 0x1000>; |
| interrupts = <166 0x2 0 0>; |
| cell-index = <0x1f>; |
| }; |
| qportal32: qman-portal@80000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x80000 0x4000>, <0x1020000 0x1000>; |
| interrupts = <168 0x2 0 0>; |
| cell-index = <0x20>; |
| }; |
| qportal33: qman-portal@84000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x84000 0x4000>, <0x1021000 0x1000>; |
| interrupts = <170 0x2 0 0>; |
| cell-index = <0x21>; |
| }; |
| qportal34: qman-portal@88000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x88000 0x4000>, <0x1022000 0x1000>; |
| interrupts = <172 0x2 0 0>; |
| cell-index = <0x22>; |
| }; |
| qportal35: qman-portal@8c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x8c000 0x4000>, <0x1023000 0x1000>; |
| interrupts = <174 0x2 0 0>; |
| cell-index = <0x23>; |
| }; |
| qportal36: qman-portal@90000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x90000 0x4000>, <0x1024000 0x1000>; |
| interrupts = <384 0x2 0 0>; |
| cell-index = <0x24>; |
| }; |
| qportal37: qman-portal@94000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x94000 0x4000>, <0x1025000 0x1000>; |
| interrupts = <386 0x2 0 0>; |
| cell-index = <0x25>; |
| }; |
| qportal38: qman-portal@98000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x98000 0x4000>, <0x1026000 0x1000>; |
| interrupts = <388 0x2 0 0>; |
| cell-index = <0x26>; |
| }; |
| qportal39: qman-portal@9c000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0x9c000 0x4000>, <0x1027000 0x1000>; |
| interrupts = <390 0x2 0 0>; |
| cell-index = <0x27>; |
| }; |
| qportal40: qman-portal@a0000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xa0000 0x4000>, <0x1028000 0x1000>; |
| interrupts = <392 0x2 0 0>; |
| cell-index = <0x28>; |
| }; |
| qportal41: qman-portal@a4000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xa4000 0x4000>, <0x1029000 0x1000>; |
| interrupts = <394 0x2 0 0>; |
| cell-index = <0x29>; |
| }; |
| qportal42: qman-portal@a8000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xa8000 0x4000>, <0x102a000 0x1000>; |
| interrupts = <396 0x2 0 0>; |
| cell-index = <0x2a>; |
| }; |
| qportal43: qman-portal@ac000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xac000 0x4000>, <0x102b000 0x1000>; |
| interrupts = <398 0x2 0 0>; |
| cell-index = <0x2b>; |
| }; |
| qportal44: qman-portal@b0000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xb0000 0x4000>, <0x102c000 0x1000>; |
| interrupts = <400 0x2 0 0>; |
| cell-index = <0x2c>; |
| }; |
| qportal45: qman-portal@b4000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xb4000 0x4000>, <0x102d000 0x1000>; |
| interrupts = <402 0x2 0 0>; |
| cell-index = <0x2d>; |
| }; |
| qportal46: qman-portal@b8000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xb8000 0x4000>, <0x102e000 0x1000>; |
| interrupts = <404 0x2 0 0>; |
| cell-index = <0x2e>; |
| }; |
| qportal47: qman-portal@bc000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xbc000 0x4000>, <0x102f000 0x1000>; |
| interrupts = <406 0x2 0 0>; |
| cell-index = <0x2f>; |
| }; |
| qportal48: qman-portal@c0000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xc0000 0x4000>, <0x1030000 0x1000>; |
| interrupts = <408 0x2 0 0>; |
| cell-index = <0x30>; |
| }; |
| qportal49: qman-portal@c4000 { |
| compatible = "fsl,qman-portal"; |
| reg = <0xc4000 0x4000>, <0x1031000 0x1000>; |
| interrupts = <410 0x2 0 0>; |
| cell-index = <0x31>; |
| }; |
| }; |
| |
| &soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| compatible = "simple-bus"; |
| |
| soc-sram-error { |
| compatible = "fsl,soc-sram-error"; |
| interrupts = <16 2 1 29>; |
| }; |
| |
| corenet-law@0 { |
| compatible = "fsl,corenet-law"; |
| reg = <0x0 0x1000>; |
| fsl,num-laws = <32>; |
| }; |
| |
| ddr1: memory-controller@8000 { |
| compatible = "fsl,qoriq-memory-controller-v4.7", |
| "fsl,qoriq-memory-controller"; |
| reg = <0x8000 0x1000>; |
| interrupts = <16 2 1 23>; |
| }; |
| |
| ddr2: memory-controller@9000 { |
| compatible = "fsl,qoriq-memory-controller-v4.7", |
| "fsl,qoriq-memory-controller"; |
| reg = <0x9000 0x1000>; |
| interrupts = <16 2 1 22>; |
| }; |
| |
| ddr3: memory-controller@a000 { |
| compatible = "fsl,qoriq-memory-controller-v4.7", |
| "fsl,qoriq-memory-controller"; |
| reg = <0xa000 0x1000>; |
| interrupts = <16 2 1 21>; |
| }; |
| |
| cpc: l3-cache-controller@10000 { |
| compatible = "fsl,t4240-l3-cache-controller", "cache"; |
| reg = <0x10000 0x1000 |
| 0x11000 0x1000 |
| 0x12000 0x1000>; |
| interrupts = <16 2 1 27 |
| 16 2 1 26 |
| 16 2 1 25>; |
| }; |
| |
| corenet-cf@18000 { |
| compatible = "fsl,corenet2-cf", "fsl,corenet-cf"; |
| reg = <0x18000 0x1000>; |
| interrupts = <16 2 1 31>; |
| fsl,ccf-num-csdids = <32>; |
| fsl,ccf-num-snoopids = <32>; |
| }; |
| |
| iommu@20000 { |
| compatible = "fsl,pamu-v1.0", "fsl,pamu"; |
| reg = <0x20000 0x6000>; |
| fsl,portid-mapping = <0x8000>; |
| interrupts = < |
| 24 2 0 0 |
| 16 2 1 30>; |
| }; |
| |
| /include/ "qoriq-mpic4.3.dtsi" |
| |
| guts: global-utilities@e0000 { |
| compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0"; |
| reg = <0xe0000 0xe00>; |
| fsl,has-rstcr; |
| fsl,liodn-bits = <12>; |
| }; |
| |
| /include/ "qoriq-clockgen2.dtsi" |
| global-utilities@e1000 { |
| compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; |
| |
| pll2: pll2@840 { |
| #clock-cells = <1>; |
| reg = <0x840 0x4>; |
| compatible = "fsl,qoriq-core-pll-2.0"; |
| clocks = <&sysclk>; |
| clock-output-names = "pll2", "pll2-div2", "pll2-div4"; |
| }; |
| |
| pll3: pll3@860 { |
| #clock-cells = <1>; |
| reg = <0x860 0x4>; |
| compatible = "fsl,qoriq-core-pll-2.0"; |
| clocks = <&sysclk>; |
| clock-output-names = "pll3", "pll3-div2", "pll3-div4"; |
| }; |
| |
| pll4: pll4@880 { |
| #clock-cells = <1>; |
| reg = <0x880 0x4>; |
| compatible = "fsl,qoriq-core-pll-2.0"; |
| clocks = <&sysclk>; |
| clock-output-names = "pll4", "pll4-div2", "pll4-div4"; |
| }; |
| |
| mux0: mux0@0 { |
| #clock-cells = <0>; |
| reg = <0x0 0x4>; |
| compatible = "fsl,qoriq-core-mux-2.0"; |
| clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, |
| <&pll1 0>, <&pll1 1>, <&pll1 2>, |
| <&pll2 0>, <&pll2 1>, <&pll2 2>; |
| clock-names = "pll0", "pll0-div2", "pll0-div4", |
| "pll1", "pll1-div2", "pll1-div4", |
| "pll2", "pll2-div2", "pll2-div4"; |
| clock-output-names = "cmux0"; |
| }; |
| |
| mux1: mux1@20 { |
| #clock-cells = <0>; |
| reg = <0x20 0x4>; |
| compatible = "fsl,qoriq-core-mux-2.0"; |
| clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, |
| <&pll1 0>, <&pll1 1>, <&pll1 2>, |
| <&pll2 0>, <&pll2 1>, <&pll2 2>; |
| clock-names = "pll0", "pll0-div2", "pll0-div4", |
| "pll1", "pll1-div2", "pll1-div4", |
| "pll2", "pll2-div2", "pll2-div4"; |
| clock-output-names = "cmux1"; |
| }; |
| |
| mux2: mux2@40 { |
| #clock-cells = <0>; |
| reg = <0x40 0x4>; |
| compatible = "fsl,qoriq-core-mux-2.0"; |
| clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, |
| <&pll4 0>, <&pll4 1>, <&pll4 2>; |
| clock-names = "pll3", "pll3-div2", "pll3-div4", |
| "pll4", "pll4-div2", "pll4-div4"; |
| clock-output-names = "cmux2"; |
| }; |
| }; |
| |
| rcpm: global-utilities@e2000 { |
| compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; |
| reg = <0xe2000 0x1000>; |
| }; |
| |
| sfp: sfp@e8000 { |
| compatible = "fsl,t4240-sfp"; |
| reg = <0xe8000 0x1000>; |
| }; |
| |
| serdes: serdes@ea000 { |
| compatible = "fsl,t4240-serdes"; |
| reg = <0xea000 0x4000>; |
| }; |
| |
| /include/ "elo3-dma-0.dtsi" |
| /include/ "elo3-dma-1.dtsi" |
| /include/ "elo3-dma-2.dtsi" |
| |
| /include/ "qoriq-espi-0.dtsi" |
| spi@110000 { |
| fsl,espi-num-chipselects = <4>; |
| }; |
| |
| /include/ "qoriq-esdhc-0.dtsi" |
| sdhc@114000 { |
| compatible = "fsl,t4240-esdhc", "fsl,esdhc"; |
| sdhci,auto-cmd12; |
| }; |
| /include/ "qoriq-i2c-0.dtsi" |
| /include/ "qoriq-i2c-1.dtsi" |
| /include/ "qoriq-duart-0.dtsi" |
| /include/ "qoriq-duart-1.dtsi" |
| /include/ "qoriq-gpio-0.dtsi" |
| /include/ "qoriq-gpio-1.dtsi" |
| /include/ "qoriq-gpio-2.dtsi" |
| /include/ "qoriq-gpio-3.dtsi" |
| /include/ "qoriq-usb2-mph-0.dtsi" |
| usb0: usb@210000 { |
| compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph"; |
| phy_type = "utmi"; |
| port0; |
| }; |
| /include/ "qoriq-usb2-dr-0.dtsi" |
| usb1: usb@211000 { |
| compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; |
| dr_mode = "host"; |
| phy_type = "utmi"; |
| }; |
| /include/ "qoriq-sata2-0.dtsi" |
| /include/ "qoriq-sata2-1.dtsi" |
| /include/ "qoriq-sec5.0-0.dtsi" |
| /include/ "qoriq-qman3.dtsi" |
| /include/ "qoriq-bman1.dtsi" |
| |
| /include/ "qoriq-fman3-0.dtsi" |
| /include/ "qoriq-fman3-0-1g-0.dtsi" |
| /include/ "qoriq-fman3-0-1g-1.dtsi" |
| /include/ "qoriq-fman3-0-1g-2.dtsi" |
| /include/ "qoriq-fman3-0-1g-3.dtsi" |
| /include/ "qoriq-fman3-0-1g-4.dtsi" |
| /include/ "qoriq-fman3-0-1g-5.dtsi" |
| /include/ "qoriq-fman3-0-10g-0.dtsi" |
| /include/ "qoriq-fman3-0-10g-1.dtsi" |
| fman@400000 { |
| enet0: ethernet@e0000 { |
| }; |
| |
| enet1: ethernet@e2000 { |
| }; |
| |
| enet2: ethernet@e4000 { |
| }; |
| |
| enet3: ethernet@e6000 { |
| }; |
| |
| enet4: ethernet@e8000 { |
| }; |
| |
| enet5: ethernet@ea000 { |
| }; |
| |
| enet6: ethernet@f0000 { |
| }; |
| |
| enet7: ethernet@f2000 { |
| }; |
| |
| mdio@fc000 { |
| status = "disabled"; |
| }; |
| |
| mdio@fd000 { |
| status = "disabled"; |
| }; |
| }; |
| |
| /include/ "qoriq-fman3-1.dtsi" |
| /include/ "qoriq-fman3-1-1g-0.dtsi" |
| /include/ "qoriq-fman3-1-1g-1.dtsi" |
| /include/ "qoriq-fman3-1-1g-2.dtsi" |
| /include/ "qoriq-fman3-1-1g-3.dtsi" |
| /include/ "qoriq-fman3-1-1g-4.dtsi" |
| /include/ "qoriq-fman3-1-1g-5.dtsi" |
| /include/ "qoriq-fman3-1-10g-0.dtsi" |
| /include/ "qoriq-fman3-1-10g-1.dtsi" |
| fman@500000 { |
| enet8: ethernet@e0000 { |
| }; |
| |
| enet9: ethernet@e2000 { |
| }; |
| |
| enet10: ethernet@e4000 { |
| }; |
| |
| enet11: ethernet@e6000 { |
| }; |
| |
| enet12: ethernet@e8000 { |
| }; |
| |
| enet13: ethernet@ea000 { |
| }; |
| |
| enet14: ethernet@f0000 { |
| }; |
| |
| enet15: ethernet@f2000 { |
| }; |
| |
| mdio@fc000 { |
| interrupts = <100 1 0 0>; |
| }; |
| |
| mdio@fd000 { |
| interrupts = <101 1 0 0>; |
| }; |
| }; |
| |
| L2_1: l2-cache-controller@c20000 { |
| compatible = "fsl,t4240-l2-cache-controller"; |
| reg = <0xc20000 0x40000>; |
| next-level-cache = <&cpc>; |
| }; |
| L2_2: l2-cache-controller@c60000 { |
| compatible = "fsl,t4240-l2-cache-controller"; |
| reg = <0xc60000 0x40000>; |
| next-level-cache = <&cpc>; |
| }; |
| L2_3: l2-cache-controller@ca0000 { |
| compatible = "fsl,t4240-l2-cache-controller"; |
| reg = <0xca0000 0x40000>; |
| next-level-cache = <&cpc>; |
| }; |
| }; |
