arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi - arm/linux - Git at Google

 /*
  * Copyright (c) 2016 Andreas Färber
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
  * licensing only applies to this file, and not this project as a
  * whole.
  *
  *  a) This library is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
  *     This library is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  * Or, alternatively,
  *
  *  b) Permission is hereby granted, free of charge, to any person
  *     obtaining a copy of this software and associated documentation
  *     files (the "Software"), to deal in the Software without
  *     restriction, including without limitation the rights to use,
  *     copy, modify, merge, publish, distribute, sublicense, and/or
  *     sell copies of the Software, and to permit persons to whom the
  *     Software is furnished to do so, subject to the following
  *     conditions:
  *
  *     The above copyright notice and this permission notice shall be
  *     included in all copies or substantial portions of the Software.
  *
  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */

 #include "meson-gx.dtsi"
 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
 #include <dt-bindings/clock/gxbb-clkc.h>
 #include <dt-bindings/clock/gxbb-aoclkc.h>
 #include <dt-bindings/reset/gxbb-aoclkc.h>

 / {
 	compatible = "amlogic,meson-gxbb";

 	soc {
 		usb0_phy: phy@c0000000 {
 			compatible = "amlogic,meson-gxbb-usb2-phy";
 			#phy-cells = <0>;
 			reg = <0x0 0xc0000000 0x0 0x20>;
 			resets = <&reset RESET_USB_OTG>;
 			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 			clock-names = "usb_general", "usb";
 			status = "disabled";
 		};

 		usb1_phy: phy@c0000020 {
 			compatible = "amlogic,meson-gxbb-usb2-phy";
 			#phy-cells = <0>;
 			reg = <0x0 0xc0000020 0x0 0x20>;
 			resets = <&reset RESET_USB_OTG>;
 			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 			clock-names = "usb_general", "usb";
 			status = "disabled";
 		};

 		usb0: usb@c9000000 {
 			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
 			reg = <0x0 0xc9000000 0x0 0x40000>;
 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 			clock-names = "otg";
 			phys = <&usb0_phy>;
 			phy-names = "usb2-phy";
 			dr_mode = "host";
 			status = "disabled";
 		};

 		usb1: usb@c9100000 {
 			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
 			reg = <0x0 0xc9100000 0x0 0x40000>;
 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 			clock-names = "otg";
 			phys = <&usb1_phy>;
 			phy-names = "usb2-phy";
 			dr_mode = "host";
 			status = "disabled";
 		};
 	};
 };

 &aobus {
 	pinctrl_aobus: pinctrl@14 {
 		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

 		gpio_ao: bank@14 {
 			reg = <0x0 0x00014 0x0 0x8>,
 			      <0x0 0x0002c 0x0 0x4>,
 			      <0x0 0x00024 0x0 0x8>;
 			reg-names = "mux", "pull", "gpio";
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-ranges = <&pinctrl_aobus 0 0 14>;
 		};

 		uart_ao_a_pins: uart_ao_a {
 			mux {
 				groups = "uart_tx_ao_a", "uart_rx_ao_a";
 				function = "uart_ao";
 			};
 		};

 		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 			mux {
 				groups = "uart_cts_ao_a",
 				       "uart_rts_ao_a";
 				function = "uart_ao";
 			};
 		};

 		uart_ao_b_pins: uart_ao_b {
 			mux {
 				groups = "uart_tx_ao_b", "uart_rx_ao_b";
 				function = "uart_ao_b";
 			};
 		};

 		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 			mux {
 				groups = "uart_cts_ao_b",
 				       "uart_rts_ao_b";
 				function = "uart_ao_b";
 			};
 		};

 		remote_input_ao_pins: remote_input_ao {
 			mux {
 				groups = "remote_input_ao";
 				function = "remote_input_ao";
 			};
 		};

 		i2c_ao_pins: i2c_ao {
 			mux {
 				groups = "i2c_sck_ao",
 				       "i2c_sda_ao";
 				function = "i2c_ao";
 			};
 		};

 		pwm_ao_a_3_pins: pwm_ao_a_3 {
 			mux {
 				groups = "pwm_ao_a_3";
 				function = "pwm_ao_a_3";
 			};
 		};

 		pwm_ao_a_6_pins: pwm_ao_a_6 {
 			mux {
 				groups = "pwm_ao_a_6";
 				function = "pwm_ao_a_6";
 			};
 		};

 		pwm_ao_a_12_pins: pwm_ao_a_12 {
 			mux {
 				groups = "pwm_ao_a_12";
 				function = "pwm_ao_a_12";
 			};
 		};

 		pwm_ao_b_pins: pwm_ao_b {
 			mux {
 				groups = "pwm_ao_b";
 				function = "pwm_ao_b";
 			};
 		};

 		i2s_am_clk_pins: i2s_am_clk {
 			mux {
 				groups = "i2s_am_clk";
 				function = "i2s_out_ao";
 			};
 		};

 		i2s_out_ao_clk_pins: i2s_out_ao_clk {
 			mux {
 				groups = "i2s_out_ao_clk";
 				function = "i2s_out_ao";
 			};
 		};

 		i2s_out_lr_clk_pins: i2s_out_lr_clk {
 			mux {
 				groups = "i2s_out_lr_clk";
 				function = "i2s_out_ao";
 			};
 		};

 		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
 			mux {
 				groups = "i2s_out_ch01_ao";
 				function = "i2s_out_ao";
 			};
 		};

 		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 			mux {
 				groups = "i2s_out_ch23_ao";
 				function = "i2s_out_ao";
 			};
 		};

 		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 			mux {
 				groups = "i2s_out_ch45_ao";
 				function = "i2s_out_ao";
 			};
 		};

 		spdif_out_ao_6_pins: spdif_out_ao_6 {
 			mux {
 				groups = "spdif_out_ao_6";
 				function = "spdif_out_ao";
 			};
 		};

 		spdif_out_ao_13_pins: spdif_out_ao_13 {
 			mux {
 				groups = "spdif_out_ao_13";
 				function = "spdif_out_ao";
 			};
 		};

 		ao_cec_pins: ao_cec {
 			mux {
 				groups = "ao_cec";
 				function = "cec_ao";
 			};
 		};

 		ee_cec_pins: ee_cec {
 			mux {
 				groups = "ee_cec";
 				function = "cec_ao";
 			};
 		};
 	};
 };

 &apb {
 	mali: gpu@c0000 {
 		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
 		reg = <0x0 0xc0000 0x0 0x40000>;
 		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "gp", "gpmmu", "pp", "pmu",
 			"pp0", "ppmmu0", "pp1", "ppmmu1",
 			"pp2", "ppmmu2";
 		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 		clock-names = "bus", "core";

 		/*
 		 * Mali clocking is provided by two identical clock paths
 		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
 		 * free mux to safely change frequency while running.
 		 */
 		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
 				  <&clkc CLKID_MALI_0>,
 				  <&clkc CLKID_MALI>; /* Glitch free mux */
 		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
 					 <0>, /* Do Nothing */
 					 <&clkc CLKID_MALI_0>;
 		assigned-clock-rates = <0>, /* Do Nothing */
 				       <666666666>,
 				       <0>; /* Do Nothing */
 	};
 };

 &cbus {
 	spifc: spi@8c80 {
 		compatible = "amlogic,meson-gxbb-spifc";
 		reg = <0x0 0x08c80 0x0 0x80>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&clkc CLKID_SPI>;
 		status = "disabled";
 	};
 };

 &cec_AO {
 	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 	clock-names = "core";
 };

 &clkc_AO {
 	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
 };

 &ethmac {
 	clocks = <&clkc CLKID_ETH>,
 		 <&clkc CLKID_FCLK_DIV2>,
 		 <&clkc CLKID_MPLL2>;
 	clock-names = "stmmaceth", "clkin0", "clkin1";
 };

 &hdmi_tx {
 	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 	resets = <&reset RESET_HDMITX_CAPB3>,
 		 <&reset RESET_HDMI_SYSTEM_RESET>,
 		 <&reset RESET_HDMI_TX>;
 	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 	clocks = <&clkc CLKID_HDMI_PCLK>,
 		 <&clkc CLKID_CLK81>,
 		 <&clkc CLKID_GCLK_VENCI_INT0>;
 	clock-names = "isfr", "iahb", "venci";
 };

 &hiubus {
 	clkc: clock-controller@0 {
 		compatible = "amlogic,gxbb-clkc";
 		#clock-cells = <1>;
 		reg = <0x0 0x0 0x0 0x3db>;
 	};
 };

 &hwrng {
 	clocks = <&clkc CLKID_RNG0>;
 	clock-names = "core";
 };

 &i2c_A {
 	clocks = <&clkc CLKID_I2C>;
 };

 &i2c_AO {
 	clocks = <&clkc CLKID_AO_I2C>;
 };

 &i2c_B {
 	clocks = <&clkc CLKID_I2C>;
 };

 &i2c_C {
 	clocks = <&clkc CLKID_I2C>;
 };

 &periphs {
 	pinctrl_periphs: pinctrl@4b0 {
 		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

 		gpio: bank@4b0 {
 			reg = <0x0 0x004b0 0x0 0x28>,
 			      <0x0 0x004e8 0x0 0x14>,
 			      <0x0 0x00520 0x0 0x14>,
 			      <0x0 0x00430 0x0 0x40>;
 			reg-names = "mux", "pull", "pull-enable", "gpio";
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-ranges = <&pinctrl_periphs 0 14 120>;
 		};

 		emmc_pins: emmc {
 			mux {
 				groups = "emmc_nand_d07",
 				       "emmc_cmd",
 				       "emmc_clk",
 				       "emmc_ds";
 				function = "emmc";
 			};
 		};

 		emmc_clk_gate_pins: emmc_clk_gate {
 			mux {
 				groups = "BOOT_8";
 				function = "gpio_periphs";
 			};
 			cfg-pull-down {
 				pins = "BOOT_8";
 				bias-pull-down;
 			};
 		};

 		nor_pins: nor {
 			mux {
 				groups = "nor_d",
 				       "nor_q",
 				       "nor_c",
 				       "nor_cs";
 				function = "nor";
 			};
 		};

 		spi_pins: spi {
 			mux {
 				groups = "spi_miso",
 					"spi_mosi",
 					"spi_sclk";
 				function = "spi";
 			};
 		};

 		spi_ss0_pins: spi-ss0 {
 			mux {
 				groups = "spi_ss0";
 				function = "spi";
 			};
 		};

 		sdcard_pins: sdcard {
 			mux {
 				groups = "sdcard_d0",
 				       "sdcard_d1",
 				       "sdcard_d2",
 				       "sdcard_d3",
 				       "sdcard_cmd",
 				       "sdcard_clk";
 				function = "sdcard";
 			};
 		};

 		sdcard_clk_gate_pins: sdcard_clk_gate {
 			mux {
 				groups = "CARD_2";
 				function = "gpio_periphs";
 			};
 			cfg-pull-down {
 				pins = "CARD_2";
 				bias-pull-down;
 			};
 		};

 		sdio_pins: sdio {
 			mux {
 				groups = "sdio_d0",
 				       "sdio_d1",
 				       "sdio_d2",
 				       "sdio_d3",
 				       "sdio_cmd",
 				       "sdio_clk";
 				function = "sdio";
 			};
 		};

 		sdio_clk_gate_pins: sdio_clk_gate {
 			mux {
 				groups = "GPIOX_4";
 				function = "gpio_periphs";
 			};
 			cfg-pull-down {
 				pins = "GPIOX_4";
 				bias-pull-down;
 			};
 		};

 		sdio_irq_pins: sdio_irq {
 			mux {
 				groups = "sdio_irq";
 				function = "sdio";
 			};
 		};

 		uart_a_pins: uart_a {
 			mux {
 				groups = "uart_tx_a",
 				       "uart_rx_a";
 				function = "uart_a";
 			};
 		};

 		uart_a_cts_rts_pins: uart_a_cts_rts {
 			mux {
 				groups = "uart_cts_a",
 				       "uart_rts_a";
 				function = "uart_a";
 			};
 		};

 		uart_b_pins: uart_b {
 			mux {
 				groups = "uart_tx_b",
 				       "uart_rx_b";
 				function = "uart_b";
 			};
 		};

 		uart_b_cts_rts_pins: uart_b_cts_rts {
 			mux {
 				groups = "uart_cts_b",
 				       "uart_rts_b";
 				function = "uart_b";
 			};
 		};

 		uart_c_pins: uart_c {
 			mux {
 				groups = "uart_tx_c",
 				       "uart_rx_c";
 				function = "uart_c";
 			};
 		};

 		uart_c_cts_rts_pins: uart_c_cts_rts {
 			mux {
 				groups = "uart_cts_c",
 				       "uart_rts_c";
 				function = "uart_c";
 			};
 		};

 		i2c_a_pins: i2c_a {
 			mux {
 				groups = "i2c_sck_a",
 				       "i2c_sda_a";
 				function = "i2c_a";
 			};
 		};

 		i2c_b_pins: i2c_b {
 			mux {
 				groups = "i2c_sck_b",
 				       "i2c_sda_b";
 				function = "i2c_b";
 			};
 		};

 		i2c_c_pins: i2c_c {
 			mux {
 				groups = "i2c_sck_c",
 				       "i2c_sda_c";
 				function = "i2c_c";
 			};
 		};

 		eth_rgmii_pins: eth-rgmii {
 			mux {
 				groups = "eth_mdio",
 				       "eth_mdc",
 				       "eth_clk_rx_clk",
 				       "eth_rx_dv",
 				       "eth_rxd0",
 				       "eth_rxd1",
 				       "eth_rxd2",
 				       "eth_rxd3",
 				       "eth_rgmii_tx_clk",
 				       "eth_tx_en",
 				       "eth_txd0",
 				       "eth_txd1",
 				       "eth_txd2",
 				       "eth_txd3";
 				function = "eth";
 			};
 		};

 		eth_rmii_pins: eth-rmii {
 			mux {
 				groups = "eth_mdio",
 				       "eth_mdc",
 				       "eth_clk_rx_clk",
 				       "eth_rx_dv",
 				       "eth_rxd0",
 				       "eth_rxd1",
 				       "eth_tx_en",
 				       "eth_txd0",
 				       "eth_txd1";
 				function = "eth";
 			};
 		};

 		pwm_a_x_pins: pwm_a_x {
 			mux {
 				groups = "pwm_a_x";
 				function = "pwm_a_x";
 			};
 		};

 		pwm_a_y_pins: pwm_a_y {
 			mux {
 				groups = "pwm_a_y";
 				function = "pwm_a_y";
 			};
 		};

 		pwm_b_pins: pwm_b {
 			mux {
 				groups = "pwm_b";
 				function = "pwm_b";
 			};
 		};

 		pwm_d_pins: pwm_d {
 			mux {
 				groups = "pwm_d";
 				function = "pwm_d";
 			};
 		};

 		pwm_e_pins: pwm_e {
 			mux {
 				groups = "pwm_e";
 				function = "pwm_e";
 			};
 		};

 		pwm_f_x_pins: pwm_f_x {
 			mux {
 				groups = "pwm_f_x";
 				function = "pwm_f_x";
 			};
 		};

 		pwm_f_y_pins: pwm_f_y {
 			mux {
 				groups = "pwm_f_y";
 				function = "pwm_f_y";
 			};
 		};

 		hdmi_hpd_pins: hdmi_hpd {
 			mux {
 				groups = "hdmi_hpd";
 				function = "hdmi_hpd";
 			};
 		};

 		hdmi_i2c_pins: hdmi_i2c {
 			mux {
 				groups = "hdmi_sda", "hdmi_scl";
 				function = "hdmi_i2c";
 			};
 		};

 		i2sout_ch23_y_pins: i2sout_ch23_y {
 			mux {
 				groups = "i2sout_ch23_y";
 				function = "i2s_out";
 			};
 		};

 		i2sout_ch45_y_pins: i2sout_ch45_y {
 			mux {
 				groups = "i2sout_ch45_y";
 				function = "i2s_out";
 			};
 		};

 		i2sout_ch67_y_pins: i2sout_ch67_y {
 			mux {
 				groups = "i2sout_ch67_y";
 				function = "i2s_out";
 			};
 		};

 		spdif_out_y_pins: spdif_out_y {
 			mux {
 				groups = "spdif_out_y";
 				function = "spdif_out";
 			};
 		};
 	};
 };

 &saradc {
 	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
 	clocks = <&xtal>,
 		 <&clkc CLKID_SAR_ADC>,
 		 <&clkc CLKID_SANA>,
 		 <&clkc CLKID_SAR_ADC_CLK>,
 		 <&clkc CLKID_SAR_ADC_SEL>;
 	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
 };

 &sd_emmc_a {
 	clocks = <&clkc CLKID_SD_EMMC_A>,
 		 <&clkc CLKID_SD_EMMC_A_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };

 &sd_emmc_b {
 	clocks = <&clkc CLKID_SD_EMMC_B>,
 		 <&clkc CLKID_SD_EMMC_B_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };

 &sd_emmc_c {
 	clocks = <&clkc CLKID_SD_EMMC_C>,
 		 <&clkc CLKID_SD_EMMC_C_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };

 &spicc {
 	clocks = <&clkc CLKID_SPICC>;
 	clock-names = "core";
 	resets = <&reset RESET_PERIPHS_SPICC>;
 	num-cs = <1>;
 };

 &spifc {
 	clocks = <&clkc CLKID_SPI>;
 };

 &uart_A {
 	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 	clock-names = "xtal", "pclk", "baud";
 };

 &uart_AO {
 	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
 	clock-names = "xtal", "pclk", "baud";
 };

 &uart_AO_B {
 	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
 	clock-names = "xtal", "pclk", "baud";
 };

 &uart_B {
 	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 	clock-names = "xtal", "core", "baud";
 };

 &uart_C {
 	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 	clock-names = "xtal", "core", "baud";
 };

 &vpu {
 	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
 };
	/*
	* Copyright (c) 2016 Andreas Färber
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This library is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This library is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/

	#include "meson-gx.dtsi"
	#include <dt-bindings/gpio/meson-gxbb-gpio.h>
	#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
	#include <dt-bindings/clock/gxbb-clkc.h>
	#include <dt-bindings/clock/gxbb-aoclkc.h>
	#include <dt-bindings/reset/gxbb-aoclkc.h>

	/ {
	compatible = "amlogic,meson-gxbb";

	soc {
	usb0_phy: phy@c0000000 {
	compatible = "amlogic,meson-gxbb-usb2-phy";
	#phy-cells = <0>;
	reg = <0x0 0xc0000000 0x0 0x20>;
	resets = <&reset RESET_USB_OTG>;
	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
	clock-names = "usb_general", "usb";
	status = "disabled";
	};

	usb1_phy: phy@c0000020 {
	compatible = "amlogic,meson-gxbb-usb2-phy";
	#phy-cells = <0>;
	reg = <0x0 0xc0000020 0x0 0x20>;
	resets = <&reset RESET_USB_OTG>;
	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
	clock-names = "usb_general", "usb";
	status = "disabled";
	};

	usb0: usb@c9000000 {
	compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
	reg = <0x0 0xc9000000 0x0 0x40000>;
	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
	clock-names = "otg";
	phys = <&usb0_phy>;
	phy-names = "usb2-phy";
	dr_mode = "host";
	status = "disabled";
	};

	usb1: usb@c9100000 {
	compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
	reg = <0x0 0xc9100000 0x0 0x40000>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
	clock-names = "otg";
	phys = <&usb1_phy>;
	phy-names = "usb2-phy";
	dr_mode = "host";
	status = "disabled";
	};
	};
	};

	&aobus {
	pinctrl_aobus: pinctrl@14 {
	compatible = "amlogic,meson-gxbb-aobus-pinctrl";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio_ao: bank@14 {
	reg = <0x0 0x00014 0x0 0x8>,
	<0x0 0x0002c 0x0 0x4>,
	<0x0 0x00024 0x0 0x8>;
	reg-names = "mux", "pull", "gpio";
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl_aobus 0 0 14>;
	};

	uart_ao_a_pins: uart_ao_a {
	mux {
	groups = "uart_tx_ao_a", "uart_rx_ao_a";
	function = "uart_ao";
	};
	};

	uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
	mux {
	groups = "uart_cts_ao_a",
	"uart_rts_ao_a";
	function = "uart_ao";
	};
	};

	uart_ao_b_pins: uart_ao_b {
	mux {
	groups = "uart_tx_ao_b", "uart_rx_ao_b";
	function = "uart_ao_b";
	};
	};

	uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
	mux {
	groups = "uart_cts_ao_b",
	"uart_rts_ao_b";
	function = "uart_ao_b";
	};
	};

	remote_input_ao_pins: remote_input_ao {
	mux {
	groups = "remote_input_ao";
	function = "remote_input_ao";
	};
	};

	i2c_ao_pins: i2c_ao {
	mux {
	groups = "i2c_sck_ao",
	"i2c_sda_ao";
	function = "i2c_ao";
	};
	};

	pwm_ao_a_3_pins: pwm_ao_a_3 {
	mux {
	groups = "pwm_ao_a_3";
	function = "pwm_ao_a_3";
	};
	};

	pwm_ao_a_6_pins: pwm_ao_a_6 {
	mux {
	groups = "pwm_ao_a_6";
	function = "pwm_ao_a_6";
	};
	};

	pwm_ao_a_12_pins: pwm_ao_a_12 {
	mux {
	groups = "pwm_ao_a_12";
	function = "pwm_ao_a_12";
	};
	};

	pwm_ao_b_pins: pwm_ao_b {
	mux {
	groups = "pwm_ao_b";
	function = "pwm_ao_b";
	};
	};

	i2s_am_clk_pins: i2s_am_clk {
	mux {
	groups = "i2s_am_clk";
	function = "i2s_out_ao";
	};
	};

	i2s_out_ao_clk_pins: i2s_out_ao_clk {
	mux {
	groups = "i2s_out_ao_clk";
	function = "i2s_out_ao";
	};
	};

	i2s_out_lr_clk_pins: i2s_out_lr_clk {
	mux {
	groups = "i2s_out_lr_clk";
	function = "i2s_out_ao";
	};
	};

	i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
	mux {
	groups = "i2s_out_ch01_ao";
	function = "i2s_out_ao";
	};
	};

	i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
	mux {
	groups = "i2s_out_ch23_ao";
	function = "i2s_out_ao";
	};
	};

	i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
	mux {
	groups = "i2s_out_ch45_ao";
	function = "i2s_out_ao";
	};
	};

	spdif_out_ao_6_pins: spdif_out_ao_6 {
	mux {
	groups = "spdif_out_ao_6";
	function = "spdif_out_ao";
	};
	};

	spdif_out_ao_13_pins: spdif_out_ao_13 {
	mux {
	groups = "spdif_out_ao_13";
	function = "spdif_out_ao";
	};
	};

	ao_cec_pins: ao_cec {
	mux {
	groups = "ao_cec";
	function = "cec_ao";
	};
	};

	ee_cec_pins: ee_cec {
	mux {
	groups = "ee_cec";
	function = "cec_ao";
	};
	};
	};
	};

	&apb {
	mali: gpu@c0000 {
	compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
	reg = <0x0 0xc0000 0x0 0x40000>;
	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "gp", "gpmmu", "pp", "pmu",
	"pp0", "ppmmu0", "pp1", "ppmmu1",
	"pp2", "ppmmu2";
	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
	clock-names = "bus", "core";

	/*
	* Mali clocking is provided by two identical clock paths
	* MALI_0 and MALI_1 muxed to a single clock by a glitch
	* free mux to safely change frequency while running.
	*/
	assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
	<&clkc CLKID_MALI_0>,
	<&clkc CLKID_MALI>; /* Glitch free mux */
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
	<0>, /* Do Nothing */
	<&clkc CLKID_MALI_0>;
	assigned-clock-rates = <0>, /* Do Nothing */
	<666666666>,
	<0>; /* Do Nothing */
	};
	};

	&cbus {
	spifc: spi@8c80 {
	compatible = "amlogic,meson-gxbb-spifc";
	reg = <0x0 0x08c80 0x0 0x80>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&clkc CLKID_SPI>;
	status = "disabled";
	};
	};

	&cec_AO {
	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
	clock-names = "core";
	};

	&clkc_AO {
	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
	};

	&ethmac {
	clocks = <&clkc CLKID_ETH>,
	<&clkc CLKID_FCLK_DIV2>,
	<&clkc CLKID_MPLL2>;
	clock-names = "stmmaceth", "clkin0", "clkin1";
	};

	&hdmi_tx {
	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
	resets = <&reset RESET_HDMITX_CAPB3>,
	<&reset RESET_HDMI_SYSTEM_RESET>,
	<&reset RESET_HDMI_TX>;
	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
	clocks = <&clkc CLKID_HDMI_PCLK>,
	<&clkc CLKID_CLK81>,
	<&clkc CLKID_GCLK_VENCI_INT0>;
	clock-names = "isfr", "iahb", "venci";
	};

	&hiubus {
	clkc: clock-controller@0 {
	compatible = "amlogic,gxbb-clkc";
	#clock-cells = <1>;
	reg = <0x0 0x0 0x0 0x3db>;
	};
	};

	&hwrng {
	clocks = <&clkc CLKID_RNG0>;
	clock-names = "core";
	};

	&i2c_A {
	clocks = <&clkc CLKID_I2C>;
	};

	&i2c_AO {
	clocks = <&clkc CLKID_AO_I2C>;
	};

	&i2c_B {
	clocks = <&clkc CLKID_I2C>;
	};

	&i2c_C {
	clocks = <&clkc CLKID_I2C>;
	};

	&periphs {
	pinctrl_periphs: pinctrl@4b0 {
	compatible = "amlogic,meson-gxbb-periphs-pinctrl";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	gpio: bank@4b0 {
	reg = <0x0 0x004b0 0x0 0x28>,
	<0x0 0x004e8 0x0 0x14>,
	<0x0 0x00520 0x0 0x14>,
	<0x0 0x00430 0x0 0x40>;
	reg-names = "mux", "pull", "pull-enable", "gpio";
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&pinctrl_periphs 0 14 120>;
	};

	emmc_pins: emmc {
	mux {
	groups = "emmc_nand_d07",
	"emmc_cmd",
	"emmc_clk",
	"emmc_ds";
	function = "emmc";
	};
	};

	emmc_clk_gate_pins: emmc_clk_gate {
	mux {
	groups = "BOOT_8";
	function = "gpio_periphs";
	};
	cfg-pull-down {
	pins = "BOOT_8";
	bias-pull-down;
	};
	};

	nor_pins: nor {
	mux {
	groups = "nor_d",
	"nor_q",
	"nor_c",
	"nor_cs";
	function = "nor";
	};
	};

	spi_pins: spi {
	mux {
	groups = "spi_miso",
	"spi_mosi",
	"spi_sclk";
	function = "spi";
	};
	};

	spi_ss0_pins: spi-ss0 {
	mux {
	groups = "spi_ss0";
	function = "spi";
	};
	};

	sdcard_pins: sdcard {
	mux {
	groups = "sdcard_d0",
	"sdcard_d1",
	"sdcard_d2",
	"sdcard_d3",
	"sdcard_cmd",
	"sdcard_clk";
	function = "sdcard";
	};
	};

	sdcard_clk_gate_pins: sdcard_clk_gate {
	mux {
	groups = "CARD_2";
	function = "gpio_periphs";
	};
	cfg-pull-down {
	pins = "CARD_2";
	bias-pull-down;
	};
	};

	sdio_pins: sdio {
	mux {
	groups = "sdio_d0",
	"sdio_d1",
	"sdio_d2",
	"sdio_d3",
	"sdio_cmd",
	"sdio_clk";
	function = "sdio";
	};
	};

	sdio_clk_gate_pins: sdio_clk_gate {
	mux {
	groups = "GPIOX_4";
	function = "gpio_periphs";
	};
	cfg-pull-down {
	pins = "GPIOX_4";
	bias-pull-down;
	};
	};

	sdio_irq_pins: sdio_irq {
	mux {
	groups = "sdio_irq";
	function = "sdio";
	};
	};

	uart_a_pins: uart_a {
	mux {
	groups = "uart_tx_a",
	"uart_rx_a";
	function = "uart_a";
	};
	};

	uart_a_cts_rts_pins: uart_a_cts_rts {
	mux {
	groups = "uart_cts_a",
	"uart_rts_a";
	function = "uart_a";
	};
	};

	uart_b_pins: uart_b {
	mux {
	groups = "uart_tx_b",
	"uart_rx_b";
	function = "uart_b";
	};
	};

	uart_b_cts_rts_pins: uart_b_cts_rts {
	mux {
	groups = "uart_cts_b",
	"uart_rts_b";
	function = "uart_b";
	};
	};

	uart_c_pins: uart_c {
	mux {
	groups = "uart_tx_c",
	"uart_rx_c";
	function = "uart_c";
	};
	};

	uart_c_cts_rts_pins: uart_c_cts_rts {
	mux {
	groups = "uart_cts_c",
	"uart_rts_c";
	function = "uart_c";
	};
	};

	i2c_a_pins: i2c_a {
	mux {
	groups = "i2c_sck_a",
	"i2c_sda_a";
	function = "i2c_a";
	};
	};

	i2c_b_pins: i2c_b {
	mux {
	groups = "i2c_sck_b",
	"i2c_sda_b";
	function = "i2c_b";
	};
	};

	i2c_c_pins: i2c_c {
	mux {
	groups = "i2c_sck_c",
	"i2c_sda_c";
	function = "i2c_c";
	};
	};

	eth_rgmii_pins: eth-rgmii {
	mux {
	groups = "eth_mdio",
	"eth_mdc",
	"eth_clk_rx_clk",
	"eth_rx_dv",
	"eth_rxd0",
	"eth_rxd1",
	"eth_rxd2",
	"eth_rxd3",
	"eth_rgmii_tx_clk",
	"eth_tx_en",
	"eth_txd0",
	"eth_txd1",
	"eth_txd2",
	"eth_txd3";
	function = "eth";
	};
	};

	eth_rmii_pins: eth-rmii {
	mux {
	groups = "eth_mdio",
	"eth_mdc",
	"eth_clk_rx_clk",
	"eth_rx_dv",
	"eth_rxd0",
	"eth_rxd1",
	"eth_tx_en",
	"eth_txd0",
	"eth_txd1";
	function = "eth";
	};
	};

	pwm_a_x_pins: pwm_a_x {
	mux {
	groups = "pwm_a_x";
	function = "pwm_a_x";
	};
	};

	pwm_a_y_pins: pwm_a_y {
	mux {
	groups = "pwm_a_y";
	function = "pwm_a_y";
	};
	};

	pwm_b_pins: pwm_b {
	mux {
	groups = "pwm_b";
	function = "pwm_b";
	};
	};

	pwm_d_pins: pwm_d {
	mux {
	groups = "pwm_d";
	function = "pwm_d";
	};
	};

	pwm_e_pins: pwm_e {
	mux {
	groups = "pwm_e";
	function = "pwm_e";
	};
	};

	pwm_f_x_pins: pwm_f_x {
	mux {
	groups = "pwm_f_x";
	function = "pwm_f_x";
	};
	};

	pwm_f_y_pins: pwm_f_y {
	mux {
	groups = "pwm_f_y";
	function = "pwm_f_y";
	};
	};

	hdmi_hpd_pins: hdmi_hpd {
	mux {
	groups = "hdmi_hpd";
	function = "hdmi_hpd";
	};
	};

	hdmi_i2c_pins: hdmi_i2c {
	mux {
	groups = "hdmi_sda", "hdmi_scl";
	function = "hdmi_i2c";
	};
	};

	i2sout_ch23_y_pins: i2sout_ch23_y {
	mux {
	groups = "i2sout_ch23_y";
	function = "i2s_out";
	};
	};

	i2sout_ch45_y_pins: i2sout_ch45_y {
	mux {
	groups = "i2sout_ch45_y";
	function = "i2s_out";
	};
	};

	i2sout_ch67_y_pins: i2sout_ch67_y {
	mux {
	groups = "i2sout_ch67_y";
	function = "i2s_out";
	};
	};

	spdif_out_y_pins: spdif_out_y {
	mux {
	groups = "spdif_out_y";
	function = "spdif_out";
	};
	};
	};
	};

	&saradc {
	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
	clocks = <&xtal>,
	<&clkc CLKID_SAR_ADC>,
	<&clkc CLKID_SANA>,
	<&clkc CLKID_SAR_ADC_CLK>,
	<&clkc CLKID_SAR_ADC_SEL>;
	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
	};

	&sd_emmc_a {
	clocks = <&clkc CLKID_SD_EMMC_A>,
	<&clkc CLKID_SD_EMMC_A_CLK0>,
	<&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	};

	&sd_emmc_b {
	clocks = <&clkc CLKID_SD_EMMC_B>,
	<&clkc CLKID_SD_EMMC_B_CLK0>,
	<&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	};

	&sd_emmc_c {
	clocks = <&clkc CLKID_SD_EMMC_C>,
	<&clkc CLKID_SD_EMMC_C_CLK0>,
	<&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	};

	&spicc {
	clocks = <&clkc CLKID_SPICC>;
	clock-names = "core";
	resets = <&reset RESET_PERIPHS_SPICC>;
	num-cs = <1>;
	};

	&spifc {
	clocks = <&clkc CLKID_SPI>;
	};

	&uart_A {
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	};

	&uart_AO {
	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	};

	&uart_AO_B {
	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
	};

	&uart_B {
	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
	clock-names = "xtal", "core", "baud";
	};

	&uart_C {
	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
	clock-names = "xtal", "core", "baud";
	};

	&vpu {
	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
	};