| #ifndef DSI_XML |
| #define DSI_XML |
| |
| /* Autogenerated file, DO NOT EDIT manually! |
| |
| This file was generated by the rules-ng-ng headergen tool in this git repository: |
| http://github.com/freedreno/envytools/ |
| git clone https://github.com/freedreno/envytools.git |
| |
| The rules-ng-ng source files this header was generated from are: |
| - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27) |
| - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27) |
| - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27) |
| - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27) |
| - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27) |
| - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27) |
| - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27) |
| - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27) |
| - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27) |
| - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42) |
| - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27) |
| |
| Copyright (C) 2013-2017 by the following authors: |
| - Rob Clark <robdclark@gmail.com> (robclark) |
| - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) |
| |
| Permission is hereby granted, free of charge, to any person obtaining |
| a copy of this software and associated documentation files (the |
| "Software"), to deal in the Software without restriction, including |
| without limitation the rights to use, copy, modify, merge, publish, |
| distribute, sublicense, and/or sell copies of the Software, and to |
| permit persons to whom the Software is furnished to do so, subject to |
| the following conditions: |
| |
| The above copyright notice and this permission notice (including the |
| next paragraph) shall be included in all copies or substantial |
| portions of the Software. |
| |
| THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| |
| enum dsi_traffic_mode { |
| NON_BURST_SYNCH_PULSE = 0, |
| NON_BURST_SYNCH_EVENT = 1, |
| BURST_MODE = 2, |
| }; |
| |
| enum dsi_vid_dst_format { |
| VID_DST_FORMAT_RGB565 = 0, |
| VID_DST_FORMAT_RGB666 = 1, |
| VID_DST_FORMAT_RGB666_LOOSE = 2, |
| VID_DST_FORMAT_RGB888 = 3, |
| }; |
| |
| enum dsi_rgb_swap { |
| SWAP_RGB = 0, |
| SWAP_RBG = 1, |
| SWAP_BGR = 2, |
| SWAP_BRG = 3, |
| SWAP_GRB = 4, |
| SWAP_GBR = 5, |
| }; |
| |
| enum dsi_cmd_trigger { |
| TRIGGER_NONE = 0, |
| TRIGGER_SEOF = 1, |
| TRIGGER_TE = 2, |
| TRIGGER_SW = 4, |
| TRIGGER_SW_SEOF = 5, |
| TRIGGER_SW_TE = 6, |
| }; |
| |
| enum dsi_cmd_dst_format { |
| CMD_DST_FORMAT_RGB111 = 0, |
| CMD_DST_FORMAT_RGB332 = 3, |
| CMD_DST_FORMAT_RGB444 = 4, |
| CMD_DST_FORMAT_RGB565 = 6, |
| CMD_DST_FORMAT_RGB666 = 7, |
| CMD_DST_FORMAT_RGB888 = 8, |
| }; |
| |
| enum dsi_lane_swap { |
| LANE_SWAP_0123 = 0, |
| LANE_SWAP_3012 = 1, |
| LANE_SWAP_2301 = 2, |
| LANE_SWAP_1230 = 3, |
| LANE_SWAP_0321 = 4, |
| LANE_SWAP_1032 = 5, |
| LANE_SWAP_2103 = 6, |
| LANE_SWAP_3210 = 7, |
| }; |
| |
| #define DSI_IRQ_CMD_DMA_DONE 0x00000001 |
| #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 |
| #define DSI_IRQ_CMD_MDP_DONE 0x00000100 |
| #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 |
| #define DSI_IRQ_VIDEO_DONE 0x00010000 |
| #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 |
| #define DSI_IRQ_BTA_DONE 0x00100000 |
| #define DSI_IRQ_MASK_BTA_DONE 0x00200000 |
| #define DSI_IRQ_ERROR 0x01000000 |
| #define DSI_IRQ_MASK_ERROR 0x02000000 |
| #define REG_DSI_6G_HW_VERSION 0x00000000 |
| #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000 |
| #define DSI_6G_HW_VERSION_MAJOR__SHIFT 28 |
| static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) |
| { |
| return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; |
| } |
| #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000 |
| #define DSI_6G_HW_VERSION_MINOR__SHIFT 16 |
| static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) |
| { |
| return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; |
| } |
| #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff |
| #define DSI_6G_HW_VERSION_STEP__SHIFT 0 |
| static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) |
| { |
| return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; |
| } |
| |
| #define REG_DSI_CTRL 0x00000000 |
| #define DSI_CTRL_ENABLE 0x00000001 |
| #define DSI_CTRL_VID_MODE_EN 0x00000002 |
| #define DSI_CTRL_CMD_MODE_EN 0x00000004 |
| #define DSI_CTRL_LANE0 0x00000010 |
| #define DSI_CTRL_LANE1 0x00000020 |
| #define DSI_CTRL_LANE2 0x00000040 |
| #define DSI_CTRL_LANE3 0x00000080 |
| #define DSI_CTRL_CLK_EN 0x00000100 |
| #define DSI_CTRL_ECC_CHECK 0x00100000 |
| #define DSI_CTRL_CRC_CHECK 0x01000000 |
| |
| #define REG_DSI_STATUS0 0x00000004 |
| #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001 |
| #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 |
| #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004 |
| #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 |
| #define DSI_STATUS0_DSI_BUSY 0x00000010 |
| #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 |
| |
| #define REG_DSI_FIFO_STATUS 0x00000008 |
| #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 |
| |
| #define REG_DSI_VID_CFG0 0x0000000c |
| #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 |
| #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0 |
| static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) |
| { |
| return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; |
| } |
| #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 |
| #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 |
| static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) |
| { |
| return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; |
| } |
| #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300 |
| #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8 |
| static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) |
| { |
| return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; |
| } |
| #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000 |
| #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000 |
| #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 |
| #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 |
| #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 |
| #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 |
| |
| #define REG_DSI_VID_CFG1 0x0000001c |
| #define DSI_VID_CFG1_R_SEL 0x00000001 |
| #define DSI_VID_CFG1_G_SEL 0x00000010 |
| #define DSI_VID_CFG1_B_SEL 0x00000100 |
| #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000 |
| #define DSI_VID_CFG1_RGB_SWAP__SHIFT 12 |
| static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) |
| { |
| return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; |
| } |
| |
| #define REG_DSI_ACTIVE_H 0x00000020 |
| #define DSI_ACTIVE_H_START__MASK 0x00000fff |
| #define DSI_ACTIVE_H_START__SHIFT 0 |
| static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; |
| } |
| #define DSI_ACTIVE_H_END__MASK 0x0fff0000 |
| #define DSI_ACTIVE_H_END__SHIFT 16 |
| static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; |
| } |
| |
| #define REG_DSI_ACTIVE_V 0x00000024 |
| #define DSI_ACTIVE_V_START__MASK 0x00000fff |
| #define DSI_ACTIVE_V_START__SHIFT 0 |
| static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; |
| } |
| #define DSI_ACTIVE_V_END__MASK 0x0fff0000 |
| #define DSI_ACTIVE_V_END__SHIFT 16 |
| static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; |
| } |
| |
| #define REG_DSI_TOTAL 0x00000028 |
| #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff |
| #define DSI_TOTAL_H_TOTAL__SHIFT 0 |
| static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) |
| { |
| return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; |
| } |
| #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000 |
| #define DSI_TOTAL_V_TOTAL__SHIFT 16 |
| static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) |
| { |
| return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; |
| } |
| |
| #define REG_DSI_ACTIVE_HSYNC 0x0000002c |
| #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff |
| #define DSI_ACTIVE_HSYNC_START__SHIFT 0 |
| static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; |
| } |
| #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000 |
| #define DSI_ACTIVE_HSYNC_END__SHIFT 16 |
| static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; |
| } |
| |
| #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030 |
| #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff |
| #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0 |
| static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; |
| } |
| #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000 |
| #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16 |
| static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; |
| } |
| |
| #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034 |
| #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff |
| #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0 |
| static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; |
| } |
| #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000 |
| #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16 |
| static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) |
| { |
| return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; |
| } |
| |
| #define REG_DSI_CMD_DMA_CTRL 0x00000038 |
| #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000 |
| #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 |
| #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 |
| |
| #define REG_DSI_CMD_CFG0 0x0000003c |
| #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f |
| #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0 |
| static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) |
| { |
| return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; |
| } |
| #define DSI_CMD_CFG0_R_SEL 0x00000010 |
| #define DSI_CMD_CFG0_G_SEL 0x00000100 |
| #define DSI_CMD_CFG0_B_SEL 0x00001000 |
| #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000 |
| #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20 |
| static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) |
| { |
| return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; |
| } |
| #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000 |
| #define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16 |
| static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) |
| { |
| return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; |
| } |
| |
| #define REG_DSI_CMD_CFG1 0x00000040 |
| #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff |
| #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0 |
| static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) |
| { |
| return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; |
| } |
| #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00 |
| #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8 |
| static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) |
| { |
| return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; |
| } |
| #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000 |
| |
| #define REG_DSI_DMA_BASE 0x00000044 |
| |
| #define REG_DSI_DMA_LEN 0x00000048 |
| |
| #define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054 |
| #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f |
| #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0 |
| static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) |
| { |
| return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK; |
| } |
| #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 |
| #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8 |
| static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) |
| { |
| return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK; |
| } |
| #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000 |
| #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16 |
| static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) |
| { |
| return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK; |
| } |
| |
| #define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058 |
| #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff |
| #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0 |
| static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) |
| { |
| return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; |
| } |
| #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000 |
| #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16 |
| static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) |
| { |
| return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; |
| } |
| |
| #define REG_DSI_ACK_ERR_STATUS 0x00000064 |
| |
| static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } |
| |
| static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } |
| |
| #define REG_DSI_TRIG_CTRL 0x00000080 |
| #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007 |
| #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 |
| static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) |
| { |
| return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; |
| } |
| #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070 |
| #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 |
| static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) |
| { |
| return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; |
| } |
| #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300 |
| #define DSI_TRIG_CTRL_STREAM__SHIFT 8 |
| static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) |
| { |
| return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; |
| } |
| #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000 |
| #define DSI_TRIG_CTRL_TE 0x80000000 |
| |
| #define REG_DSI_TRIG_DMA 0x0000008c |
| |
| #define REG_DSI_DLN0_PHY_ERR 0x000000b0 |
| #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001 |
| #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010 |
| #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100 |
| #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000 |
| #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000 |
| |
| #define REG_DSI_TIMEOUT_STATUS 0x000000bc |
| |
| #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 |
| #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f |
| #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0 |
| static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) |
| { |
| return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; |
| } |
| #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00 |
| #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8 |
| static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) |
| { |
| return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; |
| } |
| |
| #define REG_DSI_EOT_PACKET_CTRL 0x000000c8 |
| #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 |
| #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 |
| |
| #define REG_DSI_LANE_CTRL 0x000000a8 |
| #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 |
| |
| #define REG_DSI_LANE_SWAP_CTRL 0x000000ac |
| #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 |
| #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 |
| static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) |
| { |
| return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; |
| } |
| |
| #define REG_DSI_ERR_INT_MASK0 0x00000108 |
| |
| #define REG_DSI_INTR_CTRL 0x0000010c |
| |
| #define REG_DSI_RESET 0x00000114 |
| |
| #define REG_DSI_CLK_CTRL 0x00000118 |
| #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001 |
| #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002 |
| #define DSI_CLK_CTRL_PCLK_ON 0x00000004 |
| #define DSI_CLK_CTRL_DSICLK_ON 0x00000008 |
| #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010 |
| #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020 |
| #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 |
| |
| #define REG_DSI_CLK_STATUS 0x0000011c |
| #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 |
| |
| #define REG_DSI_PHY_RESET 0x00000128 |
| #define DSI_PHY_RESET_RESET 0x00000001 |
| |
| #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c |
| #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001 |
| |
| #define REG_DSI_RDBK_DATA_CTRL 0x000001d0 |
| #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 |
| #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 |
| static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) |
| { |
| return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; |
| } |
| #define DSI_RDBK_DATA_CTRL_CLR 0x00000001 |
| |
| #define REG_DSI_VERSION 0x000001f0 |
| #define DSI_VERSION_MAJOR__MASK 0xff000000 |
| #define DSI_VERSION_MAJOR__SHIFT 24 |
| static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) |
| { |
| return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; |
| } |
| |
| #define REG_DSI_PHY_PLL_CTRL_0 0x00000200 |
| #define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001 |
| |
| #define REG_DSI_PHY_PLL_CTRL_1 0x00000204 |
| |
| #define REG_DSI_PHY_PLL_CTRL_2 0x00000208 |
| |
| #define REG_DSI_PHY_PLL_CTRL_3 0x0000020c |
| |
| #define REG_DSI_PHY_PLL_CTRL_4 0x00000210 |
| |
| #define REG_DSI_PHY_PLL_CTRL_5 0x00000214 |
| |
| #define REG_DSI_PHY_PLL_CTRL_6 0x00000218 |
| |
| #define REG_DSI_PHY_PLL_CTRL_7 0x0000021c |
| |
| #define REG_DSI_PHY_PLL_CTRL_8 0x00000220 |
| |
| #define REG_DSI_PHY_PLL_CTRL_9 0x00000224 |
| |
| #define REG_DSI_PHY_PLL_CTRL_10 0x00000228 |
| |
| #define REG_DSI_PHY_PLL_CTRL_11 0x0000022c |
| |
| #define REG_DSI_PHY_PLL_CTRL_12 0x00000230 |
| |
| #define REG_DSI_PHY_PLL_CTRL_13 0x00000234 |
| |
| #define REG_DSI_PHY_PLL_CTRL_14 0x00000238 |
| |
| #define REG_DSI_PHY_PLL_CTRL_15 0x0000023c |
| |
| #define REG_DSI_PHY_PLL_CTRL_16 0x00000240 |
| |
| #define REG_DSI_PHY_PLL_CTRL_17 0x00000244 |
| |
| #define REG_DSI_PHY_PLL_CTRL_18 0x00000248 |
| |
| #define REG_DSI_PHY_PLL_CTRL_19 0x0000024c |
| |
| #define REG_DSI_PHY_PLL_CTRL_20 0x00000250 |
| |
| #define REG_DSI_PHY_PLL_STATUS 0x00000280 |
| #define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001 |
| |
| #define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258 |
| |
| #define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260 |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264 |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268 |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270 |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274 |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278 |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280 |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284 |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288 |
| |
| #define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c |
| |
| #define REG_DSI_8x60_PHY_CTRL_0 0x00000290 |
| |
| #define REG_DSI_8x60_PHY_CTRL_1 0x00000294 |
| |
| #define REG_DSI_8x60_PHY_CTRL_2 0x00000298 |
| |
| #define REG_DSI_8x60_PHY_CTRL_3 0x0000029c |
| |
| #define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0 |
| |
| #define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4 |
| |
| #define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8 |
| |
| #define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac |
| |
| #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc |
| |
| #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0 |
| |
| #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4 |
| |
| #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8 |
| |
| #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc |
| |
| #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0 |
| |
| #define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4 |
| |
| #define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc |
| #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000 |
| |
| static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } |
| |
| #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100 |
| |
| #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104 |
| |
| #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108 |
| |
| #define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c |
| |
| #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114 |
| |
| #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118 |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK; |
| } |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff |
| #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 |
| static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) |
| { |
| return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; |
| } |
| |
| #define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170 |
| |
| #define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174 |
| |
| #define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178 |
| |
| #define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c |
| |
| #define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180 |
| |
| #define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184 |
| |
| #define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188 |
| |
| #define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c |
| |
| #define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190 |
| |
| #define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194 |
| |
| #define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198 |
| |
| #define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c |
| |
| #define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048 |
| |
| #define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050 |
| #define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000 |
| #define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050 |
| |
| #define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080 |
| #define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001 |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } |
| |
| #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 |
| |
| #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 |
| |
| #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 |
| |
| #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c |
| |
| #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 |
| |
| #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 |
| |
| #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 |
| |
| #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c |
| |
| #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 |
| #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff |
| #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 |
| #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff |
| #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 |
| #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff |
| #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c |
| #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 |
| #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff |
| #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 |
| #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff |
| #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 |
| #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff |
| #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c |
| #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff |
| #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 |
| #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff |
| #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 |
| #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 |
| #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; |
| } |
| #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 |
| #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 |
| #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 |
| #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c |
| #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff |
| #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_CTRL_0 0x00000170 |
| |
| #define REG_DSI_28nm_PHY_CTRL_1 0x00000174 |
| |
| #define REG_DSI_28nm_PHY_CTRL_2 0x00000178 |
| |
| #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c |
| |
| #define REG_DSI_28nm_PHY_CTRL_4 0x00000180 |
| |
| #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 |
| |
| #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 |
| |
| #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 |
| |
| #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 |
| |
| #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc |
| |
| #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 |
| |
| #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 |
| |
| #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 |
| |
| #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 |
| #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 |
| |
| #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc |
| |
| #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 |
| |
| #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 |
| |
| #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 |
| |
| #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c |
| |
| #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 |
| |
| #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 |
| |
| #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 |
| |
| #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 |
| #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 |
| |
| #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 |
| |
| #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 |
| |
| #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c |
| |
| #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 |
| #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 |
| |
| #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 |
| |
| #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 |
| |
| #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c |
| |
| #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 |
| #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 |
| #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 |
| #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 |
| #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 |
| |
| #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 |
| |
| #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 |
| |
| #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c |
| |
| #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 |
| |
| #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 |
| |
| #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 |
| #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f |
| #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; |
| } |
| #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 |
| |
| #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c |
| #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f |
| #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; |
| } |
| #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 |
| #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 |
| static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 |
| #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff |
| #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 |
| #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff |
| #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 |
| static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) |
| { |
| return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; |
| } |
| |
| #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 |
| |
| #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c |
| |
| #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 |
| |
| #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 |
| |
| #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 |
| |
| #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c |
| |
| #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 |
| |
| #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 |
| |
| #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 |
| #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 |
| |
| #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 |
| |
| #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c |
| |
| #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 |
| |
| #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 |
| |
| #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 |
| |
| #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac |
| |
| #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 |
| |
| #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 |
| |
| #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 |
| |
| #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc |
| |
| #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 |
| #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 |
| |
| #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 |
| |
| #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 |
| |
| #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc |
| |
| #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 |
| |
| #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } |
| |
| static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } |
| |
| #define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100 |
| |
| #define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104 |
| |
| #define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108 |
| |
| #define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c |
| |
| #define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110 |
| |
| #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114 |
| |
| #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118 |
| |
| #define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c |
| |
| #define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120 |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140 |
| #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff |
| #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144 |
| #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff |
| #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148 |
| #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff |
| #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c |
| #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150 |
| #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff |
| #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154 |
| #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff |
| #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158 |
| #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff |
| #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c |
| #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff |
| #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160 |
| #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff |
| #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164 |
| #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 |
| #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; |
| } |
| #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 |
| #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168 |
| #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 |
| #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c |
| #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff |
| #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 |
| static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) |
| { |
| return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; |
| } |
| |
| #define REG_DSI_20nm_PHY_CTRL_0 0x00000170 |
| |
| #define REG_DSI_20nm_PHY_CTRL_1 0x00000174 |
| |
| #define REG_DSI_20nm_PHY_CTRL_2 0x00000178 |
| |
| #define REG_DSI_20nm_PHY_CTRL_3 0x0000017c |
| |
| #define REG_DSI_20nm_PHY_CTRL_4 0x00000180 |
| |
| #define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184 |
| |
| #define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188 |
| |
| #define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4 |
| |
| #define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8 |
| |
| #define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc |
| |
| #define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0 |
| |
| #define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4 |
| |
| #define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8 |
| |
| #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4 |
| #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 |
| |
| #define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc |
| |
| #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000 |
| |
| #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004 |
| |
| #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008 |
| |
| #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c |
| |
| #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010 |
| |
| #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014 |
| |
| #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 |
| |
| #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000 |
| |
| #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004 |
| |
| #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008 |
| |
| #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c |
| |
| #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010 |
| #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0 |
| #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4 |
| static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK; |
| } |
| #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0 |
| #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4 |
| static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK; |
| } |
| |
| #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014 |
| #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001 |
| |
| #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018 |
| #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004 |
| |
| #define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c |
| |
| #define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020 |
| |
| #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024 |
| |
| #define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028 |
| |
| #define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c |
| |
| #define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030 |
| |
| #define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034 |
| |
| #define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038 |
| |
| #define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c |
| |
| #define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040 |
| |
| #define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044 |
| |
| #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048 |
| #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001 |
| |
| #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c |
| #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f |
| #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0 |
| static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0 |
| #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6 |
| static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001 |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0 |
| static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0 |
| static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 |
| static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 |
| static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0 |
| static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007 |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0 |
| static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK; |
| } |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4 |
| static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007 |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0 |
| static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; } |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff |
| #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 |
| static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) |
| { |
| return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK; |
| } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; } |
| |
| static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; } |
| |
| #define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000 |
| |
| #define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004 |
| |
| #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010 |
| |
| #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c |
| |
| #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028 |
| |
| #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c |
| |
| #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030 |
| |
| #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034 |
| |
| #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038 |
| |
| #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c |
| |
| #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040 |
| |
| #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044 |
| |
| #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048 |
| |
| #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c |
| |
| #define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c |
| |
| #define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058 |
| |
| #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c |
| |
| #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070 |
| |
| #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074 |
| |
| #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c |
| |
| #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c |
| |
| #define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090 |
| |
| #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094 |
| |
| #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098 |
| |
| #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c |
| |
| #define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0 |
| |
| #define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4 |
| |
| #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8 |
| |
| #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac |
| |
| #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4 |
| |
| #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8 |
| |
| #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc |
| |
| #define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4 |
| |
| #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc |
| |
| #define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8 |
| |
| #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc |
| |
| #define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104 |
| |
| #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108 |
| |
| |
| #endif /* DSI_XML */ |
