drivers/gpu/drm/i915/i915_reg.h

/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef _I915_REG_H_
#define _I915_REG_H_

/**
 * DOC: The i915 register macro definition style guide
 *
 * Follow the style described here for new macros, and while changing existing
 * macros. Do **not** mass change existing definitions just to update the style.
 *
 * Layout
 * ''''''
 *
 * Keep helper macros near the top. For example, _PIPE() and friends.
 *
 * Prefix macros that generally should not be used outside of this file with
 * underscore '_'. For example, _PIPE() and friends, single instances of
 * registers that are defined solely for the use by function-like macros.
 *
 * Avoid using the underscore prefixed macros outside of this file. There are
 * exceptions, but keep them to a minimum.
 *
 * There are two basic types of register definitions: Single registers and
 * register groups. Register groups are registers which have two or more
 * instances, for example one per pipe, port, transcoder, etc. Register groups
 * should be defined using function-like macros.
 *
 * For single registers, define the register offset first, followed by register
 * contents.
 *
 * For register groups, define the register instance offsets first, prefixed
 * with underscore, followed by a function-like macro choosing the right
 * instance based on the parameter, followed by register contents.
 *
 * Define the register contents (i.e. bit and bit field macros) from most
 * significant to least significant bit. Indent the register content macros
 * using two extra spaces between ``#define`` and the macro name.
 *
 * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
 * contents so that they are already shifted in place, and can be directly
 * OR'd. For convenience, function-like macros may be used to define bit fields,
 * but do note that the macros may be needed to read as well as write the
 * register contents.
 *
 * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
 * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
 * to the name.
 *
 * Group the register and its contents together without blank lines, separate
 * from other registers and their contents with one blank line.
 *
 * Indent macro values from macro names using TABs. Align values vertically. Use
 * braces in macro values as needed to avoid unintended precedence after macro
 * substitution. Use spaces in macro values according to kernel coding
 * style. Use lower case in hexadecimal values.
 *
 * Naming
 * ''''''
 *
 * Try to name registers according to the specs. If the register name changes in
 * the specs from platform to another, stick to the original name.
 *
 * Try to re-use existing register macro definitions. Only add new macros for
 * new register offsets, or when the register contents have changed enough to
 * warrant a full redefinition.
 *
 * When a register macro changes for a new platform, prefix the new macro using
 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
 * prefix signifies the start platform/generation using the register.
 *
 * When a bit (field) macro changes or gets added for a new platform, while
 * retaining the existing register macro, add a platform acronym or generation
 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
 *
 * Examples
 * ''''''''
 *
 * (Note that the values in the example are indented using spaces instead of
 * TABs to avoid misalignment in generated documentation. Use TABs in the
 * definitions.)::
 *
 *  #define _FOO_A                      0xf000
 *  #define _FOO_B                      0xf001
 *  #define FOO(pipe)                   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
 *  #define   FOO_ENABLE                (1 << 31)
 *  #define   FOO_MODE_MASK             (0xf << 16)
 *  #define   FOO_MODE_SHIFT            16
 *  #define   FOO_MODE_BAR              (0 << 16)
 *  #define   FOO_MODE_BAZ              (1 << 16)
 *  #define   FOO_MODE_QUX_SNB          (2 << 16)
 *
 *  #define BAR                         _MMIO(0xb000)
 *  #define GEN8_BAR                    _MMIO(0xb888)
 */

typedef struct {
	uint32_t reg;
} i915_reg_t;

#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })

#define INVALID_MMIO_REG _MMIO(0)

static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
{
	return reg.reg;
}

static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
{
	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
}

static inline bool i915_mmio_reg_valid(i915_reg_t reg)
{
	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
}

#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])

#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
#define _PLANE(plane, a, b) _PIPE(plane, a, b)
#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
#define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)			\
	_MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))

#define _MASKED_FIELD(mask, value) ({					   \
	if (__builtin_constant_p(mask))					   \
		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
	if (__builtin_constant_p(value))				   \
		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
				 "Incorrect value for mask");		   \
	(mask) << 16 | (value); })
#define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
#define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))

/* Engine ID */

#define RCS_HW		0
#define VCS_HW		1
#define BCS_HW		2
#define VECS_HW		3
#define VCS2_HW		4

/* Engine class */

#define RENDER_CLASS		0
#define VIDEO_DECODE_CLASS	1
#define VIDEO_ENHANCEMENT_CLASS	2
#define COPY_ENGINE_CLASS	3
#define OTHER_CLASS		4

/* PCI config space */

#define MCHBAR_I915 0x44
#define MCHBAR_I965 0x48
#define MCHBAR_SIZE (4 * 4096)

#define DEVEN 0x54
#define   DEVEN_MCHBAR_EN (1 << 28)

/* BSM in include/drm/i915_drm.h */

#define HPLLCC	0xc0 /* 85x only */
#define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
#define   GC_CLOCK_133_200		(0 << 0)
#define   GC_CLOCK_100_200		(1 << 0)
#define   GC_CLOCK_100_133		(2 << 0)
#define   GC_CLOCK_133_266		(3 << 0)
#define   GC_CLOCK_133_200_2		(4 << 0)
#define   GC_CLOCK_133_266_2		(5 << 0)
#define   GC_CLOCK_166_266		(6 << 0)
#define   GC_CLOCK_166_250		(7 << 0)

#define I915_GDRST 0xc0 /* PCI config register */
#define   GRDOM_FULL		(0 << 2)
#define   GRDOM_RENDER		(1 << 2)
#define   GRDOM_MEDIA		(3 << 2)
#define   GRDOM_MASK		(3 << 2)
#define   GRDOM_RESET_STATUS	(1 << 1)
#define   GRDOM_RESET_ENABLE	(1 << 0)

/* BSpec only has register offset, PCI device and bit found empirically */
#define I830_CLOCK_GATE	0xc8 /* device 0 */
#define   I830_L2_CACHE_CLOCK_GATE_DISABLE	(1 << 2)

#define GCDGMBUS 0xcc

#define GCFGC2	0xda
#define GCFGC	0xf0 /* 915+ only */
#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
#define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
#define   GC_DISPLAY_CLOCK_333_320_MHZ	(4 << 4)
#define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
#define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
#define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
#define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
#define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
#define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
#define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
#define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
#define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
#define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
#define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
#define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
#define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
#define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
#define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
#define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
#define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
#define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
#define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
#define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
#define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)

#define ASLE	0xe4
#define ASLS	0xfc

#define SWSCI	0xe8
#define   SWSCI_SCISEL	(1 << 15)
#define   SWSCI_GSSCIE	(1 << 0)

#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */


#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
#define  ILK_GRDOM_FULL		(0<<1)
#define  ILK_GRDOM_RENDER	(1<<1)
#define  ILK_GRDOM_MEDIA	(3<<1)
#define  ILK_GRDOM_MASK		(3<<1)
#define  ILK_GRDOM_RESET_ENABLE (1<<0)

#define GEN6_MBCUNIT_SNPCR	_MMIO(0x900c) /* for LLC config */
#define   GEN6_MBC_SNPCR_SHIFT	21
#define   GEN6_MBC_SNPCR_MASK	(3<<21)
#define   GEN6_MBC_SNPCR_MAX	(0<<21)
#define   GEN6_MBC_SNPCR_MED	(1<<21)
#define   GEN6_MBC_SNPCR_LOW	(2<<21)
#define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */

#define VLV_G3DCTL		_MMIO(0x9024)
#define VLV_GSCKGCTL		_MMIO(0x9028)

#define GEN6_MBCTL		_MMIO(0x0907c)
#define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
#define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
#define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
#define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
#define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)

#define GEN6_GDRST	_MMIO(0x941c)
#define  GEN6_GRDOM_FULL		(1 << 0)
#define  GEN6_GRDOM_RENDER		(1 << 1)
#define  GEN6_GRDOM_MEDIA		(1 << 2)
#define  GEN6_GRDOM_BLT			(1 << 3)
#define  GEN6_GRDOM_VECS		(1 << 4)
#define  GEN9_GRDOM_GUC			(1 << 5)
#define  GEN8_GRDOM_MEDIA2		(1 << 7)

#define RING_PP_DIR_BASE(engine)	_MMIO((engine)->mmio_base+0x228)
#define RING_PP_DIR_BASE_READ(engine)	_MMIO((engine)->mmio_base+0x518)
#define RING_PP_DIR_DCLV(engine)	_MMIO((engine)->mmio_base+0x220)
#define   PP_DIR_DCLV_2G		0xffffffff

#define GEN8_RING_PDP_UDW(engine, n)	_MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4)
#define GEN8_RING_PDP_LDW(engine, n)	_MMIO((engine)->mmio_base+0x270 + (n) * 8)

#define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)
#define   GEN8_RPCS_ENABLE		(1 << 31)
#define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
#define   GEN8_RPCS_S_CNT_SHIFT		15
#define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
#define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)
#define   GEN8_RPCS_SS_CNT_SHIFT	8
#define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
#define   GEN8_RPCS_EU_MAX_SHIFT	4
#define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
#define   GEN8_RPCS_EU_MIN_SHIFT	0
#define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)

#define WAIT_FOR_RC6_EXIT		_MMIO(0x20CC)
/* HSW only */
#define   HSW_SELECTIVE_READ_ADDRESSING_SHIFT		2
#define   HSW_SELECTIVE_READ_ADDRESSING_MASK		(0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
#define   HSW_SELECTIVE_WRITE_ADDRESS_SHIFT		4
#define   HSW_SELECTIVE_WRITE_ADDRESS_MASK		(0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
/* HSW+ */
#define   HSW_WAIT_FOR_RC6_EXIT_ENABLE			(1 << 0)
#define   HSW_RCS_CONTEXT_ENABLE			(1 << 7)
#define   HSW_RCS_INHIBIT				(1 << 8)
/* Gen8 */
#define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
#define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
#define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
#define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
#define   GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE	(1 << 6)
#define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT	9
#define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK	(0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
#define   GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT	11
#define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK		(0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
#define   GEN8_SELECTIVE_READ_ADDRESSING_ENABLE         (1 << 13)

#define GAM_ECOCHK			_MMIO(0x4090)
#define   BDW_DISABLE_HDC_INVALIDATION	(1<<25)
#define   ECOCHK_SNB_BIT		(1<<10)
#define   ECOCHK_DIS_TLB		(1<<8)
#define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
#define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
#define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
#define   ECOCHK_PPGTT_GFDT_IVB		(0x1<<4)
#define   ECOCHK_PPGTT_LLC_IVB		(0x1<<3)
#define   ECOCHK_PPGTT_UC_HSW		(0x1<<3)
#define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
#define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)

#define GEN8_CONFIG0			_MMIO(0xD00)
#define  GEN9_DEFAULT_FIXES		(1 << 3 | 1 << 2 | 1 << 1)

#define GAC_ECO_BITS			_MMIO(0x14090)
#define   ECOBITS_SNB_BIT		(1<<13)
#define   ECOBITS_PPGTT_CACHE64B	(3<<8)
#define   ECOBITS_PPGTT_CACHE4B		(0<<8)

#define GAB_CTL				_MMIO(0x24000)
#define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)

#define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
#define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
#define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
#define GEN6_STOLEN_RESERVED_SIZE_MASK	(3 << 4)
#define GEN6_STOLEN_RESERVED_1M		(0 << 4)
#define GEN6_STOLEN_RESERVED_512K	(1 << 4)
#define GEN6_STOLEN_RESERVED_256K	(2 << 4)
#define GEN6_STOLEN_RESERVED_128K	(3 << 4)
#define GEN7_STOLEN_RESERVED_SIZE_MASK	(1 << 5)
#define GEN7_STOLEN_RESERVED_1M		(0 << 5)
#define GEN7_STOLEN_RESERVED_256K	(1 << 5)
#define GEN8_STOLEN_RESERVED_SIZE_MASK	(3 << 7)
#define GEN8_STOLEN_RESERVED_1M		(0 << 7)
#define GEN8_STOLEN_RESERVED_2M		(1 << 7)
#define GEN8_STOLEN_RESERVED_4M		(2 << 7)
#define GEN8_STOLEN_RESERVED_8M		(3 << 7)

/* VGA stuff */

#define VGA_ST01_MDA 0x3ba
#define VGA_ST01_CGA 0x3da

#define _VGA_MSR_WRITE _MMIO(0x3c2)
#define VGA_MSR_WRITE 0x3c2
#define VGA_MSR_READ 0x3cc
#define   VGA_MSR_MEM_EN (1<<1)
#define   VGA_MSR_CGA_MODE (1<<0)

#define VGA_SR_INDEX 0x3c4
#define SR01			1
#define VGA_SR_DATA 0x3c5

#define VGA_AR_INDEX 0x3c0
#define   VGA_AR_VID_EN (1<<5)
#define VGA_AR_DATA_WRITE 0x3c0
#define VGA_AR_DATA_READ 0x3c1

#define VGA_GR_INDEX 0x3ce
#define VGA_GR_DATA 0x3cf
/* GR05 */
#define   VGA_GR_MEM_READ_MODE_SHIFT 3
#define     VGA_GR_MEM_READ_MODE_PLANE 1
/* GR06 */
#define   VGA_GR_MEM_MODE_MASK 0xc
#define   VGA_GR_MEM_MODE_SHIFT 2
#define   VGA_GR_MEM_A0000_AFFFF 0
#define   VGA_GR_MEM_A0000_BFFFF 1
#define   VGA_GR_MEM_B0000_B7FFF 2
#define   VGA_GR_MEM_B0000_BFFFF 3

#define VGA_DACMASK 0x3c6
#define VGA_DACRX 0x3c7
#define VGA_DACWX 0x3c8
#define VGA_DACDATA 0x3c9

#define VGA_CR_INDEX_MDA 0x3b4
#define VGA_CR_DATA_MDA 0x3b5
#define VGA_CR_INDEX_CGA 0x3d4
#define VGA_CR_DATA_CGA 0x3d5

/*
 * Instruction field definitions used by the command parser
 */
#define INSTR_CLIENT_SHIFT      29
#define   INSTR_MI_CLIENT       0x0
#define   INSTR_BC_CLIENT       0x2
#define   INSTR_RC_CLIENT       0x3
#define INSTR_SUBCLIENT_SHIFT   27
#define INSTR_SUBCLIENT_MASK    0x18000000
#define   INSTR_MEDIA_SUBCLIENT 0x2
#define INSTR_26_TO_24_MASK	0x7000000
#define   INSTR_26_TO_24_SHIFT	24

/*
 * Memory interface instructions used by the kernel
 */
#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
#define  MI_GLOBAL_GTT    (1<<22)

#define MI_NOOP			MI_INSTR(0, 0)
#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
#define MI_FLUSH		MI_INSTR(0x04, 0)
#define   MI_READ_FLUSH		(1 << 0)
#define   MI_EXE_FLUSH		(1 << 1)
#define   MI_NO_WRITE_FLUSH	(1 << 2)
#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
#define   MI_ARB_ENABLE			(1<<0)
#define   MI_ARB_DISABLE		(0<<0)
#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
#define   MI_SUSPEND_FLUSH_EN	(1<<0)
#define MI_SET_APPID		MI_INSTR(0x0e, 0)
#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
#define   MI_OVERLAY_CONTINUE	(0x0<<21)
#define   MI_OVERLAY_ON		(0x1<<21)
#define   MI_OVERLAY_OFF	(0x2<<21)
#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
/* IVB has funny definitions for which plane to flip. */
#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
/* SKL ones */
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_A	(0 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_B	(1 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_C	(2 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_A	(4 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_B	(5 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_C	(6 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_A	(7 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_B	(8 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_C	(9 << 8)
#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
#define   MI_SEMAPHORE_UPDATE	    (1<<21)
#define   MI_SEMAPHORE_COMPARE	    (1<<20)
#define   MI_SEMAPHORE_REGISTER	    (1<<18)
#define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */
#define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */
#define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */
#define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */
#define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */
#define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */
#define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */
#define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */
#define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */
#define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */
#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */
#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */
#define   MI_SEMAPHORE_SYNC_INVALID (3<<16)
#define   MI_SEMAPHORE_SYNC_MASK    (3<<16)
#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
#define   MI_MM_SPACE_GTT		(1<<8)
#define   MI_MM_SPACE_PHYSICAL		(0<<8)
#define   MI_SAVE_EXT_STATE_EN		(1<<3)
#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
#define   MI_FORCE_RESTORE		(1<<1)
#define   MI_RESTORE_INHIBIT		(1<<0)
#define   HSW_MI_RS_SAVE_STATE_EN       (1<<3)
#define   HSW_MI_RS_RESTORE_STATE_EN    (1<<2)
#define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
#define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
#define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
#define   MI_SEMAPHORE_POLL		(1<<15)
#define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)
#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
#define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)
#define   MI_MEM_VIRTUAL	(1 << 22) /* 945,g33,965 */
#define   MI_USE_GGTT		(1 << 22) /* g4x+ */
#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
#define   MI_STORE_DWORD_INDEX_SHIFT 2
/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
 *   simply ignores the register load under certain conditions.
 * - One can actually load arbitrary many arbitrary registers: Simply issue x
 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
 */
#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
#define   MI_LRI_FORCE_POSTED		(1<<12)
#define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
#define   MI_INVALIDATE_TLB		(1<<18)
#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
#define   MI_FLUSH_DW_OP_MASK		(3<<14)
#define   MI_FLUSH_DW_NOTIFY		(1<<8)
#define   MI_INVALIDATE_BSD		(1<<7)
#define   MI_FLUSH_DW_USE_GTT		(1<<2)
#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
#define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
#define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
#define   MI_BATCH_NON_SECURE		(1)
/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
#define   MI_BATCH_NON_SECURE_I965	(1<<8)
#define   MI_BATCH_PPGTT_HSW		(1<<8)
#define   MI_BATCH_NON_SECURE_HSW	(1<<13)
#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
#define   MI_BATCH_RESOURCE_STREAMER (1<<10)

#define MI_PREDICATE_SRC0	_MMIO(0x2400)
#define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
#define MI_PREDICATE_SRC1	_MMIO(0x2408)
#define MI_PREDICATE_SRC1_UDW	_MMIO(0x2408 + 4)

#define MI_PREDICATE_RESULT_2	_MMIO(0x2214)
#define  LOWER_SLICE_ENABLED	(1<<0)
#define  LOWER_SLICE_DISABLED	(0<<0)

/*
 * 3D instructions used by the kernel
 */
#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))

#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define   SC_UPDATE_SCISSOR       (0x1<<1)
#define   SC_ENABLE_MASK          (0x1<<0)
#define   SC_ENABLE               (0x1<<0)
#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
#define   SCI_YMIN_MASK      (0xffff<<16)
#define   SCI_XMIN_MASK      (0xffff<<0)
#define   SCI_YMAX_MASK      (0xffff<<16)
#define   SCI_XMAX_MASK      (0xffff<<0)
#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)

#define COLOR_BLT_CMD			(2<<29 | 0x40<<22 | (5-2))
#define SRC_COPY_BLT_CMD		((2<<29)|(0x43<<22)|4)
#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
#define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
#define   BLT_WRITE_A			(2<<20)
#define   BLT_WRITE_RGB			(1<<20)
#define   BLT_WRITE_RGBA		(BLT_WRITE_RGB | BLT_WRITE_A)
#define   BLT_DEPTH_8			(0<<24)
#define   BLT_DEPTH_16_565		(1<<24)
#define   BLT_DEPTH_16_1555		(2<<24)
#define   BLT_DEPTH_32			(3<<24)
#define   BLT_ROP_SRC_COPY		(0xcc<<16)
#define   BLT_ROP_COLOR_COPY		(0xf0<<16)
#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
#define   ASYNC_FLIP                (1<<22)
#define   DISPLAY_PLANE_A           (0<<20)
#define   DISPLAY_PLANE_B           (1<<20)
#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
#define   PIPE_CONTROL_FLUSH_L3				(1<<27)
#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
#define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
#define   PIPE_CONTROL_CS_STALL				(1<<20)
#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
#define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
#define   PIPE_CONTROL_QW_WRITE				(1<<14)
#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
#define   PIPE_CONTROL_NOTIFY				(1<<8)
#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */

/*
 * Commands used only by the command parser
 */
#define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
#define MI_ARB_CHECK            MI_INSTR(0x05, 0)
#define MI_RS_CONTROL           MI_INSTR(0x06, 0)
#define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
#define MI_PREDICATE            MI_INSTR(0x0C, 0)
#define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
#define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
#define MI_URB_CLEAR            MI_INSTR(0x19, 0)
#define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
#define MI_CLFLUSH              MI_INSTR(0x27, 0)
#define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
#define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
#define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 0)
#define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
#define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
#define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)

#define PIPELINE_SELECT                ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
#define GFX_OP_3DSTATE_VF_STATISTICS   ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
#define MEDIA_VFE_STATE                ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
#define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
#define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
#define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
#define GFX_OP_3DSTATE_SO_DECL_LIST \
	((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))

#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))

#define MFX_WAIT  ((0x3<<29)|(0x1<<27)|(0x0<<16))

#define COLOR_BLT     ((0x2<<29)|(0x40<<22))
#define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))

/*
 * Registers used only by the command parser
 */
#define BCS_SWCTRL _MMIO(0x22200)

#define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
#define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)
#define HS_INVOCATION_COUNT             _MMIO(0x2300)
#define HS_INVOCATION_COUNT_UDW		_MMIO(0x2300 + 4)
#define DS_INVOCATION_COUNT             _MMIO(0x2308)
#define DS_INVOCATION_COUNT_UDW		_MMIO(0x2308 + 4)
#define IA_VERTICES_COUNT               _MMIO(0x2310)
#define IA_VERTICES_COUNT_UDW		_MMIO(0x2310 + 4)
#define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
#define IA_PRIMITIVES_COUNT_UDW		_MMIO(0x2318 + 4)
#define VS_INVOCATION_COUNT             _MMIO(0x2320)
#define VS_INVOCATION_COUNT_UDW		_MMIO(0x2320 + 4)
#define GS_INVOCATION_COUNT             _MMIO(0x2328)
#define GS_INVOCATION_COUNT_UDW		_MMIO(0x2328 + 4)
#define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
#define GS_PRIMITIVES_COUNT_UDW		_MMIO(0x2330 + 4)
#define CL_INVOCATION_COUNT             _MMIO(0x2338)
#define CL_INVOCATION_COUNT_UDW		_MMIO(0x2338 + 4)
#define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
#define CL_PRIMITIVES_COUNT_UDW		_MMIO(0x2340 + 4)
#define PS_INVOCATION_COUNT             _MMIO(0x2348)
#define PS_INVOCATION_COUNT_UDW		_MMIO(0x2348 + 4)
#define PS_DEPTH_COUNT                  _MMIO(0x2350)
#define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)

/* There are the 4 64-bit counter registers, one for each stream output */
#define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)

#define GEN7_SO_PRIM_STORAGE_NEEDED(n)		_MMIO(0x5240 + (n) * 8)
#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)	_MMIO(0x5240 + (n) * 8 + 4)

#define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
#define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
#define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
#define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
#define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
#define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)

#define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
#define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
#define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)

/* There are the 16 64-bit CS General Purpose Registers */
#define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
#define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)

#define GEN7_OACONTROL _MMIO(0x2360)
#define  GEN7_OACONTROL_CTX_MASK	    0xFFFFF000
#define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
#define  GEN7_OACONTROL_TIMER_PERIOD_SHIFT  6
#define  GEN7_OACONTROL_TIMER_ENABLE	    (1<<5)
#define  GEN7_OACONTROL_FORMAT_A13	    (0<<2)
#define  GEN7_OACONTROL_FORMAT_A29	    (1<<2)
#define  GEN7_OACONTROL_FORMAT_A13_B8_C8    (2<<2)
#define  GEN7_OACONTROL_FORMAT_A29_B8_C8    (3<<2)
#define  GEN7_OACONTROL_FORMAT_B4_C8	    (4<<2)
#define  GEN7_OACONTROL_FORMAT_A45_B8_C8    (5<<2)
#define  GEN7_OACONTROL_FORMAT_B4_C8_A16    (6<<2)
#define  GEN7_OACONTROL_FORMAT_C4_B8	    (7<<2)
#define  GEN7_OACONTROL_FORMAT_SHIFT	    2
#define  GEN7_OACONTROL_PER_CTX_ENABLE	    (1<<1)
#define  GEN7_OACONTROL_ENABLE		    (1<<0)

#define GEN8_OACTXID _MMIO(0x2364)

#define GEN8_OA_DEBUG _MMIO(0x2B04)
#define  GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS    (1<<5)
#define  GEN9_OA_DEBUG_INCLUDE_CLK_RATIO	    (1<<6)
#define  GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS	    (1<<2)
#define  GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS   (1<<1)

#define GEN8_OACONTROL _MMIO(0x2B00)
#define  GEN8_OA_REPORT_FORMAT_A12	    (0<<2)
#define  GEN8_OA_REPORT_FORMAT_A12_B8_C8    (2<<2)
#define  GEN8_OA_REPORT_FORMAT_A36_B8_C8    (5<<2)
#define  GEN8_OA_REPORT_FORMAT_C4_B8	    (7<<2)
#define  GEN8_OA_REPORT_FORMAT_SHIFT	    2
#define  GEN8_OA_SPECIFIC_CONTEXT_ENABLE    (1<<1)
#define  GEN8_OA_COUNTER_ENABLE             (1<<0)

#define GEN8_OACTXCONTROL _MMIO(0x2360)
#define  GEN8_OA_TIMER_PERIOD_MASK	    0x3F
#define  GEN8_OA_TIMER_PERIOD_SHIFT	    2
#define  GEN8_OA_TIMER_ENABLE		    (1<<1)
#define  GEN8_OA_COUNTER_RESUME		    (1<<0)

#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
#define  GEN7_OABUFFER_OVERRUN_DISABLE	    (1<<3)
#define  GEN7_OABUFFER_EDGE_TRIGGER	    (1<<2)
#define  GEN7_OABUFFER_STOP_RESUME_ENABLE   (1<<1)
#define  GEN7_OABUFFER_RESUME		    (1<<0)

#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
#define GEN8_OABUFFER _MMIO(0x2b14)

#define GEN7_OASTATUS1 _MMIO(0x2364)
#define  GEN7_OASTATUS1_TAIL_MASK	    0xffffffc0
#define  GEN7_OASTATUS1_COUNTER_OVERFLOW    (1<<2)
#define  GEN7_OASTATUS1_OABUFFER_OVERFLOW   (1<<1)
#define  GEN7_OASTATUS1_REPORT_LOST	    (1<<0)

#define GEN7_OASTATUS2 _MMIO(0x2368)
#define GEN7_OASTATUS2_HEAD_MASK    0xffffffc0

#define GEN8_OASTATUS _MMIO(0x2b08)
#define  GEN8_OASTATUS_OVERRUN_STATUS	    (1<<3)
#define  GEN8_OASTATUS_COUNTER_OVERFLOW     (1<<2)
#define  GEN8_OASTATUS_OABUFFER_OVERFLOW    (1<<1)
#define  GEN8_OASTATUS_REPORT_LOST	    (1<<0)

#define GEN8_OAHEADPTR _MMIO(0x2B0C)
#define GEN8_OAHEADPTR_MASK    0xffffffc0
#define GEN8_OATAILPTR _MMIO(0x2B10)
#define GEN8_OATAILPTR_MASK    0xffffffc0

#define OABUFFER_SIZE_128K  (0<<3)
#define OABUFFER_SIZE_256K  (1<<3)
#define OABUFFER_SIZE_512K  (2<<3)
#define OABUFFER_SIZE_1M    (3<<3)
#define OABUFFER_SIZE_2M    (4<<3)
#define OABUFFER_SIZE_4M    (5<<3)
#define OABUFFER_SIZE_8M    (6<<3)
#define OABUFFER_SIZE_16M   (7<<3)

#define OA_MEM_SELECT_GGTT  (1<<0)

/*
 * Flexible, Aggregate EU Counter Registers.
 * Note: these aren't contiguous
 */
#define EU_PERF_CNTL0	    _MMIO(0xe458)
#define EU_PERF_CNTL1	    _MMIO(0xe558)
#define EU_PERF_CNTL2	    _MMIO(0xe658)
#define EU_PERF_CNTL3	    _MMIO(0xe758)
#define EU_PERF_CNTL4	    _MMIO(0xe45c)
#define EU_PERF_CNTL5	    _MMIO(0xe55c)
#define EU_PERF_CNTL6	    _MMIO(0xe65c)

/*
 * OA Boolean state
 */

#define OASTARTTRIG1 _MMIO(0x2710)
#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
#define OASTARTTRIG1_THRESHOLD_MASK	      0xffff

#define OASTARTTRIG2 _MMIO(0x2714)
#define OASTARTTRIG2_INVERT_A_0 (1<<0)
#define OASTARTTRIG2_INVERT_A_1 (1<<1)
#define OASTARTTRIG2_INVERT_A_2 (1<<2)
#define OASTARTTRIG2_INVERT_A_3 (1<<3)
#define OASTARTTRIG2_INVERT_A_4 (1<<4)
#define OASTARTTRIG2_INVERT_A_5 (1<<5)
#define OASTARTTRIG2_INVERT_A_6 (1<<6)
#define OASTARTTRIG2_INVERT_A_7 (1<<7)
#define OASTARTTRIG2_INVERT_A_8 (1<<8)
#define OASTARTTRIG2_INVERT_A_9 (1<<9)
#define OASTARTTRIG2_INVERT_A_10 (1<<10)
#define OASTARTTRIG2_INVERT_A_11 (1<<11)
#define OASTARTTRIG2_INVERT_A_12 (1<<12)
#define OASTARTTRIG2_INVERT_A_13 (1<<13)
#define OASTARTTRIG2_INVERT_A_14 (1<<14)
#define OASTARTTRIG2_INVERT_A_15 (1<<15)
#define OASTARTTRIG2_INVERT_B_0 (1<<16)
#define OASTARTTRIG2_INVERT_B_1 (1<<17)
#define OASTARTTRIG2_INVERT_B_2 (1<<18)
#define OASTARTTRIG2_INVERT_B_3 (1<<19)
#define OASTARTTRIG2_INVERT_C_0 (1<<20)
#define OASTARTTRIG2_INVERT_C_1 (1<<21)
#define OASTARTTRIG2_INVERT_D_0 (1<<22)
#define OASTARTTRIG2_THRESHOLD_ENABLE	    (1<<23)
#define OASTARTTRIG2_START_TRIG_FLAG_MBZ    (1<<24)
#define OASTARTTRIG2_EVENT_SELECT_0  (1<<28)
#define OASTARTTRIG2_EVENT_SELECT_1  (1<<29)
#define OASTARTTRIG2_EVENT_SELECT_2  (1<<30)
#define OASTARTTRIG2_EVENT_SELECT_3  (1<<31)

#define OASTARTTRIG3 _MMIO(0x2718)
#define OASTARTTRIG3_NOA_SELECT_MASK	   0xf
#define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
#define OASTARTTRIG3_NOA_SELECT_9_SHIFT    4
#define OASTARTTRIG3_NOA_SELECT_10_SHIFT   8
#define OASTARTTRIG3_NOA_SELECT_11_SHIFT   12
#define OASTARTTRIG3_NOA_SELECT_12_SHIFT   16
#define OASTARTTRIG3_NOA_SELECT_13_SHIFT   20
#define OASTARTTRIG3_NOA_SELECT_14_SHIFT   24
#define OASTARTTRIG3_NOA_SELECT_15_SHIFT   28

#define OASTARTTRIG4 _MMIO(0x271c)
#define OASTARTTRIG4_NOA_SELECT_MASK	    0xf
#define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
#define OASTARTTRIG4_NOA_SELECT_1_SHIFT    4
#define OASTARTTRIG4_NOA_SELECT_2_SHIFT    8
#define OASTARTTRIG4_NOA_SELECT_3_SHIFT    12
#define OASTARTTRIG4_NOA_SELECT_4_SHIFT    16
#define OASTARTTRIG4_NOA_SELECT_5_SHIFT    20
#define OASTARTTRIG4_NOA_SELECT_6_SHIFT    24
#define OASTARTTRIG4_NOA_SELECT_7_SHIFT    28

#define OASTARTTRIG5 _MMIO(0x2720)
#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
#define OASTARTTRIG5_THRESHOLD_MASK	      0xffff

#define OASTARTTRIG6 _MMIO(0x2724)
#define OASTARTTRIG6_INVERT_A_0 (1<<0)
#define OASTARTTRIG6_INVERT_A_1 (1<<1)
#define OASTARTTRIG6_INVERT_A_2 (1<<2)
#define OASTARTTRIG6_INVERT_A_3 (1<<3)
#define OASTARTTRIG6_INVERT_A_4 (1<<4)
#define OASTARTTRIG6_INVERT_A_5 (1<<5)
#define OASTARTTRIG6_INVERT_A_6 (1<<6)
#define OASTARTTRIG6_INVERT_A_7 (1<<7)
#define OASTARTTRIG6_INVERT_A_8 (1<<8)
#define OASTARTTRIG6_INVERT_A_9 (1<<9)
#define OASTARTTRIG6_INVERT_A_10 (1<<10)
#define OASTARTTRIG6_INVERT_A_11 (1<<11)
#define OASTARTTRIG6_INVERT_A_12 (1<<12)
#define OASTARTTRIG6_INVERT_A_13 (1<<13)
#define OASTARTTRIG6_INVERT_A_14 (1<<14)
#define OASTARTTRIG6_INVERT_A_15 (1<<15)
#define OASTARTTRIG6_INVERT_B_0 (1<<16)
#define OASTARTTRIG6_INVERT_B_1 (1<<17)
#define OASTARTTRIG6_INVERT_B_2 (1<<18)
#define OASTARTTRIG6_INVERT_B_3 (1<<19)
#define OASTARTTRIG6_INVERT_C_0 (1<<20)
#define OASTARTTRIG6_INVERT_C_1 (1<<21)
#define OASTARTTRIG6_INVERT_D_0 (1<<22)
#define OASTARTTRIG6_THRESHOLD_ENABLE	    (1<<23)
#define OASTARTTRIG6_START_TRIG_FLAG_MBZ    (1<<24)
#define OASTARTTRIG6_EVENT_SELECT_4  (1<<28)
#define OASTARTTRIG6_EVENT_SELECT_5  (1<<29)
#define OASTARTTRIG6_EVENT_SELECT_6  (1<<30)
#define OASTARTTRIG6_EVENT_SELECT_7  (1<<31)

#define OASTARTTRIG7 _MMIO(0x2728)
#define OASTARTTRIG7_NOA_SELECT_MASK	   0xf
#define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
#define OASTARTTRIG7_NOA_SELECT_9_SHIFT    4
#define OASTARTTRIG7_NOA_SELECT_10_SHIFT   8
#define OASTARTTRIG7_NOA_SELECT_11_SHIFT   12
#define OASTARTTRIG7_NOA_SELECT_12_SHIFT   16
#define OASTARTTRIG7_NOA_SELECT_13_SHIFT   20
#define OASTARTTRIG7_NOA_SELECT_14_SHIFT   24
#define OASTARTTRIG7_NOA_SELECT_15_SHIFT   28

#define OASTARTTRIG8 _MMIO(0x272c)
#define OASTARTTRIG8_NOA_SELECT_MASK	   0xf
#define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
#define OASTARTTRIG8_NOA_SELECT_1_SHIFT    4
#define OASTARTTRIG8_NOA_SELECT_2_SHIFT    8
#define OASTARTTRIG8_NOA_SELECT_3_SHIFT    12
#define OASTARTTRIG8_NOA_SELECT_4_SHIFT    16
#define OASTARTTRIG8_NOA_SELECT_5_SHIFT    20
#define OASTARTTRIG8_NOA_SELECT_6_SHIFT    24
#define OASTARTTRIG8_NOA_SELECT_7_SHIFT    28

#define OAREPORTTRIG1 _MMIO(0x2740)
#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */

#define OAREPORTTRIG2 _MMIO(0x2744)
#define OAREPORTTRIG2_INVERT_A_0  (1<<0)
#define OAREPORTTRIG2_INVERT_A_1  (1<<1)
#define OAREPORTTRIG2_INVERT_A_2  (1<<2)
#define OAREPORTTRIG2_INVERT_A_3  (1<<3)
#define OAREPORTTRIG2_INVERT_A_4  (1<<4)
#define OAREPORTTRIG2_INVERT_A_5  (1<<5)
#define OAREPORTTRIG2_INVERT_A_6  (1<<6)
#define OAREPORTTRIG2_INVERT_A_7  (1<<7)
#define OAREPORTTRIG2_INVERT_A_8  (1<<8)
#define OAREPORTTRIG2_INVERT_A_9  (1<<9)
#define OAREPORTTRIG2_INVERT_A_10 (1<<10)
#define OAREPORTTRIG2_INVERT_A_11 (1<<11)
#define OAREPORTTRIG2_INVERT_A_12 (1<<12)
#define OAREPORTTRIG2_INVERT_A_13 (1<<13)
#define OAREPORTTRIG2_INVERT_A_14 (1<<14)
#define OAREPORTTRIG2_INVERT_A_15 (1<<15)
#define OAREPORTTRIG2_INVERT_B_0  (1<<16)
#define OAREPORTTRIG2_INVERT_B_1  (1<<17)
#define OAREPORTTRIG2_INVERT_B_2  (1<<18)
#define OAREPORTTRIG2_INVERT_B_3  (1<<19)
#define OAREPORTTRIG2_INVERT_C_0  (1<<20)
#define OAREPORTTRIG2_INVERT_C_1  (1<<21)
#define OAREPORTTRIG2_INVERT_D_0  (1<<22)
#define OAREPORTTRIG2_THRESHOLD_ENABLE	    (1<<23)
#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31)

#define OAREPORTTRIG3 _MMIO(0x2748)
#define OAREPORTTRIG3_NOA_SELECT_MASK	    0xf
#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT    4
#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT   8
#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT   12
#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT   16
#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT   20
#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT   24
#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT   28

#define OAREPORTTRIG4 _MMIO(0x274c)
#define OAREPORTTRIG4_NOA_SELECT_MASK	    0xf
#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT    4
#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT    8
#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT    12
#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT    16
#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT    20
#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT    24
#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT    28

#define OAREPORTTRIG5 _MMIO(0x2750)
#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */

#define OAREPORTTRIG6 _MMIO(0x2754)
#define OAREPORTTRIG6_INVERT_A_0  (1<<0)
#define OAREPORTTRIG6_INVERT_A_1  (1<<1)
#define OAREPORTTRIG6_INVERT_A_2  (1<<2)
#define OAREPORTTRIG6_INVERT_A_3  (1<<3)
#define OAREPORTTRIG6_INVERT_A_4  (1<<4)
#define OAREPORTTRIG6_INVERT_A_5  (1<<5)
#define OAREPORTTRIG6_INVERT_A_6  (1<<6)
#define OAREPORTTRIG6_INVERT_A_7  (1<<7)
#define OAREPORTTRIG6_INVERT_A_8  (1<<8)
#define OAREPORTTRIG6_INVERT_A_9  (1<<9)
#define OAREPORTTRIG6_INVERT_A_10 (1<<10)
#define OAREPORTTRIG6_INVERT_A_11 (1<<11)
#define OAREPORTTRIG6_INVERT_A_12 (1<<12)
#define OAREPORTTRIG6_INVERT_A_13 (1<<13)
#define OAREPORTTRIG6_INVERT_A_14 (1<<14)
#define OAREPORTTRIG6_INVERT_A_15 (1<<15)
#define OAREPORTTRIG6_INVERT_B_0  (1<<16)
#define OAREPORTTRIG6_INVERT_B_1  (1<<17)
#define OAREPORTTRIG6_INVERT_B_2  (1<<18)
#define OAREPORTTRIG6_INVERT_B_3  (1<<19)
#define OAREPORTTRIG6_INVERT_C_0  (1<<20)
#define OAREPORTTRIG6_INVERT_C_1  (1<<21)
#define OAREPORTTRIG6_INVERT_D_0  (1<<22)
#define OAREPORTTRIG6_THRESHOLD_ENABLE	    (1<<23)
#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31)

#define OAREPORTTRIG7 _MMIO(0x2758)
#define OAREPORTTRIG7_NOA_SELECT_MASK	    0xf
#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT    4
#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT   8
#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT   12
#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT   16
#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT   20
#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT   24
#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT   28

#define OAREPORTTRIG8 _MMIO(0x275c)
#define OAREPORTTRIG8_NOA_SELECT_MASK	    0xf
#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT    4
#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT    8
#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT    12
#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT    16
#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT    20
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT    24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT    28

/* CECX_0 */
#define OACEC_COMPARE_LESS_OR_EQUAL	6
#define OACEC_COMPARE_NOT_EQUAL		5
#define OACEC_COMPARE_LESS_THAN		4
#define OACEC_COMPARE_GREATER_OR_EQUAL	3
#define OACEC_COMPARE_EQUAL		2
#define OACEC_COMPARE_GREATER_THAN	1
#define OACEC_COMPARE_ANY_EQUAL		0

#define OACEC_COMPARE_VALUE_MASK    0xffff
#define OACEC_COMPARE_VALUE_SHIFT   3

#define OACEC_SELECT_NOA	(0<<19)
#define OACEC_SELECT_PREV	(1<<19)
#define OACEC_SELECT_BOOLEAN	(2<<19)

/* CECX_1 */
#define OACEC_MASK_MASK		    0xffff
#define OACEC_CONSIDERATIONS_MASK   0xffff
#define OACEC_CONSIDERATIONS_SHIFT  16

#define OACEC0_0 _MMIO(0x2770)
#define OACEC0_1 _MMIO(0x2774)
#define OACEC1_0 _MMIO(0x2778)
#define OACEC1_1 _MMIO(0x277c)
#define OACEC2_0 _MMIO(0x2780)
#define OACEC2_1 _MMIO(0x2784)
#define OACEC3_0 _MMIO(0x2788)
#define OACEC3_1 _MMIO(0x278c)
#define OACEC4_0 _MMIO(0x2790)
#define OACEC4_1 _MMIO(0x2794)
#define OACEC5_0 _MMIO(0x2798)
#define OACEC5_1 _MMIO(0x279c)
#define OACEC6_0 _MMIO(0x27a0)
#define OACEC6_1 _MMIO(0x27a4)
#define OACEC7_0 _MMIO(0x27a8)
#define OACEC7_1 _MMIO(0x27ac)

/* OA perf counters */
#define OA_PERFCNT1_LO      _MMIO(0x91B8)
#define OA_PERFCNT1_HI      _MMIO(0x91BC)
#define OA_PERFCNT2_LO      _MMIO(0x91C0)
#define OA_PERFCNT2_HI      _MMIO(0x91C4)

#define OA_PERFMATRIX_LO    _MMIO(0x91C8)
#define OA_PERFMATRIX_HI    _MMIO(0x91CC)

/* RPM unit config (Gen8+) */
#define RPM_CONFIG0	    _MMIO(0x0D00)
#define RPM_CONFIG1	    _MMIO(0x0D04)

/* RPC unit config (Gen8+) */
#define RPM_CONFIG	    _MMIO(0x0D08)

/* NOA (Gen8+) */
#define NOA_CONFIG(i)	    _MMIO(0x0D0C + (i) * 4)

#define MICRO_BP0_0	    _MMIO(0x9800)
#define MICRO_BP0_2	    _MMIO(0x9804)
#define MICRO_BP0_1	    _MMIO(0x9808)

#define MICRO_BP1_0	    _MMIO(0x980C)
#define MICRO_BP1_2	    _MMIO(0x9810)
#define MICRO_BP1_1	    _MMIO(0x9814)

#define MICRO_BP2_0	    _MMIO(0x9818)
#define MICRO_BP2_2	    _MMIO(0x981C)
#define MICRO_BP2_1	    _MMIO(0x9820)

#define MICRO_BP3_0	    _MMIO(0x9824)
#define MICRO_BP3_2	    _MMIO(0x9828)
#define MICRO_BP3_1	    _MMIO(0x982C)

#define MICRO_BP_TRIGGER		_MMIO(0x9830)
#define MICRO_BP3_COUNT_STATUS01	_MMIO(0x9834)
#define MICRO_BP3_COUNT_STATUS23	_MMIO(0x9838)
#define MICRO_BP_FIRED_ARMED		_MMIO(0x983C)

#define GDT_CHICKEN_BITS    _MMIO(0x9840)
#define   GT_NOA_ENABLE	    0x00000080

#define NOA_DATA	    _MMIO(0x986C)
#define NOA_WRITE	    _MMIO(0x9888)

#define _GEN7_PIPEA_DE_LOAD_SL	0x70068
#define _GEN7_PIPEB_DE_LOAD_SL	0x71068
#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)

/*
 * Reset registers
 */
#define DEBUG_RESET_I830		_MMIO(0x6070)
#define  DEBUG_RESET_FULL		(1<<7)
#define  DEBUG_RESET_RENDER		(1<<8)
#define  DEBUG_RESET_DISPLAY		(1<<9)

/*
 * IOSF sideband
 */
#define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
#define   IOSF_DEVFN_SHIFT			24
#define   IOSF_OPCODE_SHIFT			16
#define   IOSF_PORT_SHIFT			8
#define   IOSF_BYTE_ENABLES_SHIFT		4
#define   IOSF_BAR_SHIFT			1
#define   IOSF_SB_BUSY				(1<<0)
#define   IOSF_PORT_BUNIT			0x03
#define   IOSF_PORT_PUNIT			0x04
#define   IOSF_PORT_NC				0x11
#define   IOSF_PORT_DPIO			0x12
#define   IOSF_PORT_GPIO_NC			0x13
#define   IOSF_PORT_CCK				0x14
#define   IOSF_PORT_DPIO_2			0x1a
#define   IOSF_PORT_FLISDSI			0x1b
#define   IOSF_PORT_GPIO_SC			0x48
#define   IOSF_PORT_GPIO_SUS			0xa8
#define   IOSF_PORT_CCU				0xa9
#define   CHV_IOSF_PORT_GPIO_N			0x13
#define   CHV_IOSF_PORT_GPIO_SE			0x48
#define   CHV_IOSF_PORT_GPIO_E			0xa8
#define   CHV_IOSF_PORT_GPIO_SW			0xb2
#define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
#define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)

/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC				0x11

#define PUNIT_REG_DSPFREQ			0x36
#define   DSPFREQSTAT_SHIFT_CHV			24
#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
#define   DSPFREQGUAR_SHIFT_CHV			8
#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
#define   DSPFREQSTAT_SHIFT			30
#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
#define   DSPFREQGUAR_SHIFT			14
#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))

/*
 * i915_power_well_id:
 *
 * Platform specific IDs used to look up power wells and - except for custom
 * power wells - to define request/status register flag bit positions. As such
 * the set of IDs on a given platform must be unique and except for custom
 * power wells their value must stay fixed.
 */
enum i915_power_well_id {
	/*
	 * I830
	 *  - custom power well
	 */
	I830_DISP_PW_PIPES = 0,

	/*
	 * VLV/CHV
	 *  - PUNIT_REG_PWRGT_CTRL (bit: id*2),
	 *    PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
	 */
	PUNIT_POWER_WELL_RENDER			= 0,
	PUNIT_POWER_WELL_MEDIA			= 1,
	PUNIT_POWER_WELL_DISP2D			= 3,
	PUNIT_POWER_WELL_DPIO_CMN_BC		= 5,
	PUNIT_POWER_WELL_DPIO_TX_B_LANES_01	= 6,
	PUNIT_POWER_WELL_DPIO_TX_B_LANES_23	= 7,
	PUNIT_POWER_WELL_DPIO_TX_C_LANES_01	= 8,
	PUNIT_POWER_WELL_DPIO_TX_C_LANES_23	= 9,
	PUNIT_POWER_WELL_DPIO_RX0		= 10,
	PUNIT_POWER_WELL_DPIO_RX1		= 11,
	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
	/*  - custom power well */
	CHV_DISP_PW_PIPE_A,			/* 13 */

	/*
	 * HSW/BDW
	 *  - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
	 */
	HSW_DISP_PW_GLOBAL = 15,

	/*
	 * GEN9+
	 *  - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
	 */
	SKL_DISP_PW_MISC_IO = 0,
	SKL_DISP_PW_DDI_A_E,
	GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
	CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
	SKL_DISP_PW_DDI_B,
	SKL_DISP_PW_DDI_C,
	SKL_DISP_PW_DDI_D,

	GLK_DISP_PW_AUX_A = 8,
	GLK_DISP_PW_AUX_B,
	GLK_DISP_PW_AUX_C,
	CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
	CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
	CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
	CNL_DISP_PW_AUX_D,

	SKL_DISP_PW_1 = 14,
	SKL_DISP_PW_2,

	/* - custom power wells */
	SKL_DISP_PW_DC_OFF,
	BXT_DPIO_CMN_A,
	BXT_DPIO_CMN_BC,
	GLK_DPIO_CMN_C,			/* 19 */

	/*
	 * Multiple platforms.
	 * Must start following the highest ID of any platform.
	 * - custom power wells
	 */
	I915_DISP_PW_ALWAYS_ON = 20,
};

#define PUNIT_REG_PWRGT_CTRL			0x60
#define PUNIT_REG_PWRGT_STATUS			0x61
#define   PUNIT_PWRGT_MASK(power_well)		(3 << ((power_well) * 2))
#define   PUNIT_PWRGT_PWR_ON(power_well)	(0 << ((power_well) * 2))
#define   PUNIT_PWRGT_CLK_GATE(power_well)	(1 << ((power_well) * 2))
#define   PUNIT_PWRGT_RESET(power_well)		(2 << ((power_well) * 2))
#define   PUNIT_PWRGT_PWR_GATE(power_well)	(3 << ((power_well) * 2))

#define PUNIT_REG_GPU_LFM			0xd3
#define PUNIT_REG_GPU_FREQ_REQ			0xd4
#define PUNIT_REG_GPU_FREQ_STS			0xd8
#define   GPLLENABLE				(1<<4)
#define   GENFREQSTATUS				(1<<0)
#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
#define PUNIT_REG_CZ_TIMESTAMP			0xce

#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */

#define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
#define FB_GFX_FREQ_FUSE_MASK			0xff
#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8

#define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8

#define PUNIT_REG_DDR_SETUP2			0x139
#define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
#define   FORCE_DDR_LOW_FREQ			(1 << 1)
#define   FORCE_DDR_HIGH_FREQ			(1 << 0)

#define PUNIT_GPU_STATUS_REG			0xdb
#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
#define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff

#define PUNIT_GPU_DUTYCYCLE_REG		0xdf
#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff

#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000

#define VLV_TURBO_SOC_OVERRIDE	0x04
#define 	VLV_OVERRIDE_EN	1
#define 	VLV_SOC_TDP_EN	(1 << 1)
#define 	VLV_BIAS_CPU_125_SOC_875 (6 << 2)
#define 	CHV_BIAS_CPU_50_SOC_50 (3 << 2)

/* vlv2 north clock has */
#define CCK_FUSE_REG				0x8
#define  CCK_FUSE_HPLL_FREQ_MASK		0x3
#define CCK_REG_DSI_PLL_FUSE			0x44
#define CCK_REG_DSI_PLL_CONTROL			0x48
#define  DSI_PLL_VCO_EN				(1 << 31)
#define  DSI_PLL_LDO_GATE			(1 << 30)
#define  DSI_PLL_P1_POST_DIV_SHIFT		17
#define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
#define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
#define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
#define  DSI_PLL_MUX_MASK			(3 << 9)
#define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
#define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
#define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
#define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
#define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
#define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
#define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
#define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
#define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
#define  DSI_PLL_LOCK				(1 << 0)
#define CCK_REG_DSI_PLL_DIVIDER			0x4c
#define  DSI_PLL_LFSR				(1 << 31)
#define  DSI_PLL_FRACTION_EN			(1 << 30)
#define  DSI_PLL_FRAC_COUNTER_SHIFT		27
#define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
#define  DSI_PLL_USYNC_CNT_SHIFT		18
#define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
#define  DSI_PLL_N1_DIV_SHIFT			16
#define  DSI_PLL_N1_DIV_MASK			(3 << 16)
#define  DSI_PLL_M1_DIV_SHIFT			0
#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
#define CCK_CZ_CLOCK_CONTROL			0x62
#define CCK_GPLL_CLOCK_CONTROL			0x67
#define CCK_DISPLAY_CLOCK_CONTROL		0x6b
#define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
#define  CCK_TRUNK_FORCE_ON			(1 << 17)
#define  CCK_TRUNK_FORCE_OFF			(1 << 16)
#define  CCK_FREQUENCY_STATUS			(0x1f << 8)
#define  CCK_FREQUENCY_STATUS_SHIFT		8
#define  CCK_FREQUENCY_VALUES			(0x1f << 0)

/* DPIO registers */
#define DPIO_DEVFN			0

#define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
#define  DPIO_SFR_BYPASS		(1<<1)
#define  DPIO_CMNRST			(1<<0)

#define DPIO_PHY(pipe)			((pipe) >> 1)
#define DPIO_PHY_IOSF_PORT(phy)		(dev_priv->dpio_phy_iosf_port[phy])

/*
 * Per pipe/PLL DPIO regs
 */
#define _VLV_PLL_DW3_CH0		0x800c
#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
#define   DPIO_POST_DIV_DAC		0
#define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
#define   DPIO_POST_DIV_LVDS1		2
#define   DPIO_POST_DIV_LVDS2		3
#define   DPIO_K_SHIFT			(24) /* 4 bits */
#define   DPIO_P1_SHIFT			(21) /* 3 bits */
#define   DPIO_P2_SHIFT			(16) /* 5 bits */
#define   DPIO_N_SHIFT			(12) /* 4 bits */
#define   DPIO_ENABLE_CALIBRATION	(1<<11)
#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
#define   DPIO_M2DIV_MASK		0xff
#define _VLV_PLL_DW3_CH1		0x802c
#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)

#define _VLV_PLL_DW5_CH0		0x8014
#define   DPIO_REFSEL_OVERRIDE		27
#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
#define   DPIO_PLL_REFCLK_SEL_MASK	3
#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
#define _VLV_PLL_DW5_CH1		0x8034
#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)

#define _VLV_PLL_DW7_CH0		0x801c
#define _VLV_PLL_DW7_CH1		0x803c
#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)

#define _VLV_PLL_DW8_CH0		0x8040
#define _VLV_PLL_DW8_CH1		0x8060
#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)

#define VLV_PLL_DW9_BCAST		0xc044
#define _VLV_PLL_DW9_CH0		0x8044
#define _VLV_PLL_DW9_CH1		0x8064
#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)

#define _VLV_PLL_DW10_CH0		0x8048
#define _VLV_PLL_DW10_CH1		0x8068
#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)

#define _VLV_PLL_DW11_CH0		0x804c
#define _VLV_PLL_DW11_CH1		0x806c
#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)

/* Spec for ref block start counts at DW10 */
#define VLV_REF_DW13			0x80ac

#define VLV_CMN_DW0			0x8100

/*
 * Per DDI channel DPIO regs
 */

#define _VLV_PCS_DW0_CH0		0x8200
#define _VLV_PCS_DW0_CH1		0x8400
#define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
#define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1<<4)
#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1<<3)
#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)

#define _VLV_PCS01_DW0_CH0		0x200
#define _VLV_PCS23_DW0_CH0		0x400
#define _VLV_PCS01_DW0_CH1		0x2600
#define _VLV_PCS23_DW0_CH1		0x2800
#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)

#define _VLV_PCS_DW1_CH0		0x8204
#define _VLV_PCS_DW1_CH1		0x8404
#define   CHV_PCS_REQ_SOFTRESET_EN	(1<<23)
#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)
#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
#define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)

#define _VLV_PCS01_DW1_CH0		0x204
#define _VLV_PCS23_DW1_CH0		0x404
#define _VLV_PCS01_DW1_CH1		0x2604
#define _VLV_PCS23_DW1_CH1		0x2804
#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)

#define _VLV_PCS_DW8_CH0		0x8220
#define _VLV_PCS_DW8_CH1		0x8420
#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)

#define _VLV_PCS01_DW8_CH0		0x0220
#define _VLV_PCS23_DW8_CH0		0x0420
#define _VLV_PCS01_DW8_CH1		0x2620
#define _VLV_PCS23_DW8_CH1		0x2820
#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)

#define _VLV_PCS_DW9_CH0		0x8224
#define _VLV_PCS_DW9_CH1		0x8424
#define   DPIO_PCS_TX2MARGIN_MASK	(0x7<<13)
#define   DPIO_PCS_TX2MARGIN_000	(0<<13)
#define   DPIO_PCS_TX2MARGIN_101	(1<<13)
#define   DPIO_PCS_TX1MARGIN_MASK	(0x7<<10)
#define   DPIO_PCS_TX1MARGIN_000	(0<<10)
#define   DPIO_PCS_TX1MARGIN_101	(1<<10)
#define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)

#define _VLV_PCS01_DW9_CH0		0x224
#define _VLV_PCS23_DW9_CH0		0x424
#define _VLV_PCS01_DW9_CH1		0x2624
#define _VLV_PCS23_DW9_CH1		0x2824
#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)

#define _CHV_PCS_DW10_CH0		0x8228
#define _CHV_PCS_DW10_CH1		0x8428
#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1<<30)
#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1<<31)
#define   DPIO_PCS_TX2DEEMP_MASK	(0xf<<24)
#define   DPIO_PCS_TX2DEEMP_9P5		(0<<24)
#define   DPIO_PCS_TX2DEEMP_6P0		(2<<24)
#define   DPIO_PCS_TX1DEEMP_MASK	(0xf<<16)
#define   DPIO_PCS_TX1DEEMP_9P5		(0<<16)
#define   DPIO_PCS_TX1DEEMP_6P0		(2<<16)
#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)

#define _VLV_PCS01_DW10_CH0		0x0228
#define _VLV_PCS23_DW10_CH0		0x0428
#define _VLV_PCS01_DW10_CH1		0x2628
#define _VLV_PCS23_DW10_CH1		0x2828
#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)

#define _VLV_PCS_DW11_CH0		0x822c
#define _VLV_PCS_DW11_CH1		0x842c
#define   DPIO_TX2_STAGGER_MASK(x)	((x)<<24)
#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)
#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)
#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)

#define _VLV_PCS01_DW11_CH0		0x022c
#define _VLV_PCS23_DW11_CH0		0x042c
#define _VLV_PCS01_DW11_CH1		0x262c
#define _VLV_PCS23_DW11_CH1		0x282c
#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)

#define _VLV_PCS01_DW12_CH0		0x0230
#define _VLV_PCS23_DW12_CH0		0x0430
#define _VLV_PCS01_DW12_CH1		0x2630
#define _VLV_PCS23_DW12_CH1		0x2830
#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)

#define _VLV_PCS_DW12_CH0		0x8230
#define _VLV_PCS_DW12_CH1		0x8430
#define   DPIO_TX2_STAGGER_MULT(x)	((x)<<20)
#define   DPIO_TX1_STAGGER_MULT(x)	((x)<<16)
#define   DPIO_TX1_STAGGER_MASK(x)	((x)<<8)
#define   DPIO_LANESTAGGER_STRAP_OVRD	(1<<6)
#define   DPIO_LANESTAGGER_STRAP(x)	((x)<<0)
#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)

#define _VLV_PCS_DW14_CH0		0x8238
#define _VLV_PCS_DW14_CH1		0x8438
#define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)

#define _VLV_PCS_DW23_CH0		0x825c
#define _VLV_PCS_DW23_CH1		0x845c
#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)

#define _VLV_TX_DW2_CH0			0x8288
#define _VLV_TX_DW2_CH1			0x8488
#define   DPIO_SWING_MARGIN000_SHIFT	16
#define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)

#define _VLV_TX_DW3_CH0			0x828c
#define _VLV_TX_DW3_CH1			0x848c
/* The following bit for CHV phy */
#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1<<27)
#define   DPIO_SWING_MARGIN101_SHIFT	16
#define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)

#define _VLV_TX_DW4_CH0			0x8290
#define _VLV_TX_DW4_CH1			0x8490
#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
#define   DPIO_SWING_DEEMPH6P0_SHIFT	16
#define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)

#define _VLV_TX3_DW4_CH0		0x690
#define _VLV_TX3_DW4_CH1		0x2a90
#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)

#define _VLV_TX_DW5_CH0			0x8294
#define _VLV_TX_DW5_CH1			0x8494
#define   DPIO_TX_OCALINIT_EN		(1<<31)
#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)

#define _VLV_TX_DW11_CH0		0x82ac
#define _VLV_TX_DW11_CH1		0x84ac
#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)

#define _VLV_TX_DW14_CH0		0x82b8
#define _VLV_TX_DW14_CH1		0x84b8
#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)

/* CHV dpPhy registers */
#define _CHV_PLL_DW0_CH0		0x8000
#define _CHV_PLL_DW0_CH1		0x8180
#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)

#define _CHV_PLL_DW1_CH0		0x8004
#define _CHV_PLL_DW1_CH1		0x8184
#define   DPIO_CHV_N_DIV_SHIFT		8
#define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)

#define _CHV_PLL_DW2_CH0		0x8008
#define _CHV_PLL_DW2_CH1		0x8188
#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)

#define _CHV_PLL_DW3_CH0		0x800c
#define _CHV_PLL_DW3_CH1		0x818c
#define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
#define  DPIO_CHV_FIRST_MOD		(0 << 8)
#define  DPIO_CHV_SECOND_MOD		(1 << 8)
#define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)

#define _CHV_PLL_DW6_CH0		0x8018
#define _CHV_PLL_DW6_CH1		0x8198
#define   DPIO_CHV_GAIN_CTRL_SHIFT	16
#define	  DPIO_CHV_INT_COEFF_SHIFT	8
#define   DPIO_CHV_PROP_COEFF_SHIFT	0
#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)

#define _CHV_PLL_DW8_CH0		0x8020
#define _CHV_PLL_DW8_CH1		0x81A0
#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)

#define _CHV_PLL_DW9_CH0		0x8024
#define _CHV_PLL_DW9_CH1		0x81A4
#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)

#define _CHV_CMN_DW0_CH0               0x8100
#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
#define   DPIO_ALLDL_POWERDOWN			(1 << 1)
#define   DPIO_ANYDL_POWERDOWN			(1 << 0)

#define _CHV_CMN_DW5_CH0               0x8114
#define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
#define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
#define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
#define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
#define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
#define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
#define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
#define   CHV_BUFLEFTENA1_MASK		(3 << 22)

#define _CHV_CMN_DW13_CH0		0x8134
#define _CHV_CMN_DW0_CH1		0x8080
#define   DPIO_CHV_S1_DIV_SHIFT		21
#define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
#define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
#define   DPIO_CHV_K_DIV_SHIFT		4
#define   DPIO_PLL_FREQLOCK		(1 << 1)
#define   DPIO_PLL_LOCK			(1 << 0)
#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)

#define _CHV_CMN_DW14_CH0		0x8138
#define _CHV_CMN_DW1_CH1		0x8084
#define   DPIO_AFC_RECAL		(1 << 14)
#define   DPIO_DCLKP_EN			(1 << 13)
#define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
#define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
#define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
#define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
#define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
#define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
#define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
#define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)

#define _CHV_CMN_DW19_CH0		0x814c
#define _CHV_CMN_DW6_CH1		0x8098
#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
#define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)

#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)

#define CHV_CMN_DW28			0x8170
#define   DPIO_CL1POWERDOWNEN		(1 << 23)
#define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
#define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
#define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
#define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)

#define CHV_CMN_DW30			0x8178
#define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
#define   DPIO_LRC_BYPASS		(1 << 3)

#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
					(lane) * 0x200 + (offset))

#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
#define   DPIO_FRC_LATENCY_SHFIT	8
#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
#define   DPIO_UPAR_SHIFT		30

/* BXT PHY registers */
#define _BXT_PHY0_BASE			0x6C000
#define _BXT_PHY1_BASE			0x162000
#define _BXT_PHY2_BASE			0x163000
#define BXT_PHY_BASE(phy)		_PHY3((phy), _BXT_PHY0_BASE, \
						     _BXT_PHY1_BASE, \
						     _BXT_PHY2_BASE)

#define _BXT_PHY(phy, reg)						\
	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))

#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
	(BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE,	\
					 (reg_ch1) - _BXT_PHY0_BASE))
#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
	_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))

#define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
#define  MIPIO_RST_CTRL				(1 << 2)

#define _BXT_PHY_CTL_DDI_A		0x64C00
#define _BXT_PHY_CTL_DDI_B		0x64C10
#define _BXT_PHY_CTL_DDI_C		0x64C20
#define   BXT_PHY_CMNLANE_POWERDOWN_ACK	(1 << 10)
#define   BXT_PHY_LANE_POWERDOWN_ACK	(1 << 9)
#define   BXT_PHY_LANE_ENABLED		(1 << 8)
#define BXT_PHY_CTL(port)		_MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
							 _BXT_PHY_CTL_DDI_B)

#define _PHY_CTL_FAMILY_EDP		0x64C80
#define _PHY_CTL_FAMILY_DDI		0x64C90
#define _PHY_CTL_FAMILY_DDI_C		0x64CA0
#define   COMMON_RESET_DIS		(1 << 31)
#define BXT_PHY_CTL_FAMILY(phy)		_MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
							  _PHY_CTL_FAMILY_EDP, \
							  _PHY_CTL_FAMILY_DDI_C)

/* BXT PHY PLL registers */
#define _PORT_PLL_A			0x46074
#define _PORT_PLL_B			0x46078
#define _PORT_PLL_C			0x4607c
#define   PORT_PLL_ENABLE		(1 << 31)
#define   PORT_PLL_LOCK			(1 << 30)
#define   PORT_PLL_REF_SEL		(1 << 27)
#define   PORT_PLL_POWER_ENABLE		(1 << 26)
#define   PORT_PLL_POWER_STATE		(1 << 25)
#define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)

#define _PORT_PLL_EBB_0_A		0x162034
#define _PORT_PLL_EBB_0_B		0x6C034
#define _PORT_PLL_EBB_0_C		0x6C340
#define   PORT_PLL_P1_SHIFT		13
#define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
#define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
#define   PORT_PLL_P2_SHIFT		8
#define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
#define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
#define BXT_PORT_PLL_EBB_0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_PLL_EBB_0_B, \
							 _PORT_PLL_EBB_0_C)

#define _PORT_PLL_EBB_4_A		0x162038
#define _PORT_PLL_EBB_4_B		0x6C038
#define _PORT_PLL_EBB_4_C		0x6C344
#define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
#define   PORT_PLL_RECALIBRATE		(1 << 14)
#define BXT_PORT_PLL_EBB_4(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_PLL_EBB_4_B, \
							 _PORT_PLL_EBB_4_C)

#define _PORT_PLL_0_A			0x162100
#define _PORT_PLL_0_B			0x6C100
#define _PORT_PLL_0_C			0x6C380
/* PORT_PLL_0_A */
#define   PORT_PLL_M2_MASK		0xFF
/* PORT_PLL_1_A */
#define   PORT_PLL_N_SHIFT		8
#define   PORT_PLL_N_MASK		(0x0F << PORT_PLL_N_SHIFT)
#define   PORT_PLL_N(x)			((x) << PORT_PLL_N_SHIFT)
/* PORT_PLL_2_A */
#define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
/* PORT_PLL_3_A */
#define   PORT_PLL_M2_FRAC_ENABLE	(1 << 16)
/* PORT_PLL_6_A */
#define   PORT_PLL_PROP_COEFF_MASK	0xF
#define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
#define   PORT_PLL_INT_COEFF(x)		((x)  << 8)
#define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
#define   PORT_PLL_GAIN_CTL(x)		((x)  << 16)
/* PORT_PLL_8_A */
#define   PORT_PLL_TARGET_CNT_MASK	0x3FF
/* PORT_PLL_9_A */
#define  PORT_PLL_LOCK_THRESHOLD_SHIFT	1
#define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
/* PORT_PLL_10_A */
#define  PORT_PLL_DCO_AMP_OVR_EN_H	(1<<27)
#define  PORT_PLL_DCO_AMP_DEFAULT	15
#define  PORT_PLL_DCO_AMP_MASK		0x3c00
#define  PORT_PLL_DCO_AMP(x)		((x)<<10)
#define _PORT_PLL_BASE(phy, ch)		_BXT_PHY_CH(phy, ch, \
						    _PORT_PLL_0_B, \
						    _PORT_PLL_0_C)
#define BXT_PORT_PLL(phy, ch, idx)	_MMIO(_PORT_PLL_BASE(phy, ch) + \
					      (idx) * 4)

/* BXT PHY common lane registers */
#define _PORT_CL1CM_DW0_A		0x162000
#define _PORT_CL1CM_DW0_BC		0x6C000
#define   PHY_POWER_GOOD		(1 << 16)
#define   PHY_RESERVED			(1 << 7)
#define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)

#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
#define   CL_POWER_DOWN_ENABLE		(1 << 4)
#define   SUS_CLOCK_CONFIG		(3 << 0)

#define _PORT_CL1CM_DW9_A		0x162024
#define _PORT_CL1CM_DW9_BC		0x6C024
#define   IREF0RC_OFFSET_SHIFT		8
#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)

#define _PORT_CL1CM_DW10_A		0x162028
#define _PORT_CL1CM_DW10_BC		0x6C028
#define   IREF1RC_OFFSET_SHIFT		8
#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)

#define _PORT_CL1CM_DW28_A		0x162070
#define _PORT_CL1CM_DW28_BC		0x6C070
#define   OCL1_POWER_DOWN_EN		(1 << 23)
#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
#define   SUS_CLK_CONFIG		0x3
#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)

#define _PORT_CL1CM_DW30_A		0x162078
#define _PORT_CL1CM_DW30_BC		0x6C078
#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)

#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
						    _CNL_PORT_PCS_DW1_GRP_AE, \
						    _CNL_PORT_PCS_DW1_GRP_B, \
						    _CNL_PORT_PCS_DW1_GRP_C, \
						    _CNL_PORT_PCS_DW1_GRP_D, \
						    _CNL_PORT_PCS_DW1_GRP_AE, \
						    _CNL_PORT_PCS_DW1_GRP_F)
#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
						    _CNL_PORT_PCS_DW1_LN0_AE, \
						    _CNL_PORT_PCS_DW1_LN0_B, \
						    _CNL_PORT_PCS_DW1_LN0_C, \
						    _CNL_PORT_PCS_DW1_LN0_D, \
						    _CNL_PORT_PCS_DW1_LN0_AE, \
						    _CNL_PORT_PCS_DW1_LN0_F)
#define   COMMON_KEEPER_EN		(1 << 26)

#define _CNL_PORT_TX_DW2_GRP_AE		0x162348
#define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
#define _CNL_PORT_TX_DW2_GRP_C		0x162B48
#define _CNL_PORT_TX_DW2_GRP_D		0x162BC8
#define _CNL_PORT_TX_DW2_GRP_F		0x162A48
#define _CNL_PORT_TX_DW2_LN0_AE		0x162448
#define _CNL_PORT_TX_DW2_LN0_B		0x162648
#define _CNL_PORT_TX_DW2_LN0_C		0x162C48
#define _CNL_PORT_TX_DW2_LN0_D		0x162E48
#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
#define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
						    _CNL_PORT_TX_DW2_GRP_AE, \
						    _CNL_PORT_TX_DW2_GRP_B, \
						    _CNL_PORT_TX_DW2_GRP_C, \
						    _CNL_PORT_TX_DW2_GRP_D, \
						    _CNL_PORT_TX_DW2_GRP_AE, \
						    _CNL_PORT_TX_DW2_GRP_F)
#define CNL_PORT_TX_DW2_LN0(port)	_MMIO_PORT6(port, \
						    _CNL_PORT_TX_DW2_LN0_AE, \
						    _CNL_PORT_TX_DW2_LN0_B, \
						    _CNL_PORT_TX_DW2_LN0_C, \
						    _CNL_PORT_TX_DW2_LN0_D, \
						    _CNL_PORT_TX_DW2_LN0_AE, \
						    _CNL_PORT_TX_DW2_LN0_F)
#define   SWING_SEL_UPPER(x)		((x >> 3) << 15)
#define   SWING_SEL_UPPER_MASK		(1 << 15)
#define   SWING_SEL_LOWER(x)		((x & 0x7) << 11)
#define   SWING_SEL_LOWER_MASK		(0x7 << 11)
#define   RCOMP_SCALAR(x)		((x) << 0)
#define   RCOMP_SCALAR_MASK		(0xFF << 0)

#define _CNL_PORT_TX_DW4_GRP_AE		0x162350
#define _CNL_PORT_TX_DW4_GRP_B		0x1623D0
#define _CNL_PORT_TX_DW4_GRP_C		0x162B50
#define _CNL_PORT_TX_DW4_GRP_D		0x162BD0
#define _CNL_PORT_TX_DW4_GRP_F		0x162A50
#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
#define _CNL_PORT_TX_DW4_LN0_B		0x162650
#define _CNL_PORT_TX_DW4_LN0_C		0x162C50
#define _CNL_PORT_TX_DW4_LN0_D		0x162E50
#define _CNL_PORT_TX_DW4_LN0_F		0x162850
#define CNL_PORT_TX_DW4_GRP(port)       _MMIO_PORT6(port, \
						    _CNL_PORT_TX_DW4_GRP_AE, \
						    _CNL_PORT_TX_DW4_GRP_B, \
						    _CNL_PORT_TX_DW4_GRP_C, \
						    _CNL_PORT_TX_DW4_GRP_D, \
						    _CNL_PORT_TX_DW4_GRP_AE, \
						    _CNL_PORT_TX_DW4_GRP_F)
#define CNL_PORT_TX_DW4_LN(port, ln)       _MMIO_PORT6_LN(port, ln,	\
						    _CNL_PORT_TX_DW4_LN0_AE, \
						    _CNL_PORT_TX_DW4_LN1_AE, \
						    _CNL_PORT_TX_DW4_LN0_B, \
						    _CNL_PORT_TX_DW4_LN0_C, \
						    _CNL_PORT_TX_DW4_LN0_D, \
						    _CNL_PORT_TX_DW4_LN0_AE, \
						    _CNL_PORT_TX_DW4_LN0_F)
#define   LOADGEN_SELECT		(1 << 31)
#define   POST_CURSOR_1(x)		((x) << 12)
#define   POST_CURSOR_1_MASK		(0x3F << 12)
#define   POST_CURSOR_2(x)		((x) << 6)
#define   POST_CURSOR_2_MASK		(0x3F << 6)
#define   CURSOR_COEFF(x)		((x) << 0)
#define   CURSOR_COEFF_MASK		(0x3F << 0)

#define _CNL_PORT_TX_DW5_GRP_AE		0x162354
#define _CNL_PORT_TX_DW5_GRP_B		0x1623D4
#define _CNL_PORT_TX_DW5_GRP_C		0x162B54
#define _CNL_PORT_TX_DW5_GRP_D		0x162BD4
#define _CNL_PORT_TX_DW5_GRP_F		0x162A54
#define _CNL_PORT_TX_DW5_LN0_AE		0x162454
#define _CNL_PORT_TX_DW5_LN0_B		0x162654
#define _CNL_PORT_TX_DW5_LN0_C		0x162C54
#define _CNL_PORT_TX_DW5_LN0_D		0x162ED4
#define _CNL_PORT_TX_DW5_LN0_F		0x162854
#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \
						    _CNL_PORT_TX_DW5_GRP_AE, \
						    _CNL_PORT_TX_DW5_GRP_B, \
						    _CNL_PORT_TX_DW5_GRP_C, \
						    _CNL_PORT_TX_DW5_GRP_D, \
						    _CNL_PORT_TX_DW5_GRP_AE, \
						    _CNL_PORT_TX_DW5_GRP_F)
#define CNL_PORT_TX_DW5_LN0(port)	_MMIO_PORT6(port, \
						    _CNL_PORT_TX_DW5_LN0_AE, \
						    _CNL_PORT_TX_DW5_LN0_B, \
						    _CNL_PORT_TX_DW5_LN0_C, \
						    _CNL_PORT_TX_DW5_LN0_D, \
						    _CNL_PORT_TX_DW5_LN0_AE, \
						    _CNL_PORT_TX_DW5_LN0_F)
#define   TX_TRAINING_EN		(1 << 31)
#define   TAP3_DISABLE			(1 << 29)
#define   SCALING_MODE_SEL(x)		((x) << 18)
#define   SCALING_MODE_SEL_MASK		(0x7 << 18)
#define   RTERM_SELECT(x)		((x) << 3)
#define   RTERM_SELECT_MASK		(0x7 << 3)

#define _CNL_PORT_TX_DW7_GRP_AE		0x16235C
#define _CNL_PORT_TX_DW7_GRP_B		0x1623DC
#define _CNL_PORT_TX_DW7_GRP_C		0x162B5C
#define _CNL_PORT_TX_DW7_GRP_D		0x162BDC
#define _CNL_PORT_TX_DW7_GRP_F		0x162A5C
#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C
#define _CNL_PORT_TX_DW7_LN0_B		0x16265C
#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C
#define _CNL_PORT_TX_DW7_LN0_D		0x162EDC
#define _CNL_PORT_TX_DW7_LN0_F		0x16285C
#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \
						    _CNL_PORT_TX_DW7_GRP_AE, \
						    _CNL_PORT_TX_DW7_GRP_B, \
						    _CNL_PORT_TX_DW7_GRP_C, \
						    _CNL_PORT_TX_DW7_GRP_D, \
						    _CNL_PORT_TX_DW7_GRP_AE, \
						    _CNL_PORT_TX_DW7_GRP_F)
#define CNL_PORT_TX_DW7_LN0(port)	_MMIO_PORT6(port, \
						    _CNL_PORT_TX_DW7_LN0_AE, \
						    _CNL_PORT_TX_DW7_LN0_B, \
						    _CNL_PORT_TX_DW7_LN0_C, \
						    _CNL_PORT_TX_DW7_LN0_D, \
						    _CNL_PORT_TX_DW7_LN0_AE, \
						    _CNL_PORT_TX_DW7_LN0_F)
#define   N_SCALAR(x)			((x) << 24)
#define   N_SCALAR_MASK			(0x7F << 24)

/* The spec defines this only for BXT PHY0, but lets assume that this
 * would exist for PHY1 too if it had a second channel.
 */
#define _PORT_CL2CM_DW6_A		0x162358
#define _PORT_CL2CM_DW6_BC		0x6C358
#define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
#define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)

#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
#define   COMP_INIT			(1 << 31)
#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
#define   PROCESS_INFO_DOT_0		(0 << 26)
#define   PROCESS_INFO_DOT_1		(1 << 26)
#define   PROCESS_INFO_DOT_4		(2 << 26)
#define   PROCESS_INFO_MASK		(7 << 26)
#define   PROCESS_INFO_SHIFT		26
#define   VOLTAGE_INFO_0_85V		(0 << 24)
#define   VOLTAGE_INFO_0_95V		(1 << 24)
#define   VOLTAGE_INFO_1_05V		(2 << 24)
#define   VOLTAGE_INFO_MASK		(3 << 24)
#define   VOLTAGE_INFO_SHIFT		24
#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
#define CNL_PORT_COMP_DW10		_MMIO(0x162128)

/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A			0x16218C
#define _PORT_REF_DW3_BC		0x6C18C
#define   GRC_DONE			(1 << 22)
#define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC)

#define _PORT_REF_DW6_A			0x162198
#define _PORT_REF_DW6_BC		0x6C198
#define   GRC_CODE_SHIFT		24
#define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
#define   GRC_CODE_FAST_SHIFT		16
#define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
#define   GRC_CODE_SLOW_SHIFT		8
#define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
#define   GRC_CODE_NOM_MASK		0xFF
#define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC)

#define _PORT_REF_DW8_A			0x1621A0
#define _PORT_REF_DW8_BC		0x6C1A0
#define   GRC_DIS			(1 << 15)
#define   GRC_RDY_OVRD			(1 << 1)
#define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC)

/* BXT PHY PCS registers */
#define _PORT_PCS_DW10_LN01_A		0x162428
#define _PORT_PCS_DW10_LN01_B		0x6C428
#define _PORT_PCS_DW10_LN01_C		0x6C828
#define _PORT_PCS_DW10_GRP_A		0x162C28
#define _PORT_PCS_DW10_GRP_B		0x6CC28
#define _PORT_PCS_DW10_GRP_C		0x6CE28
#define BXT_PORT_PCS_DW10_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_PCS_DW10_LN01_B, \
							 _PORT_PCS_DW10_LN01_C)
#define BXT_PORT_PCS_DW10_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_PCS_DW10_GRP_B, \
							 _PORT_PCS_DW10_GRP_C)

#define   TX2_SWING_CALC_INIT		(1 << 31)
#define   TX1_SWING_CALC_INIT		(1 << 30)

#define _PORT_PCS_DW12_LN01_A		0x162430
#define _PORT_PCS_DW12_LN01_B		0x6C430
#define _PORT_PCS_DW12_LN01_C		0x6C830
#define _PORT_PCS_DW12_LN23_A		0x162630
#define _PORT_PCS_DW12_LN23_B		0x6C630
#define _PORT_PCS_DW12_LN23_C		0x6CA30
#define _PORT_PCS_DW12_GRP_A		0x162c30
#define _PORT_PCS_DW12_GRP_B		0x6CC30
#define _PORT_PCS_DW12_GRP_C		0x6CE30
#define   LANESTAGGER_STRAP_OVRD	(1 << 6)
#define   LANE_STAGGER_MASK		0x1F
#define BXT_PORT_PCS_DW12_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_PCS_DW12_LN01_B, \
							 _PORT_PCS_DW12_LN01_C)
#define BXT_PORT_PCS_DW12_LN23(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_PCS_DW12_LN23_B, \
							 _PORT_PCS_DW12_LN23_C)
#define BXT_PORT_PCS_DW12_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_PCS_DW12_GRP_B, \
							 _PORT_PCS_DW12_GRP_C)

/* BXT PHY TX registers */
#define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
					  ((lane) & 1) * 0x80)

#define _PORT_TX_DW2_LN0_A		0x162508
#define _PORT_TX_DW2_LN0_B		0x6C508
#define _PORT_TX_DW2_LN0_C		0x6C908
#define _PORT_TX_DW2_GRP_A		0x162D08
#define _PORT_TX_DW2_GRP_B		0x6CD08
#define _PORT_TX_DW2_GRP_C		0x6CF08
#define BXT_PORT_TX_DW2_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_TX_DW2_LN0_B, \
							 _PORT_TX_DW2_LN0_C)
#define BXT_PORT_TX_DW2_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_TX_DW2_GRP_B, \
							 _PORT_TX_DW2_GRP_C)
#define   MARGIN_000_SHIFT		16
#define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
#define   UNIQ_TRANS_SCALE_SHIFT	8
#define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)

#define _PORT_TX_DW3_LN0_A		0x16250C
#define _PORT_TX_DW3_LN0_B		0x6C50C
#define _PORT_TX_DW3_LN0_C		0x6C90C
#define _PORT_TX_DW3_GRP_A		0x162D0C
#define _PORT_TX_DW3_GRP_B		0x6CD0C
#define _PORT_TX_DW3_GRP_C		0x6CF0C
#define BXT_PORT_TX_DW3_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_TX_DW3_LN0_B, \
							 _PORT_TX_DW3_LN0_C)
#define BXT_PORT_TX_DW3_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_TX_DW3_GRP_B, \
							 _PORT_TX_DW3_GRP_C)
#define   SCALE_DCOMP_METHOD		(1 << 26)
#define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)

#define _PORT_TX_DW4_LN0_A		0x162510
#define _PORT_TX_DW4_LN0_B		0x6C510
#define _PORT_TX_DW4_LN0_C		0x6C910
#define _PORT_TX_DW4_GRP_A		0x162D10
#define _PORT_TX_DW4_GRP_B		0x6CD10
#define _PORT_TX_DW4_GRP_C		0x6CF10
#define BXT_PORT_TX_DW4_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_TX_DW4_LN0_B, \
							 _PORT_TX_DW4_LN0_C)
#define BXT_PORT_TX_DW4_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_TX_DW4_GRP_B, \
							 _PORT_TX_DW4_GRP_C)
#define   DEEMPH_SHIFT			24
#define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)

#define _PORT_TX_DW5_LN0_A		0x162514
#define _PORT_TX_DW5_LN0_B		0x6C514
#define _PORT_TX_DW5_LN0_C		0x6C914
#define _PORT_TX_DW5_GRP_A		0x162D14
#define _PORT_TX_DW5_GRP_B		0x6CD14
#define _PORT_TX_DW5_GRP_C		0x6CF14
#define BXT_PORT_TX_DW5_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_TX_DW5_LN0_B, \
							 _PORT_TX_DW5_LN0_C)
#define BXT_PORT_TX_DW5_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
							 _PORT_TX_DW5_GRP_B, \
							 _PORT_TX_DW5_GRP_C)
#define   DCC_DELAY_RANGE_1		(1 << 9)
#define   DCC_DELAY_RANGE_2		(1 << 8)

#define _PORT_TX_DW14_LN0_A		0x162538
#define _PORT_TX_DW14_LN0_B		0x6C538
#define _PORT_TX_DW14_LN0_C		0x6C938
#define   LATENCY_OPTIM_SHIFT		30
#define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
#define BXT_PORT_TX_DW14_LN(phy, ch, lane)				\
	_MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B,			\
				   _PORT_TX_DW14_LN0_C) +		\
	      _BXT_LANE_OFFSET(lane))

/* UAIMI scratch pad register 1 */
#define UAIMI_SPR1			_MMIO(0x4F074)
/* SKL VccIO mask */
#define SKL_VCCIO_MASK			0x1
/* SKL balance leg register */
#define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
/* I_boost values */
#define BALANCE_LEG_SHIFT(port)		(8+3*(port))
#define BALANCE_LEG_MASK(port)		(7<<(8+3*(port)))
/* Balance leg disable bits */
#define BALANCE_LEG_DISABLE_SHIFT	23
#define BALANCE_LEG_DISABLE(port)	(1 << (23 + (port)))

/*
 * Fence registers
 * [0-7]  @ 0x2000 gen2,gen3
 * [8-15] @ 0x3000 945,g33,pnv
 *
 * [0-15] @ 0x3000 gen4,gen5
 *
 * [0-15] @ 0x100000 gen6,vlv,chv
 * [0-31] @ 0x100000 gen7+
 */
#define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
#define   I830_FENCE_START_MASK		0x07f80000
#define   I830_FENCE_TILING_Y_SHIFT	12
#define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
#define   I830_FENCE_PITCH_SHIFT	4
#define   I830_FENCE_REG_VALID		(1<<0)
#define   I915_FENCE_MAX_PITCH_VAL	4
#define   I830_FENCE_MAX_PITCH_VAL	6
#define   I830_FENCE_MAX_SIZE_VAL	(1<<8)

#define   I915_FENCE_START_MASK		0x0ff00000
#define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)

#define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
#define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
#define   I965_FENCE_PITCH_SHIFT	2
#define   I965_FENCE_TILING_Y_SHIFT	1
#define   I965_FENCE_REG_VALID		(1<<0)
#define   I965_FENCE_MAX_PITCH_VAL	0x0400

#define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
#define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
#define   GEN6_FENCE_PITCH_SHIFT	32
#define   GEN7_FENCE_MAX_PITCH_VAL	0x0800


/* control register for cpu gtt access */
#define TILECTL				_MMIO(0x101000)
#define   TILECTL_SWZCTL			(1 << 0)
#define   TILECTL_TLBPF			(1 << 1)
#define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
#define   TILECTL_BACKSNOOP_DIS		(1 << 3)

/*
 * Instruction and interrupt control regs
 */
#define PGTBL_CTL	_MMIO(0x02020)
#define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
#define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
#define PGTBL_ER	_MMIO(0x02024)
#define PRB0_BASE	(0x2030-0x30)
#define PRB1_BASE	(0x2040-0x30) /* 830,gen3 */
#define PRB2_BASE	(0x2050-0x30) /* gen3 */
#define SRB0_BASE	(0x2100-0x30) /* gen2 */
#define SRB1_BASE	(0x2110-0x30) /* gen2 */
#define SRB2_BASE	(0x2120-0x30) /* 830 */
#define SRB3_BASE	(0x2130-0x30) /* 830 */
#define RENDER_RING_BASE	0x02000
#define BSD_RING_BASE		0x04000
#define GEN6_BSD_RING_BASE	0x12000
#define GEN8_BSD2_RING_BASE	0x1c000
#define VEBOX_RING_BASE		0x1a000
#define BLT_RING_BASE		0x22000
#define RING_TAIL(base)		_MMIO((base)+0x30)
#define RING_HEAD(base)		_MMIO((base)+0x34)
#define RING_START(base)	_MMIO((base)+0x38)
#define RING_CTL(base)		_MMIO((base)+0x3c)
#define   RING_CTL_SIZE(size)	((size) - PAGE_SIZE) /* in bytes -> pages */
#define RING_SYNC_0(base)	_MMIO((base)+0x40)
#define RING_SYNC_1(base)	_MMIO((base)+0x44)
#define RING_SYNC_2(base)	_MMIO((base)+0x48)
#define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
#define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
#define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
#define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
#define GEN6_VRSYNC	(RING_SYNC_1(GEN6_BSD_RING_BASE))
#define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
#define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
#define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
#define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
#define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
#define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
#define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
#define GEN6_NOSYNC	INVALID_MMIO_REG
#define RING_PSMI_CTL(base)	_MMIO((base)+0x50)
#define RING_MAX_IDLE(base)	_MMIO((base)+0x54)
#define RING_HWS_PGA(base)	_MMIO((base)+0x80)
#define RING_HWS_PGA_GEN6(base)	_MMIO((base)+0x2080)
#define RING_RESET_CTL(base)	_MMIO((base)+0xd0)
#define   RESET_CTL_REQUEST_RESET  (1 << 0)
#define   RESET_CTL_READY_TO_RESET (1 << 1)

#define HSW_GTT_CACHE_EN	_MMIO(0x4024)
#define   GTT_CACHE_EN_ALL	0xF0007FFF
#define GEN7_WR_WATERMARK	_MMIO(0x4028)
#define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
#define ARB_MODE		_MMIO(0x4030)
#define   ARB_MODE_SWIZZLE_SNB	(1<<4)
#define   ARB_MODE_SWIZZLE_IVB	(1<<5)
#define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
#define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
#define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
#define GEN7_LRA_LIMITS_REG_NUM	13
#define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
#define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)

#define GAMTARBMODE		_MMIO(0x04a08)
#define   ARB_MODE_BWGTLB_DISABLE (1<<9)
#define   ARB_MODE_SWIZZLE_BDW	(1<<1)
#define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
#define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100*(engine)->hw_id)
#define   RING_FAULT_GTTSEL_MASK (1<<11)
#define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
#define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
#define   RING_FAULT_VALID	(1<<0)
#define DONE_REG		_MMIO(0x40b0)
#define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
#define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
#define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + index*4)
#define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
#define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
#define RING_ACTHD(base)	_MMIO((base)+0x74)
#define RING_ACTHD_UDW(base)	_MMIO((base)+0x5c)
#define RING_NOPID(base)	_MMIO((base)+0x94)
#define RING_IMR(base)		_MMIO((base)+0xa8)
#define RING_HWSTAM(base)	_MMIO((base)+0x98)
#define RING_TIMESTAMP(base)		_MMIO((base)+0x358)
#define RING_TIMESTAMP_UDW(base)	_MMIO((base)+0x358 + 4)
#define   TAIL_ADDR		0x001FFFF8
#define   HEAD_WRAP_COUNT	0xFFE00000
#define   HEAD_WRAP_ONE		0x00200000
#define   HEAD_ADDR		0x001FFFFC
#define   RING_NR_PAGES		0x001FF000
#define   RING_REPORT_MASK	0x00000006
#define   RING_REPORT_64K	0x00000002
#define   RING_REPORT_128K	0x00000004
#define   RING_NO_REPORT	0x00000000
#define   RING_VALID_MASK	0x00000001
#define   RING_VALID		0x00000001
#define   RING_INVALID		0x00000000
#define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
#define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
#define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */

#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4)
#define   RING_MAX_NONPRIV_SLOTS  12

#define GEN7_TLB_RD_ADDR	_MMIO(0x4700)

#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
#define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS	(1<<18)

#define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
#define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1<<28)

#if 0
#define PRB0_TAIL	_MMIO(0x2030)
#define PRB0_HEAD	_MMIO(0x2034)
#define PRB0_START	_MMIO(0x2038)
#define PRB0_CTL	_MMIO(0x203c)
#define PRB1_TAIL	_MMIO(0x2040) /* 915+ only */
#define PRB1_HEAD	_MMIO(0x2044) /* 915+ only */
#define PRB1_START	_MMIO(0x2048) /* 915+ only */
#define PRB1_CTL	_MMIO(0x204c) /* 915+ only */
#endif
#define IPEIR_I965	_MMIO(0x2064)
#define IPEHR_I965	_MMIO(0x2068)
#define GEN7_SC_INSTDONE	_MMIO(0x7100)
#define GEN7_SAMPLER_INSTDONE	_MMIO(0xe160)
#define GEN7_ROW_INSTDONE	_MMIO(0xe164)
#define GEN8_MCR_SELECTOR		_MMIO(0xfdc)
#define   GEN8_MCR_SLICE(slice)		(((slice) & 3) << 26)
#define   GEN8_MCR_SLICE_MASK		GEN8_MCR_SLICE(3)
#define   GEN8_MCR_SUBSLICE(subslice)	(((subslice) & 3) << 24)
#define   GEN8_MCR_SUBSLICE_MASK	GEN8_MCR_SUBSLICE(3)
#define RING_IPEIR(base)	_MMIO((base)+0x64)
#define RING_IPEHR(base)	_MMIO((base)+0x68)
/*
 * On GEN4, only the render ring INSTDONE exists and has a different
 * layout than the GEN7+ version.
 * The GEN2 counterpart of this register is GEN2_INSTDONE.
 */
#define RING_INSTDONE(base)	_MMIO((base)+0x6c)
#define RING_INSTPS(base)	_MMIO((base)+0x70)
#define RING_DMA_FADD(base)	_MMIO((base)+0x78)
#define RING_DMA_FADD_UDW(base)	_MMIO((base)+0x60) /* gen8+ */
#define RING_INSTPM(base)	_MMIO((base)+0xc0)
#define RING_MI_MODE(base)	_MMIO((base)+0x9c)
#define INSTPS		_MMIO(0x2070) /* 965+ only */
#define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
#define ACTHD_I965	_MMIO(0x2074)
#define HWS_PGA		_MMIO(0x2080)
#define HWS_ADDRESS_MASK	0xfffff000
#define HWS_START_ADDRESS_SHIFT	4
#define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */
#define   PWRCTX_EN	(1<<0)
#define IPEIR		_MMIO(0x2088)
#define IPEHR		_MMIO(0x208c)
#define GEN2_INSTDONE	_MMIO(0x2090)
#define NOPID		_MMIO(0x2094)
#define HWSTAM		_MMIO(0x2098)
#define DMA_FADD_I8XX	_MMIO(0x20d0)
#define RING_BBSTATE(base)	_MMIO((base)+0x110)
#define   RING_BB_PPGTT		(1 << 5)
#define RING_SBBADDR(base)	_MMIO((base)+0x114) /* hsw+ */
#define RING_SBBSTATE(base)	_MMIO((base)+0x118) /* hsw+ */
#define RING_SBBADDR_UDW(base)	_MMIO((base)+0x11c) /* gen8+ */
#define RING_BBADDR(base)	_MMIO((base)+0x140)
#define RING_BBADDR_UDW(base)	_MMIO((base)+0x168) /* gen8+ */
#define RING_BB_PER_CTX_PTR(base)	_MMIO((base)+0x1c0) /* gen8+ */
#define RING_INDIRECT_CTX(base)		_MMIO((base)+0x1c4) /* gen8+ */
#define RING_INDIRECT_CTX_OFFSET(base)	_MMIO((base)+0x1c8) /* gen8+ */
#define RING_CTX_TIMESTAMP(base)	_MMIO((base)+0x3a8) /* gen8+ */

#define ERROR_GEN6	_MMIO(0x40a0)
#define GEN7_ERR_INT	_MMIO(0x44040)
#define   ERR_INT_POISON		(1<<31)
#define   ERR_INT_MMIO_UNCLAIMED	(1<<13)
#define   ERR_INT_PIPE_CRC_DONE_C	(1<<8)
#define   ERR_INT_FIFO_UNDERRUN_C	(1<<6)
#define   ERR_INT_PIPE_CRC_DONE_B	(1<<5)
#define   ERR_INT_FIFO_UNDERRUN_B	(1<<3)
#define   ERR_INT_PIPE_CRC_DONE_A	(1<<2)
#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1<<(2 + (pipe)*3))
#define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1<<((pipe)*3))

#define GEN8_FAULT_TLB_DATA0		_MMIO(0x4b10)
#define GEN8_FAULT_TLB_DATA1		_MMIO(0x4b14)

#define FPGA_DBG		_MMIO(0x42300)
#define   FPGA_DBG_RM_NOCLAIM	(1<<31)

#define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
#define   CLAIM_ER_CLR		(1 << 31)
#define   CLAIM_ER_OVERFLOW	(1 << 16)
#define   CLAIM_ER_CTR_MASK	0xffff

#define DERRMR		_MMIO(0x44050)
/* Note that HBLANK events are reserved on bdw+ */
#define   DERRMR_PIPEA_SCANLINE		(1<<0)
#define   DERRMR_PIPEA_PRI_FLIP_DONE	(1<<1)
#define   DERRMR_PIPEA_SPR_FLIP_DONE	(1<<2)
#define   DERRMR_PIPEA_VBLANK		(1<<3)
#define   DERRMR_PIPEA_HBLANK		(1<<5)
#define   DERRMR_PIPEB_SCANLINE 	(1<<8)
#define   DERRMR_PIPEB_PRI_FLIP_DONE	(1<<9)
#define   DERRMR_PIPEB_SPR_FLIP_DONE	(1<<10)
#define   DERRMR_PIPEB_VBLANK		(1<<11)
#define   DERRMR_PIPEB_HBLANK		(1<<13)
/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
#define   DERRMR_PIPEC_SCANLINE		(1<<14)
#define   DERRMR_PIPEC_PRI_FLIP_DONE	(1<<15)
#define   DERRMR_PIPEC_SPR_FLIP_DONE	(1<<20)
#define   DERRMR_PIPEC_VBLANK		(1<<21)
#define   DERRMR_PIPEC_HBLANK		(1<<22)


/* GM45+ chicken bits -- debug workaround bits that may be required
 * for various sorts of correct behavior.  The top 16 bits of each are
 * the enables for writing to the corresponding low bit.
 */
#define _3D_CHICKEN	_MMIO(0x2084)
#define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
#define _3D_CHICKEN2	_MMIO(0x208c)
/* Disables pipelining of read flushes past the SF-WIZ interface.
 * Required on all Ironlake steppings according to the B-Spec, but the
 * particular danger of not doing so is not specified.
 */
# define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
#define _3D_CHICKEN3	_MMIO(0x2090)
#define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
#define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
#define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1) /* gen8+ */
#define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */

#define MI_MODE		_MMIO(0x209c)
# define VS_TIMER_DISPATCH				(1 << 6)
# define MI_FLUSH_ENABLE				(1 << 12)
# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
# define MODE_IDLE					(1 << 9)
# define STOP_RING					(1 << 8)

#define GEN6_GT_MODE	_MMIO(0x20d0)
#define GEN7_GT_MODE	_MMIO(0x7008)
#define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
#define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
#define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
#define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
#define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
#define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
#define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))

/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
#define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)

/* WaClearTdlStateAckDirtyBits */
#define GEN8_STATE_ACK		_MMIO(0x20F0)
#define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
#define GEN9_STATE_ACK_SLICE2	_MMIO(0x2100)
#define   GEN9_STATE_ACK_TDL0 (1 << 12)
#define   GEN9_STATE_ACK_TDL1 (1 << 13)
#define   GEN9_STATE_ACK_TDL2 (1 << 14)
#define   GEN9_STATE_ACK_TDL3 (1 << 15)
#define   GEN9_SUBSLICE_TDL_ACK_BITS \
	(GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
	 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)

#define GFX_MODE	_MMIO(0x2520)
#define GFX_MODE_GEN7	_MMIO(0x229c)
#define RING_MODE_GEN7(engine)	_MMIO((engine)->mmio_base+0x29c)
#define   GFX_RUN_LIST_ENABLE		(1<<15)
#define   GFX_INTERRUPT_STEERING	(1<<14)
#define   GFX_TLB_INVALIDATE_EXPLICIT	(1<<13)
#define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
#define   GFX_REPLAY_MODE		(1<<11)
#define   GFX_PSMI_GRANULARITY		(1<<10)
#define   GFX_PPGTT_ENABLE		(1<<9)
#define   GEN8_GFX_PPGTT_48B		(1<<7)

#define   GFX_FORWARD_VBLANK_MASK	(3<<5)
#define   GFX_FORWARD_VBLANK_NEVER	(0<<5)
#define   GFX_FORWARD_VBLANK_ALWAYS	(1<<5)
#define   GFX_FORWARD_VBLANK_COND	(2<<5)

#define VLV_DISPLAY_BASE 0x180000
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
#define BXT_MIPI_BASE 0x60000

#define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
#define SCPD0		_MMIO(0x209c) /* 915+ only */
#define IER		_MMIO(0x20a0)
#define IIR		_MMIO(0x20a4)
#define IMR		_MMIO(0x20a8)
#define ISR		_MMIO(0x20ac)
#define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
#define   GINT_DIS		(1<<22)
#define   GCFG_DIS		(1<<8)
#define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
#define VLV_PCBR_ADDR_SHIFT	12

#define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
#define EIR		_MMIO(0x20b0)
#define EMR		_MMIO(0x20b4)
#define ESR		_MMIO(0x20b8)
#define   GM45_ERROR_PAGE_TABLE				(1<<5)
#define   GM45_ERROR_MEM_PRIV				(1<<4)
#define   I915_ERROR_PAGE_TABLE				(1<<4)
#define   GM45_ERROR_CP_PRIV				(1<<3)
#define   I915_ERROR_MEMORY_REFRESH			(1<<1)
#define   I915_ERROR_INSTRUCTION			(1<<0)
#define INSTPM	        _MMIO(0x20c0)
#define   INSTPM_SELF_EN (1<<12) /* 915GM only */
#define   INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
					will not assert AGPBUSY# and will only
					be delivered when out of C3. */
#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
#define   INSTPM_TLB_INVALIDATE	(1<<9)
#define   INSTPM_SYNC_FLUSH	(1<<5)
#define ACTHD	        _MMIO(0x20c8)
#define MEM_MODE	_MMIO(0x20cc)
#define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
#define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
#define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
#define FW_BLC		_MMIO(0x20d8)
#define FW_BLC2		_MMIO(0x20dc)
#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
#define   FW_BLC_SELF_EN_MASK      (1<<31)
#define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
#define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
#define MM_BURST_LENGTH     0x00700000
#define MM_FIFO_WATERMARK   0x0001F000
#define LM_BURST_LENGTH     0x00000700
#define LM_FIFO_WATERMARK   0x0000001F
#define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */

/* Make render/texture TLB fetches lower priorty than associated data
 *   fetches. This is not turned on by default
 */
#define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)

/* Isoch request wait on GTT enable (Display A/B/C streams).
 * Make isoch requests stall on the TLB update. May cause
 * display underruns (test mode only)
 */
#define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)

/* Block grant count for isoch requests when block count is
 * set to a finite value.
 */
#define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
#define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
#define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
#define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
#define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */

/* Enable render writes to complete in C2/C3/C4 power states.
 * If this isn't enabled, render writes are prevented in low
 * power states. That seems bad to me.
 */
#define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)

/* This acknowledges an async flip immediately instead
 * of waiting for 2TLB fetches.
 */
#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)

/* Enables non-sequential data reads through arbiter
 */
#define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)

/* Disable FSB snooping of cacheable write cycles from binner/render
 * command stream
 */
#define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)

/* Arbiter time slice for non-isoch streams */
#define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
#define   MI_ARB_TIME_SLICE_1			(0 << 5)
#define   MI_ARB_TIME_SLICE_2			(1 << 5)
#define   MI_ARB_TIME_SLICE_4			(2 << 5)
#define   MI_ARB_TIME_SLICE_6			(3 << 5)
#define   MI_ARB_TIME_SLICE_8			(4 << 5)
#define   MI_ARB_TIME_SLICE_10			(5 << 5)
#define   MI_ARB_TIME_SLICE_14			(6 << 5)
#define   MI_ARB_TIME_SLICE_16			(7 << 5)

/* Low priority grace period page size */
#define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
#define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)

/* Disable display A/B trickle feed */
#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)

/* Set display plane priority */
#define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */

#define MI_STATE	_MMIO(0x20e4) /* gen2 only */
#define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
#define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */

#define CACHE_MODE_0	_MMIO(0x2120) /* 915+ only */
#define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
#define   CM0_IZ_OPT_DISABLE      (1<<6)
#define   CM0_ZR_OPT_DISABLE      (1<<5)
#define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
#define   CM0_DEPTH_EVICT_DISABLE (1<<4)
#define   CM0_COLOR_EVICT_DISABLE (1<<3)
#define   CM0_DEPTH_WRITE_DISABLE (1<<1)
#define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
#define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
#define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
#define   GFX_FLSH_CNTL_EN	(1<<0)
#define ECOSKPD		_MMIO(0x21d0)
#define   ECO_GATING_CX_ONLY	(1<<3)
#define   ECO_FLIP_DONE		(1<<0)

#define CACHE_MODE_0_GEN7	_MMIO(0x7000) /* IVB+ */
#define RC_OP_FLUSH_ENABLE (1<<0)
#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
#define CACHE_MODE_1		_MMIO(0x7004) /* IVB+ */
#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1<<6)
#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)

#define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
#define   GEN6_BLITTER_LOCK_SHIFT			16
#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)

#define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)
#define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
#define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)

#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)

/* Fuse readout registers for GT */
#define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
#define   CHV_FGT_DISABLE_SS0		(1 << 10)
#define   CHV_FGT_DISABLE_SS1		(1 << 11)
#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
#define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
#define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
#define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
#define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
#define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
#define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
#define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)

#define GEN8_FUSE2			_MMIO(0x9120)
#define   GEN8_F2_SS_DIS_SHIFT		21
#define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
#define   GEN8_F2_S_ENA_SHIFT		25
#define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)

#define   GEN9_F2_SS_DIS_SHIFT		20
#define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)

#define GEN8_EU_DISABLE0		_MMIO(0x9134)
#define   GEN8_EU_DIS0_S0_MASK		0xffffff
#define   GEN8_EU_DIS0_S1_SHIFT		24
#define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)

#define GEN8_EU_DISABLE1		_MMIO(0x9138)
#define   GEN8_EU_DIS1_S1_MASK		0xffff
#define   GEN8_EU_DIS1_S2_SHIFT		16
#define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)

#define GEN8_EU_DISABLE2		_MMIO(0x913c)
#define   GEN8_EU_DIS2_S2_MASK		0xff

#define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)

#define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
#define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
#define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
#define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
#define   GEN6_BSD_GO_INDICATOR		(1 << 4)

/* On modern GEN architectures interrupt control consists of two sets
 * of registers. The first set pertains to the ring generating the
 * interrupt. The second control is for the functional block generating the
 * interrupt. These are PM, GT, DE, etc.
 *
 * Luckily *knocks on wood* all the ring interrupt bits match up with the
 * GT interrupt bits, so we don't need to duplicate the defines.
 *
 * These defines should cover us well from SNB->HSW with minor exceptions
 * it can also work on ILK.
 */
#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
#define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
#define GT_BLT_USER_INTERRUPT			(1 << 22)
#define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
#define GT_BSD_USER_INTERRUPT			(1 << 12)
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
#define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
#define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
#define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
#define GT_RENDER_USER_INTERRUPT		(1 <<  0)

#define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */
#define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */

#define GT_PARITY_ERROR(dev_priv) \
	(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
	 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))

/* These are all the "old" interrupts */
#define ILK_BSD_USER_INTERRUPT				(1<<5)

#define I915_PM_INTERRUPT				(1<<31)
#define I915_ISP_INTERRUPT				(1<<22)
#define I915_LPE_PIPE_B_INTERRUPT			(1<<21)
#define I915_LPE_PIPE_A_INTERRUPT			(1<<20)
#define I915_MIPIC_INTERRUPT				(1<<19)
#define I915_MIPIA_INTERRUPT				(1<<18)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
#define I915_DISPLAY_PORT_INTERRUPT			(1<<17)
#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1<<16)
#define I915_MASTER_ERROR_INTERRUPT			(1<<15)
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1<<14)
#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1<<13)
#define I915_HWB_OOM_INTERRUPT				(1<<13)
#define I915_LPE_PIPE_C_INTERRUPT			(1<<12)
#define I915_SYNC_STATUS_INTERRUPT			(1<<12)
#define I915_MISC_INTERRUPT				(1<<11)
#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1<<10)
#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1<<9)
#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1<<8)
#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1<<3)
#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1<<2)
#define I915_DEBUG_INTERRUPT				(1<<2)
#define I915_WINVALID_INTERRUPT				(1<<1)
#define I915_USER_INTERRUPT				(1<<1)
#define I915_ASLE_INTERRUPT				(1<<0)
#define I915_BSD_USER_INTERRUPT				(1<<25)

#define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
#define I915_HDMI_LPE_AUDIO_SIZE	0x1000

/* DisplayPort Audio w/ LPE */
#define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
#define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)

#define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
#define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
#define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
#define VLV_AUD_PORT_EN_DBG(port)	_MMIO_PORT3((port) - PORT_B,	   \
						    _VLV_AUD_PORT_EN_B_DBG, \
						    _VLV_AUD_PORT_EN_C_DBG, \
						    _VLV_AUD_PORT_EN_D_DBG)
#define VLV_AMP_MUTE		        (1 << 1)

#define GEN6_BSD_RNCID			_MMIO(0x12198)

#define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
#define   GEN7_FF_SCHED_MASK		0x0077070
#define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)
#define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
#define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
#define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
#define   GEN7_FF_TS_SCHED_HW		(0x0<<16) /* Default */