| /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,gcc-msm8996.h> |
| #include <dt-bindings/clock/qcom,mmcc-msm8996.h> |
| |
| / { |
| model = "Qualcomm Technologies, Inc. MSM8996"; |
| |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| chosen { }; |
| |
| memory { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the reg */ |
| reg = <0 0 0 0>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| mba_region: mba@91500000 { |
| reg = <0x0 0x91500000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| slpi_region: slpi@90b00000 { |
| reg = <0x0 0x90b00000 0x0 0xa00000>; |
| no-map; |
| }; |
| |
| venus_region: venus@90400000 { |
| reg = <0x0 0x90400000 0x0 0x700000>; |
| no-map; |
| }; |
| |
| adsp_region: adsp@8ea00000 { |
| reg = <0x0 0x8ea00000 0x0 0x1a00000>; |
| no-map; |
| }; |
| |
| mpss_region: mpss@88800000 { |
| reg = <0x0 0x88800000 0x0 0x6200000>; |
| no-map; |
| }; |
| |
| smem_mem: smem-mem@86000000 { |
| reg = <0x0 0x86000000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| memory@85800000 { |
| reg = <0x0 0x85800000 0x0 0x800000>; |
| no-map; |
| }; |
| |
| memory@86200000 { |
| reg = <0x0 0x86200000 0x0 0x2600000>; |
| no-map; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| }; |
| |
| CPU1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| CPU2: cpu@100 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_1>; |
| L2_1: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| }; |
| |
| CPU3: cpu@101 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo"; |
| reg = <0x0 0x101>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_1>; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&CPU2>; |
| }; |
| |
| core1 { |
| cpu = <&CPU3>; |
| }; |
| }; |
| }; |
| }; |
| |
| thermal-zones { |
| cpu-thermal0 { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 3>; |
| |
| trips { |
| cpu_alert0: trip0 { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_crit0: trip1 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| cpu-thermal1 { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 5>; |
| |
| trips { |
| cpu_alert1: trip0 { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_crit1: trip1 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| cpu-thermal2 { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 8>; |
| |
| trips { |
| cpu_alert2: trip0 { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_crit2: trip1 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| cpu-thermal3 { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 10>; |
| |
| trips { |
| cpu_alert3: trip0 { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_crit3: trip1 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| clocks { |
| xo_board: xo_board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <19200000>; |
| clock-output-names = "xo_board"; |
| }; |
| |
| sleep_clk: sleep_clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32764>; |
| clock-output-names = "sleep_clk"; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-msm8996"; |
| }; |
| }; |
| |
| tcsr_mutex: hwlock { |
| compatible = "qcom,tcsr-mutex"; |
| syscon = <&tcsr_mutex_regs 0 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_mem>; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| rpm-glink { |
| compatible = "qcom,glink-rpm"; |
| |
| interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; |
| |
| qcom,rpm-msg-ram = <&rpm_msg_ram>; |
| |
| mboxes = <&apcs_glb 0>; |
| |
| rpm_requests { |
| compatible = "qcom,rpm-msm8996"; |
| qcom,glink-channels = "rpm_requests"; |
| |
| pm8994-regulators { |
| compatible = "qcom,rpm-pm8994-regulators"; |
| |
| pm8994_s1: s1 {}; |
| pm8994_s2: s2 {}; |
| pm8994_s3: s3 {}; |
| pm8994_s4: s4 {}; |
| pm8994_s5: s5 {}; |
| pm8994_s6: s6 {}; |
| pm8994_s7: s7 {}; |
| pm8994_s8: s8 {}; |
| pm8994_s9: s9 {}; |
| pm8994_s10: s10 {}; |
| pm8994_s11: s11 {}; |
| pm8994_s12: s12 {}; |
| |
| pm8994_l1: l1 {}; |
| pm8994_l2: l2 {}; |
| pm8994_l3: l3 {}; |
| pm8994_l4: l4 {}; |
| pm8994_l5: l5 {}; |
| pm8994_l6: l6 {}; |
| pm8994_l7: l7 {}; |
| pm8994_l8: l8 {}; |
| pm8994_l9: l9 {}; |
| pm8994_l10: l10 {}; |
| pm8994_l11: l11 {}; |
| pm8994_l12: l12 {}; |
| pm8994_l13: l13 {}; |
| pm8994_l14: l14 {}; |
| pm8994_l15: l15 {}; |
| pm8994_l16: l16 {}; |
| pm8994_l17: l17 {}; |
| pm8994_l18: l18 {}; |
| pm8994_l19: l19 {}; |
| pm8994_l20: l20 {}; |
| pm8994_l21: l21 {}; |
| pm8994_l22: l22 {}; |
| pm8994_l23: l23 {}; |
| pm8994_l24: l24 {}; |
| pm8994_l25: l25 {}; |
| pm8994_l26: l26 {}; |
| pm8994_l27: l27 {}; |
| pm8994_l28: l28 {}; |
| pm8994_l29: l29 {}; |
| pm8994_l30: l30 {}; |
| pm8994_l31: l31 {}; |
| pm8994_l32: l32 {}; |
| }; |
| |
| }; |
| }; |
| |
| soc: soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| rpm_msg_ram: memory@68000 { |
| compatible = "qcom,rpm-msg-ram"; |
| reg = <0x68000 0x6000>; |
| }; |
| |
| tcsr_mutex_regs: syscon@740000 { |
| compatible = "syscon"; |
| reg = <0x740000 0x20000>; |
| }; |
| |
| intc: interrupt-controller@9bc0000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x40000>; |
| reg = <0x09bc0000 0x10000>, |
| <0x09c00000 0x100000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| apcs: syscon@9820000 { |
| compatible = "syscon"; |
| reg = <0x9820000 0x1000>; |
| }; |
| |
| apcs_glb: mailbox@9820000 { |
| compatible = "qcom,msm8996-apcs-hmss-global"; |
| reg = <0x9820000 0x1000>; |
| |
| #mbox-cells = <1>; |
| }; |
| |
| gcc: clock-controller@300000 { |
| compatible = "qcom,gcc-msm8996"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| reg = <0x300000 0x90000>; |
| }; |
| |
| kryocc: clock-controller@6400000 { |
| compatible = "qcom,apcc-msm8996"; |
| reg = <0x6400000 0x90000>; |
| #clock-cells = <1>; |
| }; |
| |
| blsp1_spi0: spi@07575000 { |
| compatible = "qcom,spi-qup-v2.2.1"; |
| reg = <0x07575000 0x600>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp1_spi0_default>; |
| pinctrl-1 = <&blsp1_spi0_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp2_i2c0: i2c@075b5000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x075b5000 0x1000>; |
| interrupts = <GIC_SPI 101 0>; |
| clocks = <&gcc GCC_BLSP2_AHB_CLK>, |
| <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; |
| clock-names = "iface", "core"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_i2c0_default>; |
| pinctrl-1 = <&blsp2_i2c0_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| tsens0: thermal-sensor@4a8000 { |
| compatible = "qcom,msm8996-tsens"; |
| reg = <0x4a8000 0x2000>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| blsp2_uart1: serial@75b0000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x75b0000 0x1000>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| blsp2_i2c1: i2c@075b6000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x075b6000 0x1000>; |
| interrupts = <GIC_SPI 102 0>; |
| clocks = <&gcc GCC_BLSP2_AHB_CLK>, |
| <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; |
| clock-names = "iface", "core"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_i2c1_default>; |
| pinctrl-1 = <&blsp2_i2c1_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp2_uart2: serial@75b1000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x075b1000 0x1000>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| blsp1_i2c2: i2c@07577000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x07577000 0x1000>; |
| interrupts = <GIC_SPI 97 0>; |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>, |
| <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; |
| clock-names = "iface", "core"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp1_i2c2_default>; |
| pinctrl-1 = <&blsp1_i2c2_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp2_spi5: spi@075ba000{ |
| compatible = "qcom,spi-qup-v2.2.1"; |
| reg = <0x075ba000 0x600>; |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_spi5_default>; |
| pinctrl-1 = <&blsp2_spi5_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sdhc2: sdhci@74a4900 { |
| status = "disabled"; |
| compatible = "qcom,sdhci-msm-v4"; |
| reg = <0x74a4900 0x314>, <0x74a4000 0x800>; |
| reg-names = "hc_mem", "core_mem"; |
| |
| interrupts = <0 125 0>, <0 221 0>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| clock-names = "iface", "core", "xo"; |
| clocks = <&gcc GCC_SDCC2_AHB_CLK>, |
| <&gcc GCC_SDCC2_APPS_CLK>, |
| <&xo_board>; |
| bus-width = <4>; |
| }; |
| |
| msmgpio: pinctrl@1010000 { |
| compatible = "qcom,msm8996-pinctrl"; |
| reg = <0x01010000 0x300000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| timer@09840000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x09840000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@9850000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x09850000 0x1000>, |
| <0x09860000 0x1000>; |
| }; |
| |
| frame@9870000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x09870000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@9880000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x09880000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@9890000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x09890000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@98a0000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x098a0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@98b0000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x098b0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@98c0000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x098c0000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| spmi_bus: qcom,spmi@400f000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0x400f000 0x1000>, |
| <0x4400000 0x800000>, |
| <0x4c00000 0x800000>, |
| <0x5800000 0x200000>, |
| <0x400a000 0x002100>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| }; |
| |
| mmcc: clock-controller@8c0000 { |
| compatible = "qcom,mmcc-msm8996"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| reg = <0x8c0000 0x40000>; |
| assigned-clocks = <&mmcc MMPLL9_PLL>, |
| <&mmcc MMPLL1_PLL>, |
| <&mmcc MMPLL3_PLL>, |
| <&mmcc MMPLL4_PLL>, |
| <&mmcc MMPLL5_PLL>; |
| assigned-clock-rates = <624000000>, |
| <810000000>, |
| <980000000>, |
| <960000000>, |
| <825000000>; |
| }; |
| |
| qfprom@74000 { |
| compatible = "qcom,qfprom"; |
| reg = <0x74000 0x8ff>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| qusb2p_hstx_trim: hstx_trim@24e { |
| reg = <0x24e 0x2>; |
| bits = <5 4>; |
| }; |
| |
| qusb2s_hstx_trim: hstx_trim@24f { |
| reg = <0x24f 0x1>; |
| bits = <1 4>; |
| }; |
| }; |
| |
| phy@34000 { |
| compatible = "qcom,msm8996-qmp-pcie-phy"; |
| reg = <0x34000 0x488>; |
| #clock-cells = <1>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, |
| <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_CLKREF_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref"; |
| |
| vdda-phy-supply = <&pm8994_l28>; |
| vdda-pll-supply = <&pm8994_l12>; |
| |
| resets = <&gcc GCC_PCIE_PHY_BCR>, |
| <&gcc GCC_PCIE_PHY_COM_BCR>, |
| <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; |
| reset-names = "phy", "common", "cfg"; |
| status = "disabled"; |
| |
| pciephy_0: lane@35000 { |
| reg = <0x035000 0x130>, |
| <0x035200 0x200>, |
| <0x035400 0x1dc>; |
| #phy-cells = <0>; |
| |
| clock-output-names = "pcie_0_pipe_clk_src"; |
| clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; |
| clock-names = "pipe0"; |
| resets = <&gcc GCC_PCIE_0_PHY_BCR>; |
| reset-names = "lane0"; |
| }; |
| |
| pciephy_1: lane@36000 { |
| reg = <0x036000 0x130>, |
| <0x036200 0x200>, |
| <0x036400 0x1dc>; |
| #phy-cells = <0>; |
| |
| clock-output-names = "pcie_1_pipe_clk_src"; |
| clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; |
| clock-names = "pipe1"; |
| resets = <&gcc GCC_PCIE_1_PHY_BCR>; |
| reset-names = "lane1"; |
| }; |
| |
| pciephy_2: lane@37000 { |
| reg = <0x037000 0x130>, |
| <0x037200 0x200>, |
| <0x037400 0x1dc>; |
| #phy-cells = <0>; |
| |
| clock-output-names = "pcie_2_pipe_clk_src"; |
| clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; |
| clock-names = "pipe2"; |
| resets = <&gcc GCC_PCIE_2_PHY_BCR>; |
| reset-names = "lane2"; |
| }; |
| }; |
| |
| phy@7410000 { |
| compatible = "qcom,msm8996-qmp-usb3-phy"; |
| reg = <0x7410000 0x1c4>; |
| #clock-cells = <1>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, |
| <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| <&gcc GCC_USB3_CLKREF_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref"; |
| |
| vdda-phy-supply = <&pm8994_l28>; |
| vdda-pll-supply = <&pm8994_l12>; |
| |
| resets = <&gcc GCC_USB3_PHY_BCR>, |
| <&gcc GCC_USB3PHY_PHY_BCR>; |
| reset-names = "phy", "common"; |
| status = "disabled"; |
| |
| ssusb_phy_0: lane@7410200 { |
| reg = <0x7410200 0x200>, |
| <0x7410400 0x130>, |
| <0x7410600 0x1a8>; |
| #phy-cells = <0>; |
| |
| clock-output-names = "usb3_phy_pipe_clk_src"; |
| clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; |
| clock-names = "pipe0"; |
| }; |
| }; |
| |
| hsusb_phy1: phy@7411000 { |
| compatible = "qcom,msm8996-qusb2-phy"; |
| reg = <0x7411000 0x180>; |
| #phy-cells = <0>; |
| |
| clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| <&gcc GCC_RX1_USB2_CLKREF_CLK>; |
| clock-names = "cfg_ahb", "ref"; |
| |
| vdda-pll-supply = <&pm8994_l12>; |
| vdda-phy-dpdm-supply = <&pm8994_l24>; |
| |
| resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
| nvmem-cells = <&qusb2p_hstx_trim>; |
| status = "disabled"; |
| }; |
| |
| hsusb_phy2: phy@7412000 { |
| compatible = "qcom,msm8996-qusb2-phy"; |
| reg = <0x7412000 0x180>; |
| #phy-cells = <0>; |
| |
| clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| <&gcc GCC_RX2_USB2_CLKREF_CLK>; |
| clock-names = "cfg_ahb", "ref"; |
| |
| vdda-pll-supply = <&pm8994_l12>; |
| vdda-phy-dpdm-supply = <&pm8994_l24>; |
| |
| resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
| nvmem-cells = <&qusb2s_hstx_trim>; |
| status = "disabled"; |
| }; |
| |
| usb2: usb@7600000 { |
| compatible = "qcom,dwc3"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, |
| <&gcc GCC_USB20_MASTER_CLK>, |
| <&gcc GCC_USB20_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB20_SLEEP_CLK>, |
| <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; |
| |
| assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB20_MASTER_CLK>; |
| assigned-clock-rates = <19200000>, <60000000>; |
| |
| power-domains = <&gcc USB30_GDSC>; |
| status = "disabled"; |
| |
| dwc3@7600000 { |
| compatible = "snps,dwc3"; |
| reg = <0x7600000 0xcc00>; |
| interrupts = <0 138 0>; |
| phys = <&hsusb_phy2>; |
| phy-names = "usb2-phy"; |
| }; |
| }; |
| |
| usb3: usb@6a00000 { |
| compatible = "qcom,dwc3"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, |
| <&gcc GCC_USB30_MASTER_CLK>, |
| <&gcc GCC_AGGRE2_USB3_AXI_CLK>, |
| <&gcc GCC_USB30_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_SLEEP_CLK>, |
| <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; |
| |
| assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_MASTER_CLK>; |
| assigned-clock-rates = <19200000>, <120000000>; |
| |
| power-domains = <&gcc USB30_GDSC>; |
| status = "disabled"; |
| |
| dwc3@6a00000 { |
| compatible = "snps,dwc3"; |
| reg = <0x6a00000 0xcc00>; |
| interrupts = <0 131 0>; |
| phys = <&hsusb_phy1>, <&ssusb_phy_0>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| }; |
| }; |
| }; |
| |
| adsp-pil { |
| compatible = "qcom,msm8996-adsp-pil"; |
| |
| interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", |
| "handover", "stop-ack"; |
| |
| clocks = <&xo_board>; |
| clock-names = "xo"; |
| |
| memory-region = <&adsp_region>; |
| |
| qcom,smem-states = <&adsp_smp2p_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| smd-edge { |
| interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "lpass"; |
| qcom,ipc = <&apcs 16 8>; |
| qcom,smd-edge = <1>; |
| qcom,remote-pid = <2>; |
| }; |
| }; |
| |
| adsp-smp2p { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <443>, <429>; |
| |
| interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; |
| |
| qcom,ipc = <&apcs 16 10>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <2>; |
| |
| adsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| adsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| modem-smp2p { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <435>, <428>; |
| |
| interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; |
| |
| qcom,ipc = <&apcs 16 14>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <1>; |
| |
| modem_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| modem_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-slpi { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <481>, <430>; |
| |
| interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; |
| |
| qcom,ipc = <&apcs 16 26>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <3>; |
| |
| slpi_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| slpi_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| }; |
| |
| }; |
| #include "msm8996-pins.dtsi" |
