Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt

* ARM SMMUv3 Architecture Implementation

The SMMUv3 architecture is a significant departure from previous
revisions, replacing the MMIO register interface with in-memory command
and event queues and adding support for the ATS and PRI components of
the PCIe specification.

** SMMUv3 required properties:

- compatible        : Should include:

                      * "arm,smmu-v3" for any SMMUv3 compliant
                        implementation. This entry should be last in the
                        compatible list.

- reg               : Base address and size of the SMMU.

- interrupts        : Non-secure interrupt list describing the wired
                      interrupt sources corresponding to entries in
                      interrupt-names. If no wired interrupts are
                      present then this property may be omitted.

- interrupt-names   : When the interrupts property is present, should
                      include the following:
                      * "eventq"    - Event Queue not empty
                      * "priq"      - PRI Queue not empty
                      * "cmdq-sync" - CMD_SYNC complete
                      * "gerror"    - Global Error activated
                      * "combined"  - The combined interrupt is optional,
				      and should only be provided if the
				      hardware supports just a single,
				      combined interrupt line.
				      If provided, then the combined interrupt
				      will be used in preference to any others.

- #iommu-cells      : See the generic IOMMU binding described in
                        devicetree/bindings/pci/pci-iommu.txt
                      for details. For SMMUv3, must be 1, with each cell
                      describing a single stream ID. All possible stream
                      IDs which a device may emit must be described.

** SMMUv3 optional properties:

- dma-coherent      : Present if DMA operations made by the SMMU (page
                      table walks, stream table accesses etc) are cache
                      coherent with the CPU.

                      NOTE: this only applies to the SMMU itself, not
                      masters connected upstream of the SMMU.

- msi-parent        : See the generic MSI binding described in
                        devicetree/bindings/interrupt-controller/msi.txt
                      for a description of the msi-parent property.

- hisilicon,broken-prefetch-cmd
                    : Avoid sending CMD_PREFETCH_* commands to the SMMU.

- cavium,cn9900-broken-page1-regspace
                    : Replaces all page 1 offsets used for EVTQ_PROD/CONS,
		      PRIQ_PROD/CONS register access with page 0 offsets.
		      Set for Cavium ThunderX2 silicon that doesn't support
		      SMMU page1 register space.

** Example

        smmu@2b400000 {
                compatible = "arm,smmu-v3";
                reg = <0x0 0x2b400000 0x0 0x20000>;
                interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
                             <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
                             <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
                             <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
                interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
                dma-coherent;
                #iommu-cells = <1>;
                msi-parent = <&its 0xff0000>;
        };