Sign in
gem5
/
arm
/
linux
/
675357362aeba19688440eb1aaa7991067f73b12
/
.
/
arch
/
h8300
/
include
/
asm
/
cache.h
blob: 0ef1edc5a6a62e33cd63f51e1cc3b6e8da065000 [
file
] [
log
] [
blame
]
#ifndef
__ARCH_H8300_CACHE_H
#define
__ARCH_H8300_CACHE_H
/* bytes per L1 cache line */
#define
L1_CACHE_SHIFT
2
#define
L1_CACHE_BYTES
(
1
<<
L1_CACHE_SHIFT
)
#define
__cacheline_aligned
#define
____cacheline_aligned
#endif