drivers/media/platform/vsp1/vsp1_pipe.c - arm/linux - Git at Google

 /*
  * vsp1_pipe.c  --  R-Car VSP1 Pipeline
  *
  * Copyright (C) 2013-2015 Renesas Electronics Corporation
  *
  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  */

 #include <linux/delay.h>
 #include <linux/list.h>
 #include <linux/sched.h>
 #include <linux/wait.h>

 #include <media/media-entity.h>
 #include <media/v4l2-subdev.h>

 #include "vsp1.h"
 #include "vsp1_bru.h"
 #include "vsp1_dl.h"
 #include "vsp1_entity.h"
 #include "vsp1_hgo.h"
 #include "vsp1_hgt.h"
 #include "vsp1_pipe.h"
 #include "vsp1_rwpf.h"
 #include "vsp1_uds.h"

 /* -----------------------------------------------------------------------------
  * Helper Functions
  */

 static const struct vsp1_format_info vsp1_video_formats[] = {
 	{ V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 8, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS,
 	  1, { 16, 0, 0 }, false, false, 1, 1, true },
 	{ V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS,
 	  1, { 16, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS,
 	  1, { 16, 0, 0 }, false, false, 1, 1, true },
 	{ V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS,
 	  1, { 16, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS,
 	  1, { 16, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 24, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 24, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
 	  1, { 32, 0, 0 }, false, false, 1, 1, true },
 	{ V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
 	  1, { 32, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 32, 0, 0 }, false, false, 1, 1, true },
 	{ V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
 	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 32, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_HSV24, MEDIA_BUS_FMT_AHSV8888_1X32,
 	  VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 24, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_HSV32, MEDIA_BUS_FMT_AHSV8888_1X32,
 	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 32, 0, 0 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 16, 0, 0 }, false, false, 2, 1, false },
 	{ V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 16, 0, 0 }, false, true, 2, 1, false },
 	{ V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 16, 0, 0 }, true, false, 2, 1, false },
 	{ V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  1, { 16, 0, 0 }, true, true, 2, 1, false },
 	{ V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  2, { 8, 16, 0 }, false, false, 2, 2, false },
 	{ V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  2, { 8, 16, 0 }, false, true, 2, 2, false },
 	{ V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  2, { 8, 16, 0 }, false, false, 2, 1, false },
 	{ V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  2, { 8, 16, 0 }, false, true, 2, 1, false },
 	{ V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  3, { 8, 8, 8 }, false, false, 2, 2, false },
 	{ V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  3, { 8, 8, 8 }, false, true, 2, 2, false },
 	{ V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  3, { 8, 8, 8 }, false, false, 2, 1, false },
 	{ V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  3, { 8, 8, 8 }, false, true, 2, 1, false },
 	{ V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  3, { 8, 8, 8 }, false, false, 1, 1, false },
 	{ V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
 	  VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 	  3, { 8, 8, 8 }, false, true, 1, 1, false },
 };

 /**
  * vsp1_get_format_info - Retrieve format information for a 4CC
  * @vsp1: the VSP1 device
  * @fourcc: the format 4CC
  *
  * Return a pointer to the format information structure corresponding to the
  * given V4L2 format 4CC, or NULL if no corresponding format can be found.
  */
 const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1,
 						    u32 fourcc)
 {
 	unsigned int i;

 	/* Special case, the VYUY and HSV formats are supported on Gen2 only. */
 	if (vsp1->info->gen != 2) {
 		switch (fourcc) {
 		case V4L2_PIX_FMT_VYUY:
 		case V4L2_PIX_FMT_HSV24:
 		case V4L2_PIX_FMT_HSV32:
 			return NULL;
 		}
 	}

 	for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) {
 		const struct vsp1_format_info *info = &vsp1_video_formats[i];

 		if (info->fourcc == fourcc)
 			return info;
 	}

 	return NULL;
 }

 /* -----------------------------------------------------------------------------
  * Pipeline Management
  */

 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
 {
 	unsigned int i;

 	if (pipe->bru) {
 		struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);

 		for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i)
 			bru->inputs[i].rpf = NULL;
 	}

 	for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
 		if (pipe->inputs[i]) {
 			pipe->inputs[i]->pipe = NULL;
 			pipe->inputs[i] = NULL;
 		}
 	}

 	if (pipe->output) {
 		pipe->output->pipe = NULL;
 		pipe->output = NULL;
 	}

 	if (pipe->hgo) {
 		struct vsp1_hgo *hgo = to_hgo(&pipe->hgo->subdev);

 		hgo->histo.pipe = NULL;
 	}

 	if (pipe->hgt) {
 		struct vsp1_hgt *hgt = to_hgt(&pipe->hgt->subdev);

 		hgt->histo.pipe = NULL;
 	}

 	INIT_LIST_HEAD(&pipe->entities);
 	pipe->state = VSP1_PIPELINE_STOPPED;
 	pipe->buffers_ready = 0;
 	pipe->num_inputs = 0;
 	pipe->bru = NULL;
 	pipe->hgo = NULL;
 	pipe->hgt = NULL;
 	pipe->lif = NULL;
 	pipe->uds = NULL;
 }

 void vsp1_pipeline_init(struct vsp1_pipeline *pipe)
 {
 	mutex_init(&pipe->lock);
 	spin_lock_init(&pipe->irqlock);
 	init_waitqueue_head(&pipe->wq);
 	kref_init(&pipe->kref);

 	INIT_LIST_HEAD(&pipe->entities);
 	pipe->state = VSP1_PIPELINE_STOPPED;
 }

 /* Must be called with the pipe irqlock held. */
 void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
 {
 	struct vsp1_device *vsp1 = pipe->output->entity.vsp1;

 	if (pipe->state == VSP1_PIPELINE_STOPPED) {
 		vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
 			   VI6_CMD_STRCMD);
 		pipe->state = VSP1_PIPELINE_RUNNING;
 	}

 	pipe->buffers_ready = 0;
 }

 bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe)
 {
 	unsigned long flags;
 	bool stopped;

 	spin_lock_irqsave(&pipe->irqlock, flags);
 	stopped = pipe->state == VSP1_PIPELINE_STOPPED;
 	spin_unlock_irqrestore(&pipe->irqlock, flags);

 	return stopped;
 }

 int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
 {
 	struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
 	struct vsp1_entity *entity;
 	unsigned long flags;
 	int ret;

 	if (pipe->lif) {
 		/*
 		 * When using display lists in continuous frame mode the only
 		 * way to stop the pipeline is to reset the hardware.
 		 */
 		ret = vsp1_reset_wpf(vsp1, pipe->output->entity.index);
 		if (ret == 0) {
 			spin_lock_irqsave(&pipe->irqlock, flags);
 			pipe->state = VSP1_PIPELINE_STOPPED;
 			spin_unlock_irqrestore(&pipe->irqlock, flags);
 		}
 	} else {
 		/* Otherwise just request a stop and wait. */
 		spin_lock_irqsave(&pipe->irqlock, flags);
 		if (pipe->state == VSP1_PIPELINE_RUNNING)
 			pipe->state = VSP1_PIPELINE_STOPPING;
 		spin_unlock_irqrestore(&pipe->irqlock, flags);

 		ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 					 msecs_to_jiffies(500));
 		ret = ret == 0 ? -ETIMEDOUT : 0;
 	}

 	list_for_each_entry(entity, &pipe->entities, list_pipe) {
 		if (entity->route && entity->route->reg)
 			vsp1_write(vsp1, entity->route->reg,
 				   VI6_DPR_NODE_UNUSED);
 	}

 	if (pipe->hgo)
 		vsp1_write(vsp1, VI6_DPR_HGO_SMPPT,
 			   (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
 			   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));

 	if (pipe->hgt)
 		vsp1_write(vsp1, VI6_DPR_HGT_SMPPT,
 			   (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
 			   (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));

 	v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0);

 	return ret;
 }

 bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
 {
 	unsigned int mask;

 	mask = ((1 << pipe->num_inputs) - 1) << 1;
 	if (!pipe->lif)
 		mask |= 1 << 0;

 	return pipe->buffers_ready == mask;
 }

 void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
 {
 	bool completed;

 	if (pipe == NULL)
 		return;

 	/*
 	 * If the DL commit raced with the frame end interrupt, the commit ends
 	 * up being postponed by one frame. @completed represents whether the
 	 * active frame was finished or postponed.
 	 */
 	completed = vsp1_dlm_irq_frame_end(pipe->output->dlm);

 	if (pipe->hgo)
 		vsp1_hgo_frame_end(pipe->hgo);

 	if (pipe->hgt)
 		vsp1_hgt_frame_end(pipe->hgt);

 	/*
 	 * Regardless of frame completion we still need to notify the pipe
 	 * frame_end to account for vblank events.
 	 */
 	if (pipe->frame_end)
 		pipe->frame_end(pipe, completed);

 	pipe->sequence++;
 }

 /*
  * Propagate the alpha value through the pipeline.
  *
  * As the UDS has restricted scaling capabilities when the alpha component needs
  * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha
  * value. The UDS then outputs a fixed alpha value which needs to be programmed
  * from the input RPF alpha.
  */
 void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
 				   struct vsp1_dl_list *dl, unsigned int alpha)
 {
 	if (!pipe->uds)
 		return;

 	/*
 	 * The BRU and BRS background color has a fixed alpha value set to 255,
 	 * the output alpha value is thus always equal to 255.
 	 */
 	if (pipe->uds_input->type == VSP1_ENTITY_BRU ||
 	    pipe->uds_input->type == VSP1_ENTITY_BRS)
 		alpha = 255;

 	vsp1_uds_set_alpha(pipe->uds, dl, alpha);
 }

 /*
  * Propagate the partition calculations through the pipeline
  *
  * Work backwards through the pipe, allowing each entity to update the partition
  * parameters based on its configuration, and the entity connected to its
  * source. Each entity must produce the partition required for the previous
  * entity in the pipeline.
  */
 void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe,
 				       struct vsp1_partition *partition,
 				       unsigned int index,
 				       struct vsp1_partition_window *window)
 {
 	struct vsp1_entity *entity;

 	list_for_each_entry_reverse(entity, &pipe->entities, list_pipe) {
 		if (entity->ops->partition)
 			entity->ops->partition(entity, pipe, partition, index,
 					       window);
 	}
 }

 void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
 {
 	unsigned long flags;
 	unsigned int i;
 	int ret;

 	/*
 	 * To avoid increasing the system suspend time needlessly, loop over the
 	 * pipelines twice, first to set them all to the stopping state, and
 	 * then to wait for the stop to complete.
 	 */
 	for (i = 0; i < vsp1->info->wpf_count; ++i) {
 		struct vsp1_rwpf *wpf = vsp1->wpf[i];
 		struct vsp1_pipeline *pipe;

 		if (wpf == NULL)
 			continue;

 		pipe = wpf->pipe;
 		if (pipe == NULL)
 			continue;

 		spin_lock_irqsave(&pipe->irqlock, flags);
 		if (pipe->state == VSP1_PIPELINE_RUNNING)
 			pipe->state = VSP1_PIPELINE_STOPPING;
 		spin_unlock_irqrestore(&pipe->irqlock, flags);
 	}

 	for (i = 0; i < vsp1->info->wpf_count; ++i) {
 		struct vsp1_rwpf *wpf = vsp1->wpf[i];
 		struct vsp1_pipeline *pipe;

 		if (wpf == NULL)
 			continue;

 		pipe = wpf->pipe;
 		if (pipe == NULL)
 			continue;

 		ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 					 msecs_to_jiffies(500));
 		if (ret == 0)
 			dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
 				 wpf->entity.index);
 	}
 }

 void vsp1_pipelines_resume(struct vsp1_device *vsp1)
 {
 	unsigned long flags;
 	unsigned int i;

 	/* Resume all running pipelines. */
 	for (i = 0; i < vsp1->info->wpf_count; ++i) {
 		struct vsp1_rwpf *wpf = vsp1->wpf[i];
 		struct vsp1_pipeline *pipe;

 		if (wpf == NULL)
 			continue;

 		pipe = wpf->pipe;
 		if (pipe == NULL)
 			continue;

 		spin_lock_irqsave(&pipe->irqlock, flags);
 		if (vsp1_pipeline_ready(pipe))
 			vsp1_pipeline_run(pipe);
 		spin_unlock_irqrestore(&pipe->irqlock, flags);
 	}
 }
	/*
	* vsp1_pipe.c -- R-Car VSP1 Pipeline
	*
	* Copyright (C) 2013-2015 Renesas Electronics Corporation
	*
	* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License as published by
	* the Free Software Foundation; either version 2 of the License, or
	* (at your option) any later version.
	*/

	#include <linux/delay.h>
	#include <linux/list.h>
	#include <linux/sched.h>
	#include <linux/wait.h>

	#include <media/media-entity.h>
	#include <media/v4l2-subdev.h>

	#include "vsp1.h"
	#include "vsp1_bru.h"
	#include "vsp1_dl.h"
	#include "vsp1_entity.h"
	#include "vsp1_hgo.h"
	#include "vsp1_hgt.h"
	#include "vsp1_pipe.h"
	#include "vsp1_rwpf.h"
	#include "vsp1_uds.h"

	/* -----------------------------------------------------------------------------
	* Helper Functions
	*/

	static const struct vsp1_format_info vsp1_video_formats[] = {
	{ V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 8, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS,
	1, { 16, 0, 0 }, false, false, 1, 1, true },
	{ V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS,
	1, { 16, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS,
	1, { 16, 0, 0 }, false, false, 1, 1, true },
	{ V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS,
	1, { 16, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS,
	1, { 16, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 24, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 24, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS,
	1, { 32, 0, 0 }, false, false, 1, 1, true },
	{ V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS,
	1, { 32, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 32, 0, 0 }, false, false, 1, 1, true },
	{ V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
	VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 32, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_HSV24, MEDIA_BUS_FMT_AHSV8888_1X32,
	VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 24, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_HSV32, MEDIA_BUS_FMT_AHSV8888_1X32,
	VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 32, 0, 0 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 16, 0, 0 }, false, false, 2, 1, false },
	{ V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 16, 0, 0 }, false, true, 2, 1, false },
	{ V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 16, 0, 0 }, true, false, 2, 1, false },
	{ V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	1, { 16, 0, 0 }, true, true, 2, 1, false },
	{ V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	2, { 8, 16, 0 }, false, false, 2, 2, false },
	{ V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	2, { 8, 16, 0 }, false, true, 2, 2, false },
	{ V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	2, { 8, 16, 0 }, false, false, 2, 1, false },
	{ V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	2, { 8, 16, 0 }, false, true, 2, 1, false },
	{ V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	3, { 8, 8, 8 }, false, false, 2, 2, false },
	{ V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	3, { 8, 8, 8 }, false, true, 2, 2, false },
	{ V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	3, { 8, 8, 8 }, false, false, 2, 1, false },
	{ V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	3, { 8, 8, 8 }, false, true, 2, 1, false },
	{ V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	3, { 8, 8, 8 }, false, false, 1, 1, false },
	{ V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
	VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS \| VI6_RPF_DSWAP_P_LWS \|
	VI6_RPF_DSWAP_P_WDS \| VI6_RPF_DSWAP_P_BTS,
	3, { 8, 8, 8 }, false, true, 1, 1, false },
	};

	/**
	* vsp1_get_format_info - Retrieve format information for a 4CC
	* @vsp1: the VSP1 device
	* @fourcc: the format 4CC
	*
	* Return a pointer to the format information structure corresponding to the
	* given V4L2 format 4CC, or NULL if no corresponding format can be found.
	*/
	const struct vsp1_format_info vsp1_get_format_info(struct vsp1_device vsp1,
	u32 fourcc)
	{
	unsigned int i;

	/* Special case, the VYUY and HSV formats are supported on Gen2 only. */
	if (vsp1->info->gen != 2) {
	switch (fourcc) {
	case V4L2_PIX_FMT_VYUY:
	case V4L2_PIX_FMT_HSV24:
	case V4L2_PIX_FMT_HSV32:
	return NULL;
	}
	}

	for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) {
	const struct vsp1_format_info *info = &vsp1_video_formats[i];

	if (info->fourcc == fourcc)
	return info;
	}

	return NULL;
	}

	/* -----------------------------------------------------------------------------
	* Pipeline Management
	*/

	void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
	{
	unsigned int i;

	if (pipe->bru) {
	struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);

	for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i)
	bru->inputs[i].rpf = NULL;
	}

	for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
	if (pipe->inputs[i]) {
	pipe->inputs[i]->pipe = NULL;
	pipe->inputs[i] = NULL;
	}
	}

	if (pipe->output) {
	pipe->output->pipe = NULL;
	pipe->output = NULL;
	}

	if (pipe->hgo) {
	struct vsp1_hgo *hgo = to_hgo(&pipe->hgo->subdev);

	hgo->histo.pipe = NULL;
	}

	if (pipe->hgt) {
	struct vsp1_hgt *hgt = to_hgt(&pipe->hgt->subdev);

	hgt->histo.pipe = NULL;
	}

	INIT_LIST_HEAD(&pipe->entities);
	pipe->state = VSP1_PIPELINE_STOPPED;
	pipe->buffers_ready = 0;
	pipe->num_inputs = 0;
	pipe->bru = NULL;
	pipe->hgo = NULL;
	pipe->hgt = NULL;
	pipe->lif = NULL;
	pipe->uds = NULL;
	}

	void vsp1_pipeline_init(struct vsp1_pipeline *pipe)
	{
	mutex_init(&pipe->lock);
	spin_lock_init(&pipe->irqlock);
	init_waitqueue_head(&pipe->wq);
	kref_init(&pipe->kref);

	INIT_LIST_HEAD(&pipe->entities);
	pipe->state = VSP1_PIPELINE_STOPPED;
	}

	/* Must be called with the pipe irqlock held. */
	void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
	{
	struct vsp1_device *vsp1 = pipe->output->entity.vsp1;

	if (pipe->state == VSP1_PIPELINE_STOPPED) {
	vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
	VI6_CMD_STRCMD);
	pipe->state = VSP1_PIPELINE_RUNNING;
	}

	pipe->buffers_ready = 0;
	}

	bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe)
	{
	unsigned long flags;
	bool stopped;

	spin_lock_irqsave(&pipe->irqlock, flags);
	stopped = pipe->state == VSP1_PIPELINE_STOPPED;
	spin_unlock_irqrestore(&pipe->irqlock, flags);

	return stopped;
	}

	int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
	{
	struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
	struct vsp1_entity *entity;
	unsigned long flags;
	int ret;

	if (pipe->lif) {
	/*
	* When using display lists in continuous frame mode the only
	* way to stop the pipeline is to reset the hardware.
	*/
	ret = vsp1_reset_wpf(vsp1, pipe->output->entity.index);
	if (ret == 0) {
	spin_lock_irqsave(&pipe->irqlock, flags);
	pipe->state = VSP1_PIPELINE_STOPPED;
	spin_unlock_irqrestore(&pipe->irqlock, flags);
	}
	} else {
	/* Otherwise just request a stop and wait. */
	spin_lock_irqsave(&pipe->irqlock, flags);
	if (pipe->state == VSP1_PIPELINE_RUNNING)
	pipe->state = VSP1_PIPELINE_STOPPING;
	spin_unlock_irqrestore(&pipe->irqlock, flags);

	ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
	msecs_to_jiffies(500));
	ret = ret == 0 ? -ETIMEDOUT : 0;
	}

	list_for_each_entry(entity, &pipe->entities, list_pipe) {
	if (entity->route && entity->route->reg)
	vsp1_write(vsp1, entity->route->reg,
	VI6_DPR_NODE_UNUSED);
	}

	if (pipe->hgo)
	vsp1_write(vsp1, VI6_DPR_HGO_SMPPT,
	(7 << VI6_DPR_SMPPT_TGW_SHIFT) \|
	(VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));

	if (pipe->hgt)
	vsp1_write(vsp1, VI6_DPR_HGT_SMPPT,
	(7 << VI6_DPR_SMPPT_TGW_SHIFT) \|
	(VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));

	v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0);

	return ret;
	}

	bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
	{
	unsigned int mask;

	mask = ((1 << pipe->num_inputs) - 1) << 1;
	if (!pipe->lif)
	mask \|= 1 << 0;

	return pipe->buffers_ready == mask;
	}

	void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
	{
	bool completed;

	if (pipe == NULL)
	return;

	/*
	* If the DL commit raced with the frame end interrupt, the commit ends
	* up being postponed by one frame. @completed represents whether the
	* active frame was finished or postponed.
	*/
	completed = vsp1_dlm_irq_frame_end(pipe->output->dlm);

	if (pipe->hgo)
	vsp1_hgo_frame_end(pipe->hgo);

	if (pipe->hgt)
	vsp1_hgt_frame_end(pipe->hgt);

	/*
	* Regardless of frame completion we still need to notify the pipe
	* frame_end to account for vblank events.
	*/
	if (pipe->frame_end)
	pipe->frame_end(pipe, completed);

	pipe->sequence++;
	}

	/*
	* Propagate the alpha value through the pipeline.
	*
	* As the UDS has restricted scaling capabilities when the alpha component needs
	* to be scaled, we disable alpha scaling when the UDS input has a fixed alpha
	* value. The UDS then outputs a fixed alpha value which needs to be programmed
	* from the input RPF alpha.
	*/
	void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
	struct vsp1_dl_list *dl, unsigned int alpha)
	{
	if (!pipe->uds)
	return;

	/*
	* The BRU and BRS background color has a fixed alpha value set to 255,
	* the output alpha value is thus always equal to 255.
	*/
	if (pipe->uds_input->type == VSP1_ENTITY_BRU \|\|
	pipe->uds_input->type == VSP1_ENTITY_BRS)
	alpha = 255;

	vsp1_uds_set_alpha(pipe->uds, dl, alpha);
	}

	/*
	* Propagate the partition calculations through the pipeline
	*
	* Work backwards through the pipe, allowing each entity to update the partition
	* parameters based on its configuration, and the entity connected to its
	* source. Each entity must produce the partition required for the previous
	* entity in the pipeline.
	*/
	void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe,
	struct vsp1_partition *partition,
	unsigned int index,
	struct vsp1_partition_window *window)
	{
	struct vsp1_entity *entity;

	list_for_each_entry_reverse(entity, &pipe->entities, list_pipe) {
	if (entity->ops->partition)
	entity->ops->partition(entity, pipe, partition, index,
	window);
	}
	}

	void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
	{
	unsigned long flags;
	unsigned int i;
	int ret;

	/*
	* To avoid increasing the system suspend time needlessly, loop over the
	* pipelines twice, first to set them all to the stopping state, and
	* then to wait for the stop to complete.
	*/
	for (i = 0; i < vsp1->info->wpf_count; ++i) {
	struct vsp1_rwpf *wpf = vsp1->wpf[i];
	struct vsp1_pipeline *pipe;

	if (wpf == NULL)
	continue;

	pipe = wpf->pipe;
	if (pipe == NULL)
	continue;

	spin_lock_irqsave(&pipe->irqlock, flags);
	if (pipe->state == VSP1_PIPELINE_RUNNING)
	pipe->state = VSP1_PIPELINE_STOPPING;
	spin_unlock_irqrestore(&pipe->irqlock, flags);
	}

	for (i = 0; i < vsp1->info->wpf_count; ++i) {
	struct vsp1_rwpf *wpf = vsp1->wpf[i];
	struct vsp1_pipeline *pipe;

	if (wpf == NULL)
	continue;

	pipe = wpf->pipe;
	if (pipe == NULL)
	continue;

	ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
	msecs_to_jiffies(500));
	if (ret == 0)
	dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
	wpf->entity.index);
	}
	}

	void vsp1_pipelines_resume(struct vsp1_device *vsp1)
	{
	unsigned long flags;
	unsigned int i;

	/* Resume all running pipelines. */
	for (i = 0; i < vsp1->info->wpf_count; ++i) {
	struct vsp1_rwpf *wpf = vsp1->wpf[i];
	struct vsp1_pipeline *pipe;

	if (wpf == NULL)
	continue;

	pipe = wpf->pipe;
	if (pipe == NULL)
	continue;

	spin_lock_irqsave(&pipe->irqlock, flags);
	if (vsp1_pipeline_ready(pipe))
	vsp1_pipeline_run(pipe);
	spin_unlock_irqrestore(&pipe->irqlock, flags);
	}
	}