arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi - arm/linux - Git at Google

 /*
  * Device Tree Include file for NXP Layerscape-1088A family SoC.
  *
  * Copyright 2017 NXP
  *
  * Harninder Rai <harninder.rai@nxp.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPLv2 or the X11 license, at your option. Note that this dual
  * licensing only applies to this file, and not this project as a
  * whole.
  *
  *  a) This library is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
  *     This library is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  * Or, alternatively,
  *
  *  b) Permission is hereby granted, free of charge, to any person
  *     obtaining a copy of this software and associated documentation
  *     files (the "Software"), to deal in the Software without
  *     restriction, including without limitation the rights to use,
  *     copy, modify, merge, publish, distribute, sublicense, and/or
  *     sell copies of the Software, and to permit persons to whom the
  *     Software is furnished to do so, subject to the following
  *     conditions:
  *
  *     The above copyright notice and this permission notice shall be
  *     included in all copies or substantial portions of the Software.
  *
  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 #include <dt-bindings/interrupt-controller/arm-gic.h>

 / {
 	compatible = "fsl,ls1088a";
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		/* We have 2 clusters having 4 Cortex-A53 cores each */
 		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x0>;
 			clocks = <&clockgen 1 0>;
 		};

 		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x1>;
 			clocks = <&clockgen 1 0>;
 		};

 		cpu2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x2>;
 			clocks = <&clockgen 1 0>;
 		};

 		cpu3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x3>;
 			clocks = <&clockgen 1 0>;
 		};

 		cpu4: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x100>;
 			clocks = <&clockgen 1 1>;
 		};

 		cpu5: cpu@101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x101>;
 			clocks = <&clockgen 1 1>;
 		};

 		cpu6: cpu@102 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x102>;
 			clocks = <&clockgen 1 1>;
 		};

 		cpu7: cpu@103 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x103>;
 			clocks = <&clockgen 1 1>;
 		};
 	};

 	gic: interrupt-controller@6000000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
 		interrupt-controller;
 		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 		      <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
 		      <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 		      <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 		      <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 		interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
 	};

 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
 			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
 			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
 			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
 	};

 	sysclk: sysclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <100000000>;
 		clock-output-names = "sysclk";
 	};

 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

 		clockgen: clocking@1300000 {
 			compatible = "fsl,ls1088a-clockgen";
 			reg = <0 0x1300000 0 0xa0000>;
 			#clock-cells = <2>;
 			clocks = <&sysclk>;
 		};

 		duart0: serial@21c0500 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21c0500 0x0 0x100>;
 			clocks = <&clockgen 4 3>;
 			interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};

 		duart1: serial@21c0600 {
 			compatible = "fsl,ns16550", "ns16550a";
 			reg = <0x0 0x21c0600 0x0 0x100>;
 			clocks = <&clockgen 4 3>;
 			interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};

 		gpio0: gpio@2300000 {
 			compatible = "fsl,qoriq-gpio";
 			reg = <0x0 0x2300000 0x0 0x10000>;
 			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 		};

 		gpio1: gpio@2310000 {
 			compatible = "fsl,qoriq-gpio";
 			reg = <0x0 0x2310000 0x0 0x10000>;
 			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 		};

 		gpio2: gpio@2320000 {
 			compatible = "fsl,qoriq-gpio";
 			reg = <0x0 0x2320000 0x0 0x10000>;
 			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 		};

 		gpio3: gpio@2330000 {
 			compatible = "fsl,qoriq-gpio";
 			reg = <0x0 0x2330000 0x0 0x10000>;
 			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 		};

 		ifc: ifc@2240000 {
 			compatible = "fsl,ifc", "simple-bus";
 			reg = <0x0 0x2240000 0x0 0x20000>;
 			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 			little-endian;
 			#address-cells = <2>;
 			#size-cells = <1>;

 			ranges = <0 0 0x5 0x80000000 0x08000000
 				  2 0 0x5 0x30000000 0x00010000
 				  3 0 0x5 0x20000000 0x00010000>;
 			status = "disabled";
 		};

 		i2c0: i2c@2000000 {
 			compatible = "fsl,vf610-i2c";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x0 0x2000000 0x0 0x10000>;
 			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 3>;
 			status = "disabled";
 		};

 		i2c1: i2c@2010000 {
 			compatible = "fsl,vf610-i2c";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x0 0x2010000 0x0 0x10000>;
 			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 3>;
 			status = "disabled";
 		};

 		i2c2: i2c@2020000 {
 			compatible = "fsl,vf610-i2c";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x0 0x2020000 0x0 0x10000>;
 			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 3>;
 			status = "disabled";
 		};

 		i2c3: i2c@2030000 {
 			compatible = "fsl,vf610-i2c";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x0 0x2030000 0x0 0x10000>;
 			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 3>;
 			status = "disabled";
 		};

 		sata: sata@3200000 {
 			compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
 			reg = <0x0 0x3200000 0x0 0x10000>;
 			interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 3>;
 			status = "disabled";
 		};
 	};

 };
	/*
	* Device Tree Include file for NXP Layerscape-1088A family SoC.
	*
	* Copyright 2017 NXP
	*
	* Harninder Rai <harninder.rai@nxp.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPLv2 or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This library is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This library is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*/
	#include <dt-bindings/interrupt-controller/arm-gic.h>

	/ {
	compatible = "fsl,ls1088a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	/* We have 2 clusters having 4 Cortex-A53 cores each */
	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	clocks = <&clockgen 1 0>;
	};

	cpu1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x1>;
	clocks = <&clockgen 1 0>;
	};

	cpu2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x2>;
	clocks = <&clockgen 1 0>;
	};

	cpu3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x3>;
	clocks = <&clockgen 1 0>;
	};

	cpu4: cpu@100 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x100>;
	clocks = <&clockgen 1 1>;
	};

	cpu5: cpu@101 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x101>;
	clocks = <&clockgen 1 1>;
	};

	cpu6: cpu@102 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x102>;
	clocks = <&clockgen 1 1>;
	};

	cpu7: cpu@103 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x103>;
	clocks = <&clockgen 1 1>;
	};
	};

	gic: interrupt-controller@6000000 {
	compatible = "arm,gic-v3";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
	<0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
	<0x0 0x0c0c0000 0 0x2000>, /* GICC */
	<0x0 0x0c0d0000 0 0x1000>, /* GICH */
	<0x0 0x0c0e0000 0 0x20000>; /* GICV */
	interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
	<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
	<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
	<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
	};

	sysclk: sysclk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <100000000>;
	clock-output-names = "sysclk";
	};

	soc {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	clockgen: clocking@1300000 {
	compatible = "fsl,ls1088a-clockgen";
	reg = <0 0x1300000 0 0xa0000>;
	#clock-cells = <2>;
	clocks = <&sysclk>;
	};

	duart0: serial@21c0500 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x0 0x21c0500 0x0 0x100>;
	clocks = <&clockgen 4 3>;
	interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	duart1: serial@21c0600 {
	compatible = "fsl,ns16550", "ns16550a";
	reg = <0x0 0x21c0600 0x0 0x100>;
	clocks = <&clockgen 4 3>;
	interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	gpio0: gpio@2300000 {
	compatible = "fsl,qoriq-gpio";
	reg = <0x0 0x2300000 0x0 0x10000>;
	interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio1: gpio@2310000 {
	compatible = "fsl,qoriq-gpio";
	reg = <0x0 0x2310000 0x0 0x10000>;
	interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio2: gpio@2320000 {
	compatible = "fsl,qoriq-gpio";
	reg = <0x0 0x2320000 0x0 0x10000>;
	interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	gpio3: gpio@2330000 {
	compatible = "fsl,qoriq-gpio";
	reg = <0x0 0x2330000 0x0 0x10000>;
	interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	};

	ifc: ifc@2240000 {
	compatible = "fsl,ifc", "simple-bus";
	reg = <0x0 0x2240000 0x0 0x20000>;
	interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
	little-endian;
	#address-cells = <2>;
	#size-cells = <1>;

	ranges = <0 0 0x5 0x80000000 0x08000000
	2 0 0x5 0x30000000 0x00010000
	3 0 0x5 0x20000000 0x00010000>;
	status = "disabled";
	};

	i2c0: i2c@2000000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2000000 0x0 0x10000>;
	interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c1: i2c@2010000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2010000 0x0 0x10000>;
	interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c2: i2c@2020000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2020000 0x0 0x10000>;
	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	i2c3: i2c@2030000 {
	compatible = "fsl,vf610-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x0 0x2030000 0x0 0x10000>;
	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};

	sata: sata@3200000 {
	compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
	reg = <0x0 0x3200000 0x0 0x10000>;
	interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen 4 3>;
	status = "disabled";
	};
	};

	};