| /* |
| * Copyright 2012 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Alex Deucher |
| */ |
| #include <linux/firmware.h> |
| #include <linux/slab.h> |
| #include <linux/module.h> |
| #include <drm/drmP.h> |
| #include "radeon.h" |
| #include "radeon_asic.h" |
| #include "radeon_audio.h" |
| #include "cikd.h" |
| #include "atom.h" |
| #include "cik_blit_shaders.h" |
| #include "radeon_ucode.h" |
| #include "clearstate_ci.h" |
| #include "radeon_kfd.h" |
| |
| #define SH_MEM_CONFIG_GFX_DEFAULT \ |
| ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) |
| |
| MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin"); |
| MODULE_FIRMWARE("radeon/BONAIRE_me.bin"); |
| MODULE_FIRMWARE("radeon/BONAIRE_ce.bin"); |
| MODULE_FIRMWARE("radeon/BONAIRE_mec.bin"); |
| MODULE_FIRMWARE("radeon/BONAIRE_mc.bin"); |
| MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin"); |
| MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin"); |
| MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin"); |
| MODULE_FIRMWARE("radeon/BONAIRE_smc.bin"); |
| |
| MODULE_FIRMWARE("radeon/bonaire_pfp.bin"); |
| MODULE_FIRMWARE("radeon/bonaire_me.bin"); |
| MODULE_FIRMWARE("radeon/bonaire_ce.bin"); |
| MODULE_FIRMWARE("radeon/bonaire_mec.bin"); |
| MODULE_FIRMWARE("radeon/bonaire_mc.bin"); |
| MODULE_FIRMWARE("radeon/bonaire_rlc.bin"); |
| MODULE_FIRMWARE("radeon/bonaire_sdma.bin"); |
| MODULE_FIRMWARE("radeon/bonaire_smc.bin"); |
| MODULE_FIRMWARE("radeon/bonaire_k_smc.bin"); |
| |
| MODULE_FIRMWARE("radeon/HAWAII_pfp.bin"); |
| MODULE_FIRMWARE("radeon/HAWAII_me.bin"); |
| MODULE_FIRMWARE("radeon/HAWAII_ce.bin"); |
| MODULE_FIRMWARE("radeon/HAWAII_mec.bin"); |
| MODULE_FIRMWARE("radeon/HAWAII_mc.bin"); |
| MODULE_FIRMWARE("radeon/HAWAII_mc2.bin"); |
| MODULE_FIRMWARE("radeon/HAWAII_rlc.bin"); |
| MODULE_FIRMWARE("radeon/HAWAII_sdma.bin"); |
| MODULE_FIRMWARE("radeon/HAWAII_smc.bin"); |
| |
| MODULE_FIRMWARE("radeon/hawaii_pfp.bin"); |
| MODULE_FIRMWARE("radeon/hawaii_me.bin"); |
| MODULE_FIRMWARE("radeon/hawaii_ce.bin"); |
| MODULE_FIRMWARE("radeon/hawaii_mec.bin"); |
| MODULE_FIRMWARE("radeon/hawaii_mc.bin"); |
| MODULE_FIRMWARE("radeon/hawaii_rlc.bin"); |
| MODULE_FIRMWARE("radeon/hawaii_sdma.bin"); |
| MODULE_FIRMWARE("radeon/hawaii_smc.bin"); |
| MODULE_FIRMWARE("radeon/hawaii_k_smc.bin"); |
| |
| MODULE_FIRMWARE("radeon/KAVERI_pfp.bin"); |
| MODULE_FIRMWARE("radeon/KAVERI_me.bin"); |
| MODULE_FIRMWARE("radeon/KAVERI_ce.bin"); |
| MODULE_FIRMWARE("radeon/KAVERI_mec.bin"); |
| MODULE_FIRMWARE("radeon/KAVERI_rlc.bin"); |
| MODULE_FIRMWARE("radeon/KAVERI_sdma.bin"); |
| |
| MODULE_FIRMWARE("radeon/kaveri_pfp.bin"); |
| MODULE_FIRMWARE("radeon/kaveri_me.bin"); |
| MODULE_FIRMWARE("radeon/kaveri_ce.bin"); |
| MODULE_FIRMWARE("radeon/kaveri_mec.bin"); |
| MODULE_FIRMWARE("radeon/kaveri_mec2.bin"); |
| MODULE_FIRMWARE("radeon/kaveri_rlc.bin"); |
| MODULE_FIRMWARE("radeon/kaveri_sdma.bin"); |
| |
| MODULE_FIRMWARE("radeon/KABINI_pfp.bin"); |
| MODULE_FIRMWARE("radeon/KABINI_me.bin"); |
| MODULE_FIRMWARE("radeon/KABINI_ce.bin"); |
| MODULE_FIRMWARE("radeon/KABINI_mec.bin"); |
| MODULE_FIRMWARE("radeon/KABINI_rlc.bin"); |
| MODULE_FIRMWARE("radeon/KABINI_sdma.bin"); |
| |
| MODULE_FIRMWARE("radeon/kabini_pfp.bin"); |
| MODULE_FIRMWARE("radeon/kabini_me.bin"); |
| MODULE_FIRMWARE("radeon/kabini_ce.bin"); |
| MODULE_FIRMWARE("radeon/kabini_mec.bin"); |
| MODULE_FIRMWARE("radeon/kabini_rlc.bin"); |
| MODULE_FIRMWARE("radeon/kabini_sdma.bin"); |
| |
| MODULE_FIRMWARE("radeon/MULLINS_pfp.bin"); |
| MODULE_FIRMWARE("radeon/MULLINS_me.bin"); |
| MODULE_FIRMWARE("radeon/MULLINS_ce.bin"); |
| MODULE_FIRMWARE("radeon/MULLINS_mec.bin"); |
| MODULE_FIRMWARE("radeon/MULLINS_rlc.bin"); |
| MODULE_FIRMWARE("radeon/MULLINS_sdma.bin"); |
| |
| MODULE_FIRMWARE("radeon/mullins_pfp.bin"); |
| MODULE_FIRMWARE("radeon/mullins_me.bin"); |
| MODULE_FIRMWARE("radeon/mullins_ce.bin"); |
| MODULE_FIRMWARE("radeon/mullins_mec.bin"); |
| MODULE_FIRMWARE("radeon/mullins_rlc.bin"); |
| MODULE_FIRMWARE("radeon/mullins_sdma.bin"); |
| |
| extern int r600_ih_ring_alloc(struct radeon_device *rdev); |
| extern void r600_ih_ring_fini(struct radeon_device *rdev); |
| extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
| extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
| extern bool evergreen_is_display_hung(struct radeon_device *rdev); |
| extern void sumo_rlc_fini(struct radeon_device *rdev); |
| extern int sumo_rlc_init(struct radeon_device *rdev); |
| extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
| extern void si_rlc_reset(struct radeon_device *rdev); |
| extern void si_init_uvd_internal_cg(struct radeon_device *rdev); |
| static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh); |
| extern int cik_sdma_resume(struct radeon_device *rdev); |
| extern void cik_sdma_enable(struct radeon_device *rdev, bool enable); |
| extern void cik_sdma_fini(struct radeon_device *rdev); |
| extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable); |
| static void cik_rlc_stop(struct radeon_device *rdev); |
| static void cik_pcie_gen3_enable(struct radeon_device *rdev); |
| static void cik_program_aspm(struct radeon_device *rdev); |
| static void cik_init_pg(struct radeon_device *rdev); |
| static void cik_init_cg(struct radeon_device *rdev); |
| static void cik_fini_pg(struct radeon_device *rdev); |
| static void cik_fini_cg(struct radeon_device *rdev); |
| static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev, |
| bool enable); |
| |
| /** |
| * cik_get_allowed_info_register - fetch the register for the info ioctl |
| * |
| * @rdev: radeon_device pointer |
| * @reg: register offset in bytes |
| * @val: register value |
| * |
| * Returns 0 for success or -EINVAL for an invalid register |
| * |
| */ |
| int cik_get_allowed_info_register(struct radeon_device *rdev, |
| u32 reg, u32 *val) |
| { |
| switch (reg) { |
| case GRBM_STATUS: |
| case GRBM_STATUS2: |
| case GRBM_STATUS_SE0: |
| case GRBM_STATUS_SE1: |
| case GRBM_STATUS_SE2: |
| case GRBM_STATUS_SE3: |
| case SRBM_STATUS: |
| case SRBM_STATUS2: |
| case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET): |
| case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET): |
| case UVD_STATUS: |
| /* TODO VCE */ |
| *val = RREG32(reg); |
| return 0; |
| default: |
| return -EINVAL; |
| } |
| } |
| |
| /* |
| * Indirect registers accessor |
| */ |
| u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) |
| { |
| unsigned long flags; |
| u32 r; |
| |
| spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
| WREG32(CIK_DIDT_IND_INDEX, (reg)); |
| r = RREG32(CIK_DIDT_IND_DATA); |
| spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
| return r; |
| } |
| |
| void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| { |
| unsigned long flags; |
| |
| spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
| WREG32(CIK_DIDT_IND_INDEX, (reg)); |
| WREG32(CIK_DIDT_IND_DATA, (v)); |
| spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
| } |
| |
| /* get temperature in millidegrees */ |
| int ci_get_temp(struct radeon_device *rdev) |
| { |
| u32 temp; |
| int actual_temp = 0; |
| |
| temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> |
| CTF_TEMP_SHIFT; |
| |
| if (temp & 0x200) |
| actual_temp = 255; |
| else |
| actual_temp = temp & 0x1ff; |
| |
| actual_temp = actual_temp * 1000; |
| |
| return actual_temp; |
| } |
| |
| /* get temperature in millidegrees */ |
| int kv_get_temp(struct radeon_device *rdev) |
| { |
| u32 temp; |
| int actual_temp = 0; |
| |
| temp = RREG32_SMC(0xC0300E0C); |
| |
| if (temp) |
| actual_temp = (temp / 8) - 49; |
| else |
| actual_temp = 0; |
| |
| actual_temp = actual_temp * 1000; |
| |
| return actual_temp; |
| } |
| |
| /* |
| * Indirect registers accessor |
| */ |
| u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg) |
| { |
| unsigned long flags; |
| u32 r; |
| |
| spin_lock_irqsave(&rdev->pciep_idx_lock, flags); |
| WREG32(PCIE_INDEX, reg); |
| (void)RREG32(PCIE_INDEX); |
| r = RREG32(PCIE_DATA); |
| spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); |
| return r; |
| } |
| |
| void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| { |
| unsigned long flags; |
| |
| spin_lock_irqsave(&rdev->pciep_idx_lock, flags); |
| WREG32(PCIE_INDEX, reg); |
| (void)RREG32(PCIE_INDEX); |
| WREG32(PCIE_DATA, v); |
| (void)RREG32(PCIE_DATA); |
| spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); |
| } |
| |
| static const u32 spectre_rlc_save_restore_register_list[] = |
| { |
| (0x0e00 << 16) | (0xc12c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc140 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc150 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc15c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc168 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc170 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc178 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc204 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2b4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2b8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2bc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2c0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8228 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x829c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x869c >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x98f4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x98f8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9900 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc260 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x90e8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c000 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c00c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c1c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9700 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x8e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x9e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0xae00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0xbe00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x89bc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8900 >> 2), |
| 0x00000000, |
| 0x3, |
| (0x0e00 << 16) | (0xc130 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc134 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc1fc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc208 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc264 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc268 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc26c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc270 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc274 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc278 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc27c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc280 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc284 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc288 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc28c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc290 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc294 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc298 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc29c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2a0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2a4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2a8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2ac >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2b0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x301d0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30238 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30250 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30254 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30258 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3025c >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x8e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x9e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0xae00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0xbe00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x8e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x9e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0xae00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0xbe00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x8e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x9e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0xae00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0xbe00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x8e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x9e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0xae00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0xbe00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x8e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x9e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0xae00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0xbe00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc99c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9834 >> 2), |
| 0x00000000, |
| (0x0000 << 16) | (0x30f00 >> 2), |
| 0x00000000, |
| (0x0001 << 16) | (0x30f00 >> 2), |
| 0x00000000, |
| (0x0000 << 16) | (0x30f04 >> 2), |
| 0x00000000, |
| (0x0001 << 16) | (0x30f04 >> 2), |
| 0x00000000, |
| (0x0000 << 16) | (0x30f08 >> 2), |
| 0x00000000, |
| (0x0001 << 16) | (0x30f08 >> 2), |
| 0x00000000, |
| (0x0000 << 16) | (0x30f0c >> 2), |
| 0x00000000, |
| (0x0001 << 16) | (0x30f0c >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x9b7c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8a14 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8a18 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a00 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8bf0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8bcc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8b24 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30a04 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a10 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a14 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a18 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a2c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc700 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc704 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc708 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc768 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc770 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc774 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc778 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc77c >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc780 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc784 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc788 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc78c >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc798 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc79c >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc7a0 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc7a4 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc7a8 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc7ac >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc7b0 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc7b4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9100 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c010 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92a8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92ac >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92b4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92b8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92bc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92c0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92c4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92c8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92cc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x92d0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c00 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c04 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c20 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c38 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c3c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xae00 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9604 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac08 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac0c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac10 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac14 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac58 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac68 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac6c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac70 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac74 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac78 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac7c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac80 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac84 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac88 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac8c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x970c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9714 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9718 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x971c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x8e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x9e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0xae00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0xbe00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xcd10 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xcd14 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88b0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88b4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88b8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88bc >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0x89c0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88c4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88c8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88d0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88d4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88d8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8980 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30938 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3093c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30940 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x89a0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30900 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30904 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x89b4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c210 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c214 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c218 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8904 >> 2), |
| 0x00000000, |
| 0x5, |
| (0x0e00 << 16) | (0x8c28 >> 2), |
| (0x0e00 << 16) | (0x8c2c >> 2), |
| (0x0e00 << 16) | (0x8c30 >> 2), |
| (0x0e00 << 16) | (0x8c34 >> 2), |
| (0x0e00 << 16) | (0x9600 >> 2), |
| }; |
| |
| static const u32 kalindi_rlc_save_restore_register_list[] = |
| { |
| (0x0e00 << 16) | (0xc12c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc140 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc150 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc15c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc168 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc170 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc204 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2b4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2b8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2bc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2c0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8228 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x829c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x869c >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x98f4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x98f8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9900 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc260 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x90e8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c000 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c00c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c1c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9700 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xcd20 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x89bc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8900 >> 2), |
| 0x00000000, |
| 0x3, |
| (0x0e00 << 16) | (0xc130 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc134 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc1fc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc208 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc264 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc268 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc26c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc270 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc274 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc28c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc290 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc294 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc298 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2a0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2a4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2a8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc2ac >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x301d0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30238 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30250 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30254 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30258 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3025c >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc900 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc904 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc908 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc90c >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0xc910 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc99c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9834 >> 2), |
| 0x00000000, |
| (0x0000 << 16) | (0x30f00 >> 2), |
| 0x00000000, |
| (0x0000 << 16) | (0x30f04 >> 2), |
| 0x00000000, |
| (0x0000 << 16) | (0x30f08 >> 2), |
| 0x00000000, |
| (0x0000 << 16) | (0x30f0c >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x9b7c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8a14 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8a18 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a00 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8bf0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8bcc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8b24 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30a04 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a10 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a14 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a18 >> 2), |
| 0x00000000, |
| (0x0600 << 16) | (0x30a2c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc700 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc704 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc708 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xc768 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc770 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc774 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc798 >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0xc79c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9100 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c010 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c00 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c04 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c20 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c38 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8c3c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xae00 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9604 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac08 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac0c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac10 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac14 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac58 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac68 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac6c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac70 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac74 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac78 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac7c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac80 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac84 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac88 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xac8c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x970c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9714 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x9718 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x971c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x4e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x5e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x6e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x7e00 << 16) | (0x31068 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xcd10 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0xcd14 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88b0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88b4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88b8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88bc >> 2), |
| 0x00000000, |
| (0x0400 << 16) | (0x89c0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88c4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88c8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88d0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88d4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x88d8 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8980 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30938 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3093c >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30940 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x89a0 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30900 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x30904 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x89b4 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3e1fc >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c210 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c214 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x3c218 >> 2), |
| 0x00000000, |
| (0x0e00 << 16) | (0x8904 >> 2), |
| 0x00000000, |
| 0x5, |
| (0x0e00 << 16) | (0x8c28 >> 2), |
| (0x0e00 << 16) | (0x8c2c >> 2), |
| (0x0e00 << 16) | (0x8c30 >> 2), |
| (0x0e00 << 16) | (0x8c34 >> 2), |
| (0x0e00 << 16) | (0x9600 >> 2), |
| }; |
| |
| static const u32 bonaire_golden_spm_registers[] = |
| { |
| 0x30800, 0xe0ffffff, 0xe0000000 |
| }; |
| |
| static const u32 bonaire_golden_common_registers[] = |
| { |
| 0xc770, 0xffffffff, 0x00000800, |
| 0xc774, 0xffffffff, 0x00000800, |
| 0xc798, 0xffffffff, 0x00007fbf, |
| 0xc79c, 0xffffffff, 0x00007faf |
| }; |
| |
| static const u32 bonaire_golden_registers[] = |
| { |
| 0x3354, 0x00000333, 0x00000333, |
| 0x3350, 0x000c0fc0, 0x00040200, |
| 0x9a10, 0x00010000, 0x00058208, |
| 0x3c000, 0xffff1fff, 0x00140000, |
| 0x3c200, 0xfdfc0fff, 0x00000100, |
| 0x3c234, 0x40000000, 0x40000200, |
| 0x9830, 0xffffffff, 0x00000000, |
| 0x9834, 0xf00fffff, 0x00000400, |
| 0x9838, 0x0002021c, 0x00020200, |
| 0xc78, 0x00000080, 0x00000000, |
| 0x5bb0, 0x000000f0, 0x00000070, |
| 0x5bc0, 0xf0311fff, 0x80300000, |
| 0x98f8, 0x73773777, 0x12010001, |
| 0x350c, 0x00810000, 0x408af000, |
| 0x7030, 0x31000111, 0x00000011, |
| 0x2f48, 0x73773777, 0x12010001, |
| 0x220c, 0x00007fb6, 0x0021a1b1, |
| 0x2210, 0x00007fb6, 0x002021b1, |
| 0x2180, 0x00007fb6, 0x00002191, |
| 0x2218, 0x00007fb6, 0x002121b1, |
| 0x221c, 0x00007fb6, 0x002021b1, |
| 0x21dc, 0x00007fb6, 0x00002191, |
| 0x21e0, 0x00007fb6, 0x00002191, |
| 0x3628, 0x0000003f, 0x0000000a, |
| 0x362c, 0x0000003f, 0x0000000a, |
| 0x2ae4, 0x00073ffe, 0x000022a2, |
| 0x240c, 0x000007ff, 0x00000000, |
| 0x8a14, 0xf000003f, 0x00000007, |
| 0x8bf0, 0x00002001, 0x00000001, |
| 0x8b24, 0xffffffff, 0x00ffffff, |
| 0x30a04, 0x0000ff0f, 0x00000000, |
| 0x28a4c, 0x07ffffff, 0x06000000, |
| 0x4d8, 0x00000fff, 0x00000100, |
| 0x3e78, 0x00000001, 0x00000002, |
| 0x9100, 0x03000000, 0x0362c688, |
| 0x8c00, 0x000000ff, 0x00000001, |
| 0xe40, 0x00001fff, 0x00001fff, |
| 0x9060, 0x0000007f, 0x00000020, |
| 0x9508, 0x00010000, 0x00010000, |
| 0xac14, 0x000003ff, 0x000000f3, |
| 0xac0c, 0xffffffff, 0x00001032 |
| }; |
| |
| static const u32 bonaire_mgcg_cgcg_init[] = |
| { |
| 0xc420, 0xffffffff, 0xfffffffc, |
| 0x30800, 0xffffffff, 0xe0000000, |
| 0x3c2a0, 0xffffffff, 0x00000100, |
| 0x3c208, 0xffffffff, 0x00000100, |
| 0x3c2c0, 0xffffffff, 0xc0000100, |
| 0x3c2c8, 0xffffffff, 0xc0000100, |
| 0x3c2c4, 0xffffffff, 0xc0000100, |
| 0x55e4, 0xffffffff, 0x00600100, |
| 0x3c280, 0xffffffff, 0x00000100, |
| 0x3c214, 0xffffffff, 0x06000100, |
| 0x3c220, 0xffffffff, 0x00000100, |
| 0x3c218, 0xffffffff, 0x06000100, |
| 0x3c204, 0xffffffff, 0x00000100, |
| 0x3c2e0, 0xffffffff, 0x00000100, |
| 0x3c224, 0xffffffff, 0x00000100, |
| 0x3c200, 0xffffffff, 0x00000100, |
| 0x3c230, 0xffffffff, 0x00000100, |
| 0x3c234, 0xffffffff, 0x00000100, |
| 0x3c250, 0xffffffff, 0x00000100, |
| 0x3c254, 0xffffffff, 0x00000100, |
| 0x3c258, 0xffffffff, 0x00000100, |
| 0x3c25c, 0xffffffff, 0x00000100, |
| 0x3c260, 0xffffffff, 0x00000100, |
| 0x3c27c, 0xffffffff, 0x00000100, |
| 0x3c278, 0xffffffff, 0x00000100, |
| 0x3c210, 0xffffffff, 0x06000100, |
| 0x3c290, 0xffffffff, 0x00000100, |
| 0x3c274, 0xffffffff, 0x00000100, |
| 0x3c2b4, 0xffffffff, 0x00000100, |
| 0x3c2b0, 0xffffffff, 0x00000100, |
| 0x3c270, 0xffffffff, 0x00000100, |
| 0x30800, 0xffffffff, 0xe0000000, |
| 0x3c020, 0xffffffff, 0x00010000, |
| 0x3c024, 0xffffffff, 0x00030002, |
| 0x3c028, 0xffffffff, 0x00040007, |
| 0x3c02c, 0xffffffff, 0x00060005, |
| 0x3c030, 0xffffffff, 0x00090008, |
| 0x3c034, 0xffffffff, 0x00010000, |
| 0x3c038, 0xffffffff, 0x00030002, |
| 0x3c03c, 0xffffffff, 0x00040007, |
| 0x3c040, 0xffffffff, 0x00060005, |
| 0x3c044, 0xffffffff, 0x00090008, |
| 0x3c048, 0xffffffff, 0x00010000, |
| 0x3c04c, 0xffffffff, 0x00030002, |
| 0x3c050, 0xffffffff, 0x00040007, |
| 0x3c054, 0xffffffff, 0x00060005, |
| 0x3c058, 0xffffffff, 0x00090008, |
| 0x3c05c, 0xffffffff, 0x00010000, |
| 0x3c060, 0xffffffff, 0x00030002, |
| 0x3c064, 0xffffffff, 0x00040007, |
| 0x3c068, 0xffffffff, 0x00060005, |
| 0x3c06c, 0xffffffff, 0x00090008, |
| 0x3c070, 0xffffffff, 0x00010000, |
| 0x3c074, 0xffffffff, 0x00030002, |
| 0x3c078, 0xffffffff, 0x00040007, |
| 0x3c07c, 0xffffffff, 0x00060005, |
| 0x3c080, 0xffffffff, 0x00090008, |
| 0x3c084, 0xffffffff, 0x00010000, |
| 0x3c088, 0xffffffff, 0x00030002, |
| 0x3c08c, 0xffffffff, 0x00040007, |
| 0x3c090, 0xffffffff, 0x00060005, |
| 0x3c094, 0xffffffff, 0x00090008, |
| 0x3c098, 0xffffffff, 0x00010000, |
| 0x3c09c, 0xffffffff, 0x00030002, |
| 0x3c0a0, 0xffffffff, 0x00040007, |
| 0x3c0a4, 0xffffffff, 0x00060005, |
| 0x3c0a8, 0xffffffff, 0x00090008, |
| 0x3c000, 0xffffffff, 0x96e00200, |
| 0x8708, 0xffffffff, 0x00900100, |
| 0xc424, 0xffffffff, 0x0020003f, |
| 0x38, 0xffffffff, 0x0140001c, |
| 0x3c, 0x000f0000, 0x000f0000, |
| 0x220, 0xffffffff, 0xC060000C, |
| 0x224, 0xc0000fff, 0x00000100, |
| 0xf90, 0xffffffff, 0x00000100, |
| 0xf98, 0x00000101, 0x00000000, |
| 0x20a8, 0xffffffff, 0x00000104, |
| 0x55e4, 0xff000fff, 0x00000100, |
| 0x30cc, 0xc0000fff, 0x00000104, |
| 0xc1e4, 0x00000001, 0x00000001, |
| 0xd00c, 0xff000ff0, 0x00000100, |
| 0xd80c, 0xff000ff0, 0x00000100 |
| }; |
| |
| static const u32 spectre_golden_spm_registers[] = |
| { |
| 0x30800, 0xe0ffffff, 0xe0000000 |
| }; |
| |
| static const u32 spectre_golden_common_registers[] = |
| { |
| 0xc770, 0xffffffff, 0x00000800, |
| 0xc774, 0xffffffff, 0x00000800, |
| 0xc798, 0xffffffff, 0x00007fbf, |
| 0xc79c, 0xffffffff, 0x00007faf |
| }; |
| |
| static const u32 spectre_golden_registers[] = |
| { |
| 0x3c000, 0xffff1fff, 0x96940200, |
| 0x3c00c, 0xffff0001, 0xff000000, |
| 0x3c200, 0xfffc0fff, 0x00000100, |
| 0x6ed8, 0x00010101, 0x00010000, |
| 0x9834, 0xf00fffff, 0x00000400, |
| 0x9838, 0xfffffffc, 0x00020200, |
| 0x5bb0, 0x000000f0, 0x00000070, |
| 0x5bc0, 0xf0311fff, 0x80300000, |
| 0x98f8, 0x73773777, 0x12010001, |
| 0x9b7c, 0x00ff0000, 0x00fc0000, |
| 0x2f48, 0x73773777, 0x12010001, |
| 0x8a14, 0xf000003f, 0x00000007, |
| 0x8b24, 0xffffffff, 0x00ffffff, |
| 0x28350, 0x3f3f3fff, 0x00000082, |
| 0x28354, 0x0000003f, 0x00000000, |
| 0x3e78, 0x00000001, 0x00000002, |
| 0x913c, 0xffff03df, 0x00000004, |
| 0xc768, 0x00000008, 0x00000008, |
| 0x8c00, 0x000008ff, 0x00000800, |
| 0x9508, 0x00010000, 0x00010000, |
| 0xac0c, 0xffffffff, 0x54763210, |
| 0x214f8, 0x01ff01ff, 0x00000002, |
| 0x21498, 0x007ff800, 0x00200000, |
| 0x2015c, 0xffffffff, 0x00000f40, |
| 0x30934, 0xffffffff, 0x00000001 |
| }; |
| |
| static const u32 spectre_mgcg_cgcg_init[] = |
| { |
| 0xc420, 0xffffffff, 0xfffffffc, |
| 0x30800, 0xffffffff, 0xe0000000, |
| 0x3c2a0, 0xffffffff, 0x00000100, |
| 0x3c208, 0xffffffff, 0x00000100, |
| 0x3c2c0, 0xffffffff, 0x00000100, |
| 0x3c2c8, 0xffffffff, 0x00000100, |
| 0x3c2c4, 0xffffffff, 0x00000100, |
| 0x55e4, 0xffffffff, 0x00600100, |
| 0x3c280, 0xffffffff, 0x00000100, |
| 0x3c214, 0xffffffff, 0x06000100, |
| 0x3c220, 0xffffffff, 0x00000100, |
| 0x3c218, 0xffffffff, 0x06000100, |
| 0x3c204, 0xffffffff, 0x00000100, |
| 0x3c2e0, 0xffffffff, 0x00000100, |
| 0x3c224, 0xffffffff, 0x00000100, |
| 0x3c200, 0xffffffff, 0x00000100, |
| 0x3c230, 0xffffffff, 0x00000100, |
| 0x3c234, 0xffffffff, 0x00000100, |
| 0x3c250, 0xffffffff, 0x00000100, |
| 0x3c254, 0xffffffff, 0x00000100, |
| 0x3c258, 0xffffffff, 0x00000100, |
| 0x3c25c, 0xffffffff, 0x00000100, |
| 0x3c260, 0xffffffff, 0x00000100, |
| 0x3c27c, 0xffffffff, 0x00000100, |
| 0x3c278, 0xffffffff, 0x00000100, |
| 0x3c210, 0xffffffff, 0x06000100, |
| 0x3c290, 0xffffffff, 0x00000100, |
| 0x3c274, 0xffffffff, 0x00000100, |
| 0x3c2b4, 0xffffffff, 0x00000100, |
| 0x3c2b0, 0xffffffff, 0x00000100, |
| 0x3c270, 0xffffffff, 0x00000100, |
| 0x30800, 0xffffffff, 0xe0000000, |
| 0x3c020, 0xffffffff, 0x00010000, |
| 0x3c024, 0xffffffff, 0x00030002, |
| 0x3c028, 0xffffffff, 0x00040007, |
| 0x3c02c, 0xffffffff, 0x00060005, |
| 0x3c030, 0xffffffff, 0x00090008, |
| 0x3c034, 0xffffffff, 0x00010000, |
| 0x3c038, 0xffffffff, 0x00030002, |
| 0x3c03c, 0xffffffff, 0x00040007, |
| 0x3c040, 0xffffffff, 0x00060005, |
| 0x3c044, 0xffffffff, 0x00090008, |
| 0x3c048, 0xffffffff, 0x00010000, |
| 0x3c04c, 0xffffffff, 0x00030002, |
| 0x3c050, 0xffffffff, 0x00040007, |
| 0x3c054, 0xffffffff, 0x00060005, |
| 0x3c058, 0xffffffff, 0x00090008, |
| 0x3c05c, 0xffffffff, 0x00010000, |
| 0x3c060, 0xffffffff, 0x00030002, |
| 0x3c064, 0xffffffff, 0x00040007, |
| 0x3c068, 0xffffffff, 0x00060005, |
| 0x3c06c, 0xffffffff, 0x00090008, |
| 0x3c070, 0xffffffff, 0x00010000, |
| 0x3c074, 0xffffffff, 0x00030002, |
| 0x3c078, 0xffffffff, 0x00040007, |
| 0x3c07c, 0xffffffff, 0x00060005, |
| 0x3c080, 0xffffffff, 0x00090008, |
| 0x3c084, 0xffffffff, 0x00010000, |
| 0x3c088, 0xffffffff, 0x00030002, |
| 0x3c08c, 0xffffffff, 0x00040007, |
| 0x3c090, 0xffffffff, 0x00060005, |
| 0x3c094, 0xffffffff, 0x00090008, |
| 0x3c098, 0xffffffff, 0x00010000, |
| 0x3c09c, 0xffffffff, 0x00030002, |
| 0x3c0a0, 0xffffffff, 0x00040007, |
| 0x3c0a4, 0xffffffff, 0x00060005, |
| 0x3c0a8, 0xffffffff, 0x00090008, |
| 0x3c0ac, 0xffffffff, 0x00010000, |
| 0x3c0b0, 0xffffffff, 0x00030002, |
| 0x3c0b4, 0xffffffff, 0x00040007, |
| 0x3c0b8, 0xffffffff, 0x00060005, |
| 0x3c0bc, 0xffffffff, 0x00090008, |
| 0x3c000, 0xffffffff, 0x96e00200, |
| 0x8708, 0xffffffff, 0x00900100, |
| 0xc424, 0xffffffff, 0x0020003f, |
| 0x38, 0xffffffff, 0x0140001c, |
| 0x3c, 0x000f0000, 0x000f0000, |
| 0x220, 0xffffffff, 0xC060000C, |
| 0x224, 0xc0000fff, 0x00000100, |
| 0xf90, 0xffffffff, 0x00000100, |
| 0xf98, 0x00000101, 0x00000000, |
| 0x20a8, 0xffffffff, 0x00000104, |
| 0x55e4, 0xff000fff, 0x00000100, |
| 0x30cc, 0xc0000fff, 0x00000104, |
| 0xc1e4, 0x00000001, 0x00000001, |
| 0xd00c, 0xff000ff0, 0x00000100, |
| 0xd80c, 0xff000ff0, 0x00000100 |
| }; |
| |
| static const u32 kalindi_golden_spm_registers[] = |
| { |
| 0x30800, 0xe0ffffff, 0xe0000000 |
| }; |
| |
| static const u32 kalindi_golden_common_registers[] = |
| { |
| 0xc770, 0xffffffff, 0x00000800, |
| 0xc774, 0xffffffff, 0x00000800, |
| 0xc798, 0xffffffff, 0x00007fbf, |
| 0xc79c, 0xffffffff, 0x00007faf |
| }; |
| |
| static const u32 kalindi_golden_registers[] = |
| { |
| 0x3c000, 0xffffdfff, 0x6e944040, |
| 0x55e4, 0xff607fff, 0xfc000100, |
| 0x3c220, 0xff000fff, 0x00000100, |
| 0x3c224, 0xff000fff, 0x00000100, |
| 0x3c200, 0xfffc0fff, 0x00000100, |
| 0x6ed8, 0x00010101, 0x00010000, |
| 0x9830, 0xffffffff, 0x00000000, |
| 0x9834, 0xf00fffff, 0x00000400, |
| 0x5bb0, 0x000000f0, 0x00000070, |
| 0x5bc0, 0xf0311fff, 0x80300000, |
| 0x98f8, 0x73773777, 0x12010001, |
| 0x98fc, 0xffffffff, 0x00000010, |
| 0x9b7c, 0x00ff0000, 0x00fc0000, |
| 0x8030, 0x00001f0f, 0x0000100a, |
| 0x2f48, 0x73773777, 0x12010001, |
| 0x2408, 0x000fffff, 0x000c007f, |
| 0x8a14, 0xf000003f, 0x00000007, |
| 0x8b24, 0x3fff3fff, 0x00ffcfff, |
| 0x30a04, 0x0000ff0f, 0x00000000, |
| 0x28a4c, 0x07ffffff, 0x06000000, |
| 0x4d8, 0x00000fff, 0x00000100, |
| 0x3e78, 0x00000001, 0x00000002, |
| 0xc768, 0x00000008, 0x00000008, |
| 0x8c00, 0x000000ff, 0x00000003, |
| 0x214f8, 0x01ff01ff, 0x00000002, |
| 0x21498, 0x007ff800, 0x00200000, |
| 0x2015c, 0xffffffff, 0x00000f40, |
| 0x88c4, 0x001f3ae3, 0x00000082, |
| 0x88d4, 0x0000001f, 0x00000010, |
| 0x30934, 0xffffffff, 0x00000000 |
| }; |
| |
| static const u32 kalindi_mgcg_cgcg_init[] = |
| { |
| 0xc420, 0xffffffff, 0xfffffffc, |
| 0x30800, 0xffffffff, 0xe0000000, |
| 0x3c2a0, 0xffffffff, 0x00000100, |
| 0x3c208, 0xffffffff, 0x00000100, |
| 0x3c2c0, 0xffffffff, 0x00000100, |
| 0x3c2c8, 0xffffffff, 0x00000100, |
| 0x3c2c4, 0xffffffff, 0x00000100, |
| 0x55e4, 0xffffffff, 0x00600100, |
| 0x3c280, 0xffffffff, 0x00000100, |
| 0x3c214, 0xffffffff, 0x06000100, |
| 0x3c220, 0xffffffff, 0x00000100, |
| 0x3c218, 0xffffffff, 0x06000100, |
| 0x3c204, 0xffffffff, 0x00000100, |
| 0x3c2e0, 0xffffffff, 0x00000100, |
| 0x3c224, 0xffffffff, 0x00000100, |
| 0x3c200, 0xffffffff, 0x00000100, |
| 0x3c230, 0xffffffff, 0x00000100, |
| 0x3c234, 0xffffffff, 0x00000100, |
| 0x3c250, 0xffffffff, 0x00000100, |
| 0x3c254, 0xffffffff, 0x00000100, |
| 0x3c258, 0xffffffff, 0x00000100, |
| 0x3c25c, 0xffffffff, 0x00000100, |
| 0x3c260, 0xffffffff, 0x00000100, |
| 0x3c27c, 0xffffffff, 0x00000100, |
| 0x3c278, 0xffffffff, 0x00000100, |
| 0x3c210, 0xffffffff, 0x06000100, |
| 0x3c290, 0xffffffff, 0x00000100, |
| 0x3c274, 0xffffffff, 0x00000100, |
| 0x3c2b4, 0xffffffff, 0x00000100, |
| 0x3c2b0, 0xffffffff, 0x00000100, |
| 0x3c270, 0xffffffff, 0x00000100, |
| 0x30800, 0xffffffff, 0xe0000000, |
| 0x3c020, 0xffffffff, 0x00010000, |
| 0x3c024, 0xffffffff, 0x00030002, |
| 0x3c028, 0xffffffff, 0x00040007, |
| 0x3c02c, 0xffffffff, 0x00060005, |
| 0x3c030, 0xffffffff, 0x00090008, |
| 0x3c034, 0xffffffff, 0x00010000, |
| 0x3c038, 0xffffffff, 0x00030002, |
| 0x3c03c, 0xffffffff, 0x00040007, |
| 0x3c040, 0xffffffff, 0x00060005, |
| 0x3c044, 0xffffffff, 0x00090008, |
| 0x3c000, 0xffffffff, 0x96e00200, |
| 0x8708, 0xffffffff, 0x00900100, |
| 0xc424, 0xffffffff, 0x0020003f, |
| 0x38, 0xffffffff, 0x0140001c, |
| 0x3c, 0x000f0000, 0x000f0000, |
| 0x220, 0xffffffff, 0xC060000C, |
| 0x224, 0xc0000fff, 0x00000100, |
| 0x20a8, 0xffffffff, 0x00000104, |
| 0x55e4, 0xff000fff, 0x00000100, |
| 0x30cc, 0xc0000fff, 0x00000104, |
| 0xc1e4, 0x00000001, 0x00000001, |
| 0xd00c, 0xff000ff0, 0x00000100, |
| 0xd80c, 0xff000ff0, 0x00000100 |
| }; |
| |
| static const u32 hawaii_golden_spm_registers[] = |
| { |
| 0x30800, 0xe0ffffff, 0xe0000000 |
| }; |
| |
| static const u32 hawaii_golden_common_registers[] = |
| { |
| 0x30800, 0xffffffff, 0xe0000000, |
| 0x28350, 0xffffffff, 0x3a00161a, |
| 0x28354, 0xffffffff, 0x0000002e, |
| 0x9a10, 0xffffffff, 0x00018208, |
| 0x98f8, 0xffffffff, 0x12011003 |
| }; |
| |
| static const u32 hawaii_golden_registers[] = |
| { |
| 0x3354, 0x00000333, 0x00000333, |
| 0x9a10, 0x00010000, 0x00058208, |
| 0x9830, 0xffffffff, 0x00000000, |
| 0x9834, 0xf00fffff, 0x00000400, |
| 0x9838, 0x0002021c, 0x00020200, |
| 0xc78, 0x00000080, 0x00000000, |
| 0x5bb0, 0x000000f0, 0x00000070, |
| 0x5bc0, 0xf0311fff, 0x80300000, |
| 0x350c, 0x00810000, 0x408af000, |
| 0x7030, 0x31000111, 0x00000011, |
| 0x2f48, 0x73773777, 0x12010001, |
| 0x2120, 0x0000007f, 0x0000001b, |
| 0x21dc, 0x00007fb6, 0x00002191, |
| 0x3628, 0x0000003f, 0x0000000a, |
| 0x362c, 0x0000003f, 0x0000000a, |
| 0x2ae4, 0x00073ffe, 0x000022a2, |
| 0x240c, 0x000007ff, 0x00000000, |
| 0x8bf0, 0x00002001, 0x00000001, |
| 0x8b24, 0xffffffff, 0x00ffffff, |
| 0x30a04, 0x0000ff0f, 0x00000000, |
| 0x28a4c, 0x07ffffff, 0x06000000, |
| 0x3e78, 0x00000001, 0x00000002, |
| 0xc768, 0x00000008, 0x00000008, |
| 0xc770, 0x00000f00, 0x00000800, |
| 0xc774, 0x00000f00, 0x00000800, |
| 0xc798, 0x00ffffff, 0x00ff7fbf, |
| 0xc79c, 0x00ffffff, 0x00ff7faf, |
| 0x8c00, 0x000000ff, 0x00000800, |
| 0xe40, 0x00001fff, 0x00001fff, |
| 0x9060, 0x0000007f, 0x00000020, |
| 0x9508, 0x00010000, 0x00010000, |
| 0xae00, 0x00100000, 0x000ff07c, |
| 0xac14, 0x000003ff, 0x0000000f, |
| 0xac10, 0xffffffff, 0x7564fdec, |
| 0xac0c, 0xffffffff, 0x3120b9a8, |
| 0xac08, 0x20000000, 0x0f9c0000 |
| }; |
| |
| static const u32 hawaii_mgcg_cgcg_init[] = |
| { |
| 0xc420, 0xffffffff, 0xfffffffd, |
| 0x30800, 0xffffffff, 0xe0000000, |
| 0x3c2a0, 0xffffffff, 0x00000100, |
| 0x3c208, 0xffffffff, 0x00000100, |
| 0x3c2c0, 0xffffffff, 0x00000100, |
| 0x3c2c8, 0xffffffff, 0x00000100, |
| 0x3c2c4, 0xffffffff, 0x00000100, |
| 0x55e4, 0xffffffff, 0x00200100, |
| 0x3c280, 0xffffffff, 0x00000100, |
| 0x3c214, 0xffffffff, 0x06000100, |
| 0x3c220, 0xffffffff, 0x00000100, |
| 0x3c218, 0xffffffff, 0x06000100, |
| 0x3c204, 0xffffffff, 0x00000100, |
| 0x3c2e0, 0xffffffff, 0x00000100, |
| 0x3c224, 0xffffffff, 0x00000100, |
| 0x3c200, 0xffffffff, 0x00000100, |
| 0x3c230, 0xffffffff, 0x00000100, |
| 0x3c234, 0xffffffff, 0x00000100, |
| 0x3c250, 0xffffffff, 0x00000100, |
| 0x3c254, 0xffffffff, 0x00000100, |
| 0x3c258, 0xffffffff, 0x00000100, |
| 0x3c25c, 0xffffffff, 0x00000100, |
| 0x3c260, 0xffffffff, 0x00000100, |
| 0x3c27c, 0xffffffff, 0x00000100, |
| 0x3c278, 0xffffffff, 0x00000100, |
| 0x3c210, 0xffffffff, 0x06000100, |
| 0x3c290, 0xffffffff, 0x00000100, |
| 0x3c274, 0xffffffff, 0x00000100, |
| 0x3c2b4, 0xffffffff, 0x00000100, |
| 0x3c2b0, 0xffffffff, 0x00000100, |
| 0x3c270, 0xffffffff, 0x00000100, |
| 0x30800, 0xffffffff, 0xe0000000, |
| 0x3c020, 0xffffffff, 0x00010000, |
| 0x3c024, 0xffffffff, 0x00030002, |
| 0x3c028, 0xffffffff, 0x00040007, |
| 0x3c02c, 0xffffffff, 0x00060005, |
| 0x3c030, 0xffffffff, 0x00090008, |
| 0x3c034, 0xffffffff, 0x00010000, |
| 0x3c038, 0xffffffff, 0x00030002, |
| 0x3c03c, 0xffffffff, 0x00040007, |
| 0x3c040, 0xffffffff, 0x00060005, |
| 0x3c044, 0xffffffff, 0x00090008, |
| 0x3c048, 0xffffffff, 0x00010000, |
| 0x3c04c, 0xffffffff, 0x00030002, |
| 0x3c050, 0xffffffff, 0x00040007, |
| 0x3c054, 0xffffffff, 0x00060005, |
| 0x3c058, 0xffffffff, 0x00090008, |
| 0x3c05c, 0xffffffff, 0x00010000, |
| 0x3c060, 0xffffffff, 0x00030002, |
| 0x3c064, 0xffffffff, 0x00040007, |
| 0x3c068, 0xffffffff, 0x00060005, |
| 0x3c06c, 0xffffffff, 0x00090008, |
| 0x3c070, 0xffffffff, 0x00010000, |
| 0x3c074, 0xffffffff, 0x00030002, |
| 0x3c078, 0xffffffff, 0x00040007, |
| 0x3c07c, 0xffffffff, 0x00060005, |
| 0x3c080, 0xffffffff, 0x00090008, |
| 0x3c084, 0xffffffff, 0x00010000, |
| 0x3c088, 0xffffffff, 0x00030002, |
| 0x3c08c, 0xffffffff, 0x00040007, |
| 0x3c090, 0xffffffff, 0x00060005, |
| 0x3c094, 0xffffffff, 0x00090008, |
| 0x3c098, 0xffffffff, 0x00010000, |
| 0x3c09c, 0xffffffff, 0x00030002, |
| 0x3c0a0, 0xffffffff, 0x00040007, |
| 0x3c0a4, 0xffffffff, 0x00060005, |
| 0x3c0a8, 0xffffffff, 0x00090008, |
| 0x3c0ac, 0xffffffff, 0x00010000, |
| 0x3c0b0, 0xffffffff, 0x00030002, |
| 0x3c0b4, 0xffffffff, 0x00040007, |
| 0x3c0b8, 0xffffffff, 0x00060005, |
| 0x3c0bc, 0xffffffff, 0x00090008, |
| 0x3c0c0, 0xffffffff, 0x00010000, |
| 0x3c0c4, 0xffffffff, 0x00030002, |
| 0x3c0c8, 0xffffffff, 0x00040007, |
| 0x3c0cc, 0xffffffff, 0x00060005, |
| 0x3c0d0, 0xffffffff, 0x00090008, |
| 0x3c0d4, 0xffffffff, 0x00010000, |
| 0x3c0d8, 0xffffffff, 0x00030002, |
| 0x3c0dc, 0xffffffff, 0x00040007, |
| 0x3c0e0, 0xffffffff, 0x00060005, |
| 0x3c0e4, 0xffffffff, 0x00090008, |
| 0x3c0e8, 0xffffffff, 0x00010000, |
| 0x3c0ec, 0xffffffff, 0x00030002, |
| 0x3c0f0, 0xffffffff, 0x00040007, |
| 0x3c0f4, 0xffffffff, 0x00060005, |
| 0x3c0f8, 0xffffffff, 0x00090008, |
| 0xc318, 0xffffffff, 0x00020200, |
| 0x3350, 0xffffffff, 0x00000200, |
| 0x15c0, 0xffffffff, 0x00000400, |
| 0x55e8, 0xffffffff, 0x00000000, |
| 0x2f50, 0xffffffff, 0x00000902, |
| 0x3c000, 0xffffffff, 0x96940200, |
| 0x8708, 0xffffffff, 0x00900100, |
| 0xc424, 0xffffffff, 0x0020003f, |
| 0x38, 0xffffffff, 0x0140001c, |
| 0x3c, 0x000f0000, 0x000f0000, |
| 0x220, 0xffffffff, 0xc060000c, |
| 0x224, 0xc0000fff, 0x00000100, |
| 0xf90, 0xffffffff, 0x00000100, |
| 0xf98, 0x00000101, 0x00000000, |
| 0x20a8, 0xffffffff, 0x00000104, |
| 0x55e4, 0xff000fff, 0x00000100, |
| 0x30cc, 0xc0000fff, 0x00000104, |
| 0xc1e4, 0x00000001, 0x00000001, |
| 0xd00c, 0xff000ff0, 0x00000100, |
| 0xd80c, 0xff000ff0, 0x00000100 |
| }; |
| |
| static const u32 godavari_golden_registers[] = |
| { |
| 0x55e4, 0xff607fff, 0xfc000100, |
| 0x6ed8, 0x00010101, 0x00010000, |
| 0x9830, 0xffffffff, 0x00000000, |
| 0x98302, 0xf00fffff, 0x00000400, |
| 0x6130, 0xffffffff, 0x00010000, |
| 0x5bb0, 0x000000f0, 0x00000070, |
| 0x5bc0, 0xf0311fff, 0x80300000, |
| 0x98f8, 0x73773777, 0x12010001, |
| 0x98fc, 0xffffffff, 0x00000010, |
| 0x8030, 0x00001f0f, 0x0000100a, |
| 0x2f48, 0x73773777, 0x12010001, |
| 0x2408, 0x000fffff, 0x000c007f, |
| 0x8a14, 0xf000003f, 0x00000007, |
| 0x8b24, 0xffffffff, 0x00ff0fff, |
| 0x30a04, 0x0000ff0f, 0x00000000, |
| 0x28a4c, 0x07ffffff, 0x06000000, |
| 0x4d8, 0x00000fff, 0x00000100, |
| 0xd014, 0x00010000, 0x00810001, |
| 0xd814, 0x00010000, 0x00810001, |
| 0x3e78, 0x00000001, 0x00000002, |
| 0xc768, 0x00000008, 0x00000008, |
| 0xc770, 0x00000f00, 0x00000800, |
| 0xc774, 0x00000f00, 0x00000800, |
| 0xc798, 0x00ffffff, 0x00ff7fbf, |
| 0xc79c, 0x00ffffff, 0x00ff7faf, |
| 0x8c00, 0x000000ff, 0x00000001, |
| 0x214f8, 0x01ff01ff, 0x00000002, |
| 0x21498, 0x007ff800, 0x00200000, |
| 0x2015c, 0xffffffff, 0x00000f40, |
| 0x88c4, 0x001f3ae3, 0x00000082, |
| 0x88d4, 0x0000001f, 0x00000010, |
| 0x30934, 0xffffffff, 0x00000000 |
| }; |
| |
| |
| static void cik_init_golden_registers(struct radeon_device *rdev) |
| { |
| /* Some of the registers might be dependent on GRBM_GFX_INDEX */ |
| mutex_lock(&rdev->grbm_idx_mutex); |
| switch (rdev->family) { |
| case CHIP_BONAIRE: |
| radeon_program_register_sequence(rdev, |
| bonaire_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init)); |
| radeon_program_register_sequence(rdev, |
| bonaire_golden_registers, |
| (const u32)ARRAY_SIZE(bonaire_golden_registers)); |
| radeon_program_register_sequence(rdev, |
| bonaire_golden_common_registers, |
| (const u32)ARRAY_SIZE(bonaire_golden_common_registers)); |
| radeon_program_register_sequence(rdev, |
| bonaire_golden_spm_registers, |
| (const u32)ARRAY_SIZE(bonaire_golden_spm_registers)); |
| break; |
| case CHIP_KABINI: |
| radeon_program_register_sequence(rdev, |
| kalindi_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); |
| radeon_program_register_sequence(rdev, |
| kalindi_golden_registers, |
| (const u32)ARRAY_SIZE(kalindi_golden_registers)); |
| radeon_program_register_sequence(rdev, |
| kalindi_golden_common_registers, |
| (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); |
| radeon_program_register_sequence(rdev, |
| kalindi_golden_spm_registers, |
| (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); |
| break; |
| case CHIP_MULLINS: |
| radeon_program_register_sequence(rdev, |
| kalindi_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); |
| radeon_program_register_sequence(rdev, |
| godavari_golden_registers, |
| (const u32)ARRAY_SIZE(godavari_golden_registers)); |
| radeon_program_register_sequence(rdev, |
| kalindi_golden_common_registers, |
| (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); |
| radeon_program_register_sequence(rdev, |
| kalindi_golden_spm_registers, |
| (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); |
| break; |
| case CHIP_KAVERI: |
| radeon_program_register_sequence(rdev, |
| spectre_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init)); |
| radeon_program_register_sequence(rdev, |
| spectre_golden_registers, |
| (const u32)ARRAY_SIZE(spectre_golden_registers)); |
| radeon_program_register_sequence(rdev, |
| spectre_golden_common_registers, |
| (const u32)ARRAY_SIZE(spectre_golden_common_registers)); |
| radeon_program_register_sequence(rdev, |
| spectre_golden_spm_registers, |
| (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); |
| break; |
| case CHIP_HAWAII: |
| radeon_program_register_sequence(rdev, |
| hawaii_mgcg_cgcg_init, |
| (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); |
| radeon_program_register_sequence(rdev, |
| hawaii_golden_registers, |
| (const u32)ARRAY_SIZE(hawaii_golden_registers)); |
| radeon_program_register_sequence(rdev, |
| hawaii_golden_common_registers, |
| (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); |
| radeon_program_register_sequence(rdev, |
| hawaii_golden_spm_registers, |
| (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); |
| break; |
| default: |
| break; |
| } |
| mutex_unlock(&rdev->grbm_idx_mutex); |
| } |
| |
| /** |
| * cik_get_xclk - get the xclk |
| * |
| * @rdev: radeon_device pointer |
| * |
| * Returns the reference clock used by the gfx engine |
| * (CIK). |
| */ |
| u32 cik_get_xclk(struct radeon_device *rdev) |
| { |
| u32 reference_clock = rdev->clock.spll.reference_freq; |
| |
| if (rdev->flags & RADEON_IS_IGP) { |
| if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK) |
| return reference_clock / 2; |
| } else { |
| if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE) |
| return reference_clock / 4; |
| } |
| return reference_clock; |
| } |
| |
| /** |
| * cik_mm_rdoorbell - read a doorbell dword |
| * |
| * @rdev: radeon_device pointer |
| * @index: doorbell index |
| * |
| * Returns the value in the doorbell aperture at the |
| * requested doorbell index (CIK). |
| */ |
| u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index) |
| { |
| if (index < rdev->doorbell.num_doorbells) { |
| return readl(rdev->doorbell.ptr + index); |
| } else { |
| DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); |
| return 0; |
| } |
| } |
| |
| /** |
| * cik_mm_wdoorbell - write a doorbell dword |
| * |
| * @rdev: radeon_device pointer |
| * @index: doorbell index |
| * @v: value to write |
| * |
| * Writes @v to the doorbell aperture at the |
| * requested doorbell index (CIK). |
| */ |
| void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v) |
| { |
| if (index < rdev->doorbell.num_doorbells) { |
| writel(v, rdev->doorbell.ptr + index); |
| } else { |
| DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); |
| } |
| } |
| |
| #define BONAIRE_IO_MC_REGS_SIZE 36 |
| |
| static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] = |
| { |
| {0x00000070, 0x04400000}, |
| {0x00000071, 0x80c01803}, |
| {0x00000072, 0x00004004}, |
| {0x00000073, 0x00000100}, |
| {0x00000074, 0x00ff0000}, |
| {0x00000075, 0x34000000}, |
| {0x00000076, 0x08000014}, |
| {0x00000077, 0x00cc08ec}, |
| {0x00000078, 0x00000400}, |
| {0x00000079, 0x00000000}, |
| {0x0000007a, 0x04090000}, |
| {0x0000007c, 0x00000000}, |
| {0x0000007e, 0x4408a8e8}, |
| {0x0000007f, 0x00000304}, |
| {0x00000080, 0x00000000}, |
| {0x00000082, 0x00000001}, |
| {0x00000083, 0x00000002}, |
| {0x00000084, 0xf3e4f400}, |
| {0x00000085, 0x052024e3}, |
| {0x00000087, 0x00000000}, |
| {0x00000088, 0x01000000}, |
| {0x0000008a, 0x1c0a0000}, |
| {0x0000008b, 0xff010000}, |
| {0x0000008d, 0xffffefff}, |
| {0x0000008e, 0xfff3efff}, |
| {0x0000008f, 0xfff3efbf}, |
| {0x00000092, 0xf7ffffff}, |
| {0x00000093, 0xffffff7f}, |
| {0x00000095, 0x00101101}, |
| {0x00000096, 0x00000fff}, |
| {0x00000097, 0x00116fff}, |
| {0x00000098, 0x60010000}, |
| {0x00000099, 0x10010000}, |
| {0x0000009a, 0x00006000}, |
| {0x0000009b, 0x00001000}, |
| {0x0000009f, 0x00b48000} |
| }; |
| |
| #define HAWAII_IO_MC_REGS_SIZE 22 |
| |
| static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] = |
| { |
| {0x0000007d, 0x40000000}, |
| {0x0000007e, 0x40180304}, |
| {0x0000007f, 0x0000ff00}, |
| {0x00000081, 0x00000000}, |
| {0x00000083, 0x00000800}, |
| {0x00000086, 0x00000000}, |
| {0x00000087, 0x00000100}, |
| {0x00000088, 0x00020100}, |
| {0x00000089, 0x00000000}, |
| {0x0000008b, 0x00040000}, |
| {0x0000008c, 0x00000100}, |
| {0x0000008e, 0xff010000}, |
| {0x00000090, 0xffffefff}, |
| {0x00000091, 0xfff3efff}, |
| {0x00000092, 0xfff3efbf}, |
| {0x00000093, 0xf7ffffff}, |
| {0x00000094, 0xffffff7f}, |
| {0x00000095, 0x00000fff}, |
| {0x00000096, 0x00116fff}, |
| {0x00000097, 0x60010000}, |
| {0x00000098, 0x10010000}, |
| {0x0000009f, 0x00c79000} |
| }; |
| |
| |
| /** |
| * cik_srbm_select - select specific register instances |
| * |
| * @rdev: radeon_device pointer |
| * @me: selected ME (micro engine) |
| * @pipe: pipe |
| * @queue: queue |
| * @vmid: VMID |
| * |
| * Switches the currently active registers instances. Some |
| * registers are instanced per VMID, others are instanced per |
| * me/pipe/queue combination. |
| */ |
| static void cik_srbm_select(struct radeon_device *rdev, |
| u32 me, u32 pipe, u32 queue, u32 vmid) |
| { |
| u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) | |
| MEID(me & 0x3) | |
| VMID(vmid & 0xf) | |
| QUEUEID(queue & 0x7)); |
| WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); |
| } |
| |
| /* ucode loading */ |
| /** |
| * ci_mc_load_microcode - load MC ucode into the hw |
| * |
| * @rdev: radeon_device pointer |
| * |
| * Load the GDDR MC ucode into the hw (CIK). |
| * Returns 0 on success, error on failure. |
| */ |
| int ci_mc_load_microcode(struct radeon_device *rdev) |
| { |
| const __be32 *fw_data = NULL; |
| const __le32 *new_fw_data = NULL; |
| u32 running, tmp; |
| u32 *io_mc_regs = NULL; |
| const __le32 *new_io_mc_regs = NULL; |
| int i, regs_size, ucode_size; |
| |
| if (!rdev->mc_fw) |
| return -EINVAL; |
| |
| if (rdev->new_fw) { |
| const struct mc_firmware_header_v1_0 *hdr = |
| (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data; |
| |
| radeon_ucode_print_mc_hdr(&hdr->header); |
| |
| regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); |
| new_io_mc_regs = (const __le32 *) |
| (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); |
| ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
| new_fw_data = (const __le32 *) |
| (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
| } else { |
| ucode_size = rdev->mc_fw->size / 4; |
| |
| switch (rdev->family) { |
| case CHIP_BONAIRE: |
| io_mc_regs = (u32 *)&bonaire_io_mc_regs; |
| regs_size = BONAIRE_IO_MC_REGS_SIZE; |
| break; |
| case CHIP_HAWAII: |
| io_mc_regs = (u32 *)&hawaii_io_mc_regs; |
| regs_size = HAWAII_IO_MC_REGS_SIZE; |
| break; |
| default: |
| return -EINVAL; |
| } |
| fw_data = (const __be32 *)rdev->mc_fw->data; |
| } |
| |
| running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; |
| |
| if (running == 0) { |
| /* reset the engine and set to writable */ |
| WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
| WREG32(MC_SEQ_SUP_CNTL, 0x00000010); |
| |
| /* load mc io regs */ |
| for (i = 0; i < regs_size; i++) { |
| if (rdev->new_fw) { |
| WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); |
| WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); |
| } else { |
| WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); |
| WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); |
| } |
| } |
| |
| tmp = RREG32(MC_SEQ_MISC0); |
| if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) { |
| WREG32(MC_SEQ_IO_DEBUG_INDEX, 5); |
| WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023); |
| WREG32(MC_SEQ_IO_DEBUG_INDEX, 9); |
| WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0); |
| } |
| |
| /* load the MC ucode */ |
| for (i = 0; i < ucode_size; i++) { |
| if (rdev->new_fw) |
| WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); |
| else |
| WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); |
| } |
| |
| /* put the engine back into the active state */ |
| WREG32(MC_SEQ_SUP_CNTL, 0x00000008); |
| WREG32(MC_SEQ_SUP_CNTL, 0x00000004); |
| WREG32(MC_SEQ_SUP_CNTL, 0x00000001); |
| |
| /* wait for training to complete */ |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) |
| break; |
| udelay(1); |
| } |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) |
| break; |
| udelay(1); |
| } |
| } |
| |
| return 0; |
| } |
| |
| /** |
| * cik_init_microcode - load ucode images from disk |
| * |
| * @rdev: radeon_device pointer |
| * |
| * Use the firmware interface to load the ucode images into |
| * the driver (not loaded into hw). |
| * Returns 0 on success, error on failure. |
| */ |
| static int cik_init_microcode(struct radeon_device *rdev) |
| { |
| const char *chip_name; |
| const char *new_chip_name; |
| size_t pfp_req_size, me_req_size, ce_req_size, |
| mec_req_size, rlc_req_size, mc_req_size = 0, |
| sdma_req_size, smc_req_size = 0, mc2_req_size = 0; |
| char fw_name[30]; |
| int new_fw = 0; |
| int err; |
| int num_fw; |
| bool new_smc = false; |
| |
| DRM_DEBUG("\n"); |
| |
| switch (rdev->family) { |
| case CHIP_BONAIRE: |
| chip_name = "BONAIRE"; |
| if ((rdev->pdev->revision == 0x80) || |
| (rdev->pdev->revision == 0x81) || |
| (rdev->pdev->device == 0x665f)) |
| new_smc = true; |
| new_chip_name = "bonaire"; |
| pfp_req_size = CIK_PFP_UCODE_SIZE * 4; |
| me_req_size = CIK_ME_UCODE_SIZE * 4; |
| ce_req_size = CIK_CE_UCODE_SIZE * 4; |
| mec_req_size = CIK_MEC_UCODE_SIZE * 4; |
| rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4; |
| mc_req_size = BONAIRE_MC_UCODE_SIZE * 4; |
| mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4; |
| sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; |
| smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4); |
| num_fw = 8; |
| break; |
| case CHIP_HAWAII: |
| chip_name = "HAWAII"; |
| if (rdev->pdev->revision == 0x80) |
| new_smc = true; |
| new_chip_name = "hawaii"; |
| pfp_req_size = CIK_PFP_UCODE_SIZE * 4; |
| me_req_size = CIK_ME_UCODE_SIZE * 4; |
| ce_req_size = CIK_CE_UCODE_SIZE * 4; |
| mec_req_size = CIK_MEC_UCODE_SIZE * 4; |
| rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4; |
| mc_req_size = HAWAII_MC_UCODE_SIZE * 4; |
| mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4; |
| sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; |
| smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4); |
| num_fw = 8; |
| break; |
| case CHIP_KAVERI: |
| chip_name = "KAVERI"; |
| new_chip_name = "kaveri"; |
| pfp_req_size = CIK_PFP_UCODE_SIZE * 4; |
| me_req_size = CIK_ME_UCODE_SIZE * 4; |
| ce_req_size = CIK_CE_UCODE_SIZE * 4; |
| mec_req_size = CIK_MEC_UCODE_SIZE * 4; |
| rlc_req_size = KV_RLC_UCODE_SIZE * 4; |
| sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; |
| num_fw = 7; |
| break; |
| case CHIP_KABINI: |
| chip_name = "KABINI"; |
| new_chip_name = "kabini"; |
| pfp_req_size = CIK_PFP_UCODE_SIZE * 4; |
| me_req_size = CIK_ME_UCODE_SIZE * 4; |
| ce_req_size = CIK_CE_UCODE_SIZE * 4; |
| mec_req_size = CIK_MEC_UCODE_SIZE * 4; |
| rlc_req_size = KB_RLC_UCODE_SIZE * 4; |
| sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; |
| num_fw = 6; |
| break; |
| case CHIP_MULLINS: |
| chip_name = "MULLINS"; |
| new_chip_name = "mullins"; |
| pfp_req_size = CIK_PFP_UCODE_SIZE * 4; |
| me_req_size = CIK_ME_UCODE_SIZE * 4; |
| ce_req_size = CIK_CE_UCODE_SIZE * 4; |
| mec_req_size = CIK_MEC_UCODE_SIZE * 4; |
| rlc_req_size = ML_RLC_UCODE_SIZE * 4; |
| sdma_req_size = CIK_SDMA_UCODE_SIZE * 4; |
| num_fw = 6; |
| break; |
| default: BUG(); |
| } |
| |
| DRM_INFO("Loading %s Microcode\n", new_chip_name); |
| |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name); |
| err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); |
| if (err) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
| err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); |
| if (err) |
| goto out; |
| if (rdev->pfp_fw->size != pfp_req_size) { |
| pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n", |
| rdev->pfp_fw->size, fw_name); |
| err = -EINVAL; |
| goto out; |
| } |
| } else { |
| err = radeon_ucode_validate(rdev->pfp_fw); |
| if (err) { |
| pr_err("cik_fw: validation failed for firmware \"%s\"\n", |
| fw_name); |
| goto out; |
| } else { |
| new_fw++; |
| } |
| } |
| |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name); |
| err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); |
| if (err) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
| err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); |
| if (err) |
| goto out; |
| if (rdev->me_fw->size != me_req_size) { |
| pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n", |
| rdev->me_fw->size, fw_name); |
| err = -EINVAL; |
| } |
| } else { |
| err = radeon_ucode_validate(rdev->me_fw); |
| if (err) { |
| pr_err("cik_fw: validation failed for firmware \"%s\"\n", |
| fw_name); |
| goto out; |
| } else { |
| new_fw++; |
| } |
| } |
| |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name); |
| err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev); |
| if (err) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); |
| err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev); |
| if (err) |
| goto out; |
| if (rdev->ce_fw->size != ce_req_size) { |
| pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n", |
| rdev->ce_fw->size, fw_name); |
| err = -EINVAL; |
| } |
| } else { |
| err = radeon_ucode_validate(rdev->ce_fw); |
| if (err) { |
| pr_err("cik_fw: validation failed for firmware \"%s\"\n", |
| fw_name); |
| goto out; |
| } else { |
| new_fw++; |
| } |
| } |
| |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", new_chip_name); |
| err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev); |
| if (err) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); |
| err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev); |
| if (err) |
| goto out; |
| if (rdev->mec_fw->size != mec_req_size) { |
| pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n", |
| rdev->mec_fw->size, fw_name); |
| err = -EINVAL; |
| } |
| } else { |
| err = radeon_ucode_validate(rdev->mec_fw); |
| if (err) { |
| pr_err("cik_fw: validation failed for firmware \"%s\"\n", |
| fw_name); |
| goto out; |
| } else { |
| new_fw++; |
| } |
| } |
| |
| if (rdev->family == CHIP_KAVERI) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", new_chip_name); |
| err = request_firmware(&rdev->mec2_fw, fw_name, rdev->dev); |
| if (err) { |
| goto out; |
| } else { |
| err = radeon_ucode_validate(rdev->mec2_fw); |
| if (err) { |
| goto out; |
| } else { |
| new_fw++; |
| } |
| } |
| } |
| |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name); |
| err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); |
| if (err) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); |
| err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); |
| if (err) |
| goto out; |
| if (rdev->rlc_fw->size != rlc_req_size) { |
| pr_err("cik_rlc: Bogus length %zu in firmware \"%s\"\n", |
| rdev->rlc_fw->size, fw_name); |
| err = -EINVAL; |
| } |
| } else { |
| err = radeon_ucode_validate(rdev->rlc_fw); |
| if (err) { |
| pr_err("cik_fw: validation failed for firmware \"%s\"\n", |
| fw_name); |
| goto out; |
| } else { |
| new_fw++; |
| } |
| } |
| |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", new_chip_name); |
| err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev); |
| if (err) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); |
| err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev); |
| if (err) |
| goto out; |
| if (rdev->sdma_fw->size != sdma_req_size) { |
| pr_err("cik_sdma: Bogus length %zu in firmware \"%s\"\n", |
| rdev->sdma_fw->size, fw_name); |
| err = -EINVAL; |
| } |
| } else { |
| err = radeon_ucode_validate(rdev->sdma_fw); |
| if (err) { |
| pr_err("cik_fw: validation failed for firmware \"%s\"\n", |
| fw_name); |
| goto out; |
| } else { |
| new_fw++; |
| } |
| } |
| |
| /* No SMC, MC ucode on APUs */ |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name); |
| err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); |
| if (err) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name); |
| err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); |
| if (err) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
| err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); |
| if (err) |
| goto out; |
| } |
| if ((rdev->mc_fw->size != mc_req_size) && |
| (rdev->mc_fw->size != mc2_req_size)){ |
| pr_err("cik_mc: Bogus length %zu in firmware \"%s\"\n", |
| rdev->mc_fw->size, fw_name); |
| err = -EINVAL; |
| } |
| DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size); |
| } else { |
| err = radeon_ucode_validate(rdev->mc_fw); |
| if (err) { |
| pr_err("cik_fw: validation failed for firmware \"%s\"\n", |
| fw_name); |
| goto out; |
| } else { |
| new_fw++; |
| } |
| } |
| |
| if (new_smc) |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_k_smc.bin", new_chip_name); |
| else |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name); |
| err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); |
| if (err) { |
| snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); |
| err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); |
| if (err) { |
| pr_err("smc: error loading firmware \"%s\"\n", |
| fw_name); |
| release_firmware(rdev->smc_fw); |
| rdev->smc_fw = NULL; |
| err = 0; |
| } else if (rdev->smc_fw->size != smc_req_size) { |
| pr_err("cik_smc: Bogus length %zu in firmware \"%s\"\n", |
| rdev->smc_fw->size, fw_name); |
| err = -EINVAL; |
| } |
| } else { |
| err = radeon_ucode_validate(rdev->smc_fw); |
| if (err) { |
| pr_err("cik_fw: validation failed for firmware \"%s\"\n", |
| fw_name); |
| goto out; |
| } else { |
| new_fw++; |
| } |
| } |
| } |
| |
| if (new_fw == 0) { |
| rdev->new_fw = false; |
| } else if (new_fw < num_fw) { |
| pr_err("ci_fw: mixing new and old firmware!\n"); |
| err = -EINVAL; |
| } else { |
| rdev->new_fw = true; |
| } |
| |
| out: |
| if (err) { |
| if (err != -EINVAL) |
| pr_err("cik_cp: Failed to load firmware \"%s\"\n", |
| fw_name); |
| release_firmware(rdev->pfp_fw); |
| rdev->pfp_fw = NULL; |
| release_firmware(rdev->me_fw); |
| rdev->me_fw = NULL; |
| release_firmware(rdev->ce_fw); |
| rdev->ce_fw = NULL; |
| release_firmware(rdev->mec_fw); |
| rdev->mec_fw = NULL; |
| release_firmware(rdev->mec2_fw); |
| rdev->mec2_fw = NULL; |
| release_firmware(rdev->rlc_fw); |
| rdev->rlc_fw = NULL; |
| release_firmware(rdev->sdma_fw); |
| rdev->sdma_fw = NULL; |
| release_firmware(rdev->mc_fw); |
| rdev->mc_fw = NULL; |
| release_firmware(rdev->smc_fw); |
| rdev->smc_fw = NULL; |
| } |
| return err; |
| } |
| |
| /* |
| * Core functions |
| */ |
| /** |
| * cik_tiling_mode_table_init - init the hw tiling table |
| * |
| * @rdev: radeon_device pointer |
| * |
| * Starting with SI, the tiling setup is done globally in a |
| * set of 32 tiling modes. Rather than selecting each set of |
| * parameters per surface as on older asics, we just select |
| * which index in the tiling table we want to use, and the |
| * surface uses those parameters (CIK). |
| */ |
| static void cik_tiling_mode_table_init(struct radeon_device *rdev) |
| { |
| u32 *tile = rdev->config.cik.tile_mode_array; |
| u32 *macrotile = rdev->config.cik.macrotile_mode_array; |
| const u32 num_tile_mode_states = |
| ARRAY_SIZE(rdev->config.cik.tile_mode_array); |
| const u32 num_secondary_tile_mode_states = |
| ARRAY_SIZE(rdev->config.cik.macrotile_mode_array); |
| u32 reg_offset, split_equal_to_row_size; |
| u32 num_pipe_configs; |
| u32 num_rbs = rdev->config.cik.max_backends_per_se * |
| rdev->config.cik.max_shader_engines; |
| |
| switch (rdev->config.cik.mem_row_size_in_kb) { |
| case 1: |
| split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; |
| break; |
| case 2: |
| default: |
| split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; |
| break; |
| case 4: |
| split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; |
| break; |
| } |
| |
| num_pipe_configs = rdev->config.cik.max_tile_pipes; |
| if (num_pipe_configs > 8) |
| num_pipe_configs = 16; |
| |
| for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
| tile[reg_offset] = 0; |
| for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
| macrotile[reg_offset] = 0; |
| |
| switch(num_pipe_configs) { |
| case 16: |
| tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); |
| tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); |
| tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); |
| tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(split_equal_to_row_size)); |
| tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| TILE_SPLIT(split_equal_to_row_size)); |
| tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); |
| tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); |
| tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); |
| tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); |
| tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | |
| SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| |
| macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_4_BANK)); |
| macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_2_BANK)); |
| macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_16_BANK)); |
| macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_8_BANK)); |
| macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_4_BANK)); |
| macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_2_BANK)); |
| macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| NUM_BANKS(ADDR_SURF_2_BANK)); |
| |
| for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
| WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); |
| for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
| WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); |
| break; |
| |
| case 8: |
| tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); |
| tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)); |
| tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)); |
| tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(split_equal_to_row_size)); |
| tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)); |
| tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| TILE_SPLIT(split_equal_to_row_size)); |
| tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); |
| tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); |
| tile[10] = (ARRAY_MODE(ARRAY_2D
|
