| * AT91 SAMA5D2 Analog to Digital Converter (ADC) |
| |
| Required properties: |
| - compatible: Should be "atmel,sama5d2-adc". |
| - reg: Should contain ADC registers location and length. |
| - interrupts: Should contain the IRQ line for the ADC. |
| - clocks: phandle to device clock. |
| - clock-names: Must be "adc_clk". |
| - vref-supply: Supply used as reference for conversions. |
| - vddana-supply: Supply for the adc device. |
| - atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC. |
| - atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC. |
| - atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC. |
| - atmel,trigger-edge-type: One of possible edge types for the ADTRG hardware |
| trigger pin. When the specific edge type is detected, the conversion will |
| start. Possible values are rising, falling, or both. |
| This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING , |
| IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH |
| |
| Example: |
| |
| adc: adc@fc030000 { |
| compatible = "atmel,sama5d2-adc"; |
| reg = <0xfc030000 0x100>; |
| interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; |
| clocks = <&adc_clk>; |
| clock-names = "adc_clk"; |
| atmel,min-sample-rate-hz = <200000>; |
| atmel,max-sample-rate-hz = <20000000>; |
| atmel,startup-time-ms = <4>; |
| vddana-supply = <&vdd_3v3_lp_reg>; |
| vref-supply = <&vdd_3v3_lp_reg>; |
| atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>; |
| } |
