Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt

* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers

Required properties:
- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
- reg: should contain IC registers location and length.
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: the number of cells to define an interrupt, should be 2.
  The first cell is the IRQ number, the second cell is used to specify
  one of the supported IRQ types:
      IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
      IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
      IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
      IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
  Reset value is IRQ_TYPE_LEVEL_LOW.

Optional properties:
- interrupt-parent: empty for MIC interrupt controller, link to parent
  MIC interrupt controller for SIC1 and SIC2
- interrupts: empty for MIC interrupt controller, cascaded MIC
  hardware interrupts for SIC1 and SIC2

Examples:

	/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
	mic: interrupt-controller@40008000 {
		compatible = "nxp,lpc3220-mic";
		reg = <0x40008000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	sic1: interrupt-controller@4000c000 {
		compatible = "nxp,lpc3220-sic";
		reg = <0x4000c000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <2>;

		interrupt-parent = <&mic>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
			     <30 IRQ_TYPE_LEVEL_LOW>;
	};

	sic2: interrupt-controller@40010000 {
		compatible = "nxp,lpc3220-sic";
		reg = <0x40010000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <2>;

		interrupt-parent = <&mic>;
		interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
			     <31 IRQ_TYPE_LEVEL_LOW>;
	};

	/* ADC */
	adc@40048000 {
		compatible = "nxp,lpc3220-adc";
		reg = <0x40048000 0x1000>;
		interrupt-parent = <&sic1>;
		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
	};