| /* | |
| * SAMSUNG EXYNOS7 SoC device tree source | |
| * | |
| * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
| * http://www.samsung.com | |
| * | |
| * This program is free software; you can redistribute it and/or modify | |
| * it under the terms of the GNU General Public License version 2 as | |
| * published by the Free Software Foundation. | |
| */ | |
| #include <dt-bindings/clock/exynos7-clk.h> | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| / { | |
| compatible = "samsung,exynos7"; | |
| interrupt-parent = <&gic>; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| aliases { | |
| pinctrl0 = &pinctrl_alive; | |
| pinctrl1 = &pinctrl_bus0; | |
| pinctrl2 = &pinctrl_nfc; | |
| pinctrl3 = &pinctrl_touch; | |
| pinctrl4 = &pinctrl_ff; | |
| pinctrl5 = &pinctrl_ese; | |
| pinctrl6 = &pinctrl_fsys0; | |
| pinctrl7 = &pinctrl_fsys1; | |
| pinctrl8 = &pinctrl_bus1; | |
| tmuctrl0 = &tmuctrl_0; | |
| }; | |
| cpus { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a57", "arm,armv8"; | |
| reg = <0x0>; | |
| enable-method = "psci"; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a57", "arm,armv8"; | |
| reg = <0x1>; | |
| enable-method = "psci"; | |
| }; | |
| cpu@2 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a57", "arm,armv8"; | |
| reg = <0x2>; | |
| enable-method = "psci"; | |
| }; | |
| cpu@3 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a57", "arm,armv8"; | |
| reg = <0x3>; | |
| enable-method = "psci"; | |
| }; | |
| }; | |
| psci { | |
| compatible = "arm,psci-0.2"; | |
| method = "smc"; | |
| }; | |
| soc: soc { | |
| compatible = "simple-bus"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges = <0 0 0 0x18000000>; | |
| chipid@10000000 { | |
| compatible = "samsung,exynos4210-chipid"; | |
| reg = <0x10000000 0x100>; | |
| }; | |
| fin_pll: xxti { | |
| compatible = "fixed-clock"; | |
| clock-output-names = "fin_pll"; | |
| #clock-cells = <0>; | |
| }; | |
| gic: interrupt-controller@11001000 { | |
| compatible = "arm,gic-400"; | |
| #interrupt-cells = <3>; | |
| #address-cells = <0>; | |
| interrupt-controller; | |
| reg = <0x11001000 0x1000>, | |
| <0x11002000 0x1000>, | |
| <0x11004000 0x2000>, | |
| <0x11006000 0x2000>; | |
| }; | |
| amba { | |
| compatible = "simple-bus"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges; | |
| pdma0: pdma@10E10000 { | |
| compatible = "arm,pl330", "arm,primecell"; | |
| reg = <0x10E10000 0x1000>; | |
| interrupts = <0 225 0>; | |
| clocks = <&clock_fsys0 ACLK_PDMA0>; | |
| clock-names = "apb_pclk"; | |
| #dma-cells = <1>; | |
| #dma-channels = <8>; | |
| #dma-requests = <32>; | |
| }; | |
| pdma1: pdma@10EB0000 { | |
| compatible = "arm,pl330", "arm,primecell"; | |
| reg = <0x10EB0000 0x1000>; | |
| interrupts = <0 226 0>; | |
| clocks = <&clock_fsys0 ACLK_PDMA1>; | |
| clock-names = "apb_pclk"; | |
| #dma-cells = <1>; | |
| #dma-channels = <8>; | |
| #dma-requests = <32>; | |
| }; | |
| }; | |
| clock_topc: clock-controller@10570000 { | |
| compatible = "samsung,exynos7-clock-topc"; | |
| reg = <0x10570000 0x10000>; | |
| #clock-cells = <1>; | |
| }; | |
| clock_top0: clock-controller@105d0000 { | |
| compatible = "samsung,exynos7-clock-top0"; | |
| reg = <0x105d0000 0xb000>; | |
| #clock-cells = <1>; | |
| clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, | |
| <&clock_topc DOUT_SCLK_BUS1_PLL>, | |
| <&clock_topc DOUT_SCLK_CC_PLL>, | |
| <&clock_topc DOUT_SCLK_MFC_PLL>; | |
| clock-names = "fin_pll", "dout_sclk_bus0_pll", | |
| "dout_sclk_bus1_pll", "dout_sclk_cc_pll", | |
| "dout_sclk_mfc_pll"; | |
| }; | |
| clock_top1: clock-controller@105e0000 { | |
| compatible = "samsung,exynos7-clock-top1"; | |
| reg = <0x105e0000 0xb000>; | |
| #clock-cells = <1>; | |
| clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, | |
| <&clock_topc DOUT_SCLK_BUS1_PLL>, | |
| <&clock_topc DOUT_SCLK_CC_PLL>, | |
| <&clock_topc DOUT_SCLK_MFC_PLL>; | |
| clock-names = "fin_pll", "dout_sclk_bus0_pll", | |
| "dout_sclk_bus1_pll", "dout_sclk_cc_pll", | |
| "dout_sclk_mfc_pll"; | |
| }; | |
| clock_ccore: clock-controller@105b0000 { | |
| compatible = "samsung,exynos7-clock-ccore"; | |
| reg = <0x105b0000 0xd00>; | |
| #clock-cells = <1>; | |
| clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; | |
| clock-names = "fin_pll", "dout_aclk_ccore_133"; | |
| }; | |
| clock_peric0: clock-controller@13610000 { | |
| compatible = "samsung,exynos7-clock-peric0"; | |
| reg = <0x13610000 0xd00>; | |
| #clock-cells = <1>; | |
| clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, | |
| <&clock_top0 CLK_SCLK_UART0>; | |
| clock-names = "fin_pll", "dout_aclk_peric0_66", | |
| "sclk_uart0"; | |
| }; | |
| clock_peric1: clock-controller@14c80000 { | |
| compatible = "samsung,exynos7-clock-peric1"; | |
| reg = <0x14c80000 0xd00>; | |
| #clock-cells = <1>; | |
| clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, | |
| <&clock_top0 CLK_SCLK_UART1>, | |
| <&clock_top0 CLK_SCLK_UART2>, | |
| <&clock_top0 CLK_SCLK_UART3>; | |
| clock-names = "fin_pll", "dout_aclk_peric1_66", | |
| "sclk_uart1", "sclk_uart2", "sclk_uart3"; | |
| }; | |
| clock_peris: clock-controller@10040000 { | |
| compatible = "samsung,exynos7-clock-peris"; | |
| reg = <0x10040000 0xd00>; | |
| #clock-cells = <1>; | |
| clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; | |
| clock-names = "fin_pll", "dout_aclk_peris_66"; | |
| }; | |
| clock_fsys0: clock-controller@10e90000 { | |
| compatible = "samsung,exynos7-clock-fsys0"; | |
| reg = <0x10e90000 0xd00>; | |
| #clock-cells = <1>; | |
| clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, | |
| <&clock_top1 DOUT_SCLK_MMC2>; | |
| clock-names = "fin_pll", "dout_aclk_fsys0_200", | |
| "dout_sclk_mmc2"; | |
| }; | |
| clock_fsys1: clock-controller@156e0000 { | |
| compatible = "samsung,exynos7-clock-fsys1"; | |
| reg = <0x156e0000 0xd00>; | |
| #clock-cells = <1>; | |
| clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, | |
| <&clock_top1 DOUT_SCLK_MMC0>, | |
| <&clock_top1 DOUT_SCLK_MMC1>; | |
| clock-names = "fin_pll", "dout_aclk_fsys1_200", | |
| "dout_sclk_mmc0", "dout_sclk_mmc1"; | |
| }; | |
| serial_0: serial@13630000 { | |
| compatible = "samsung,exynos4210-uart"; | |
| reg = <0x13630000 0x100>; | |
| interrupts = <0 440 0>; | |
| clocks = <&clock_peric0 PCLK_UART0>, | |
| <&clock_peric0 SCLK_UART0>; | |
| clock-names = "uart", "clk_uart_baud0"; | |
| status = "disabled"; | |
| }; | |
| serial_1: serial@14c20000 { | |
| compatible = "samsung,exynos4210-uart"; | |
| reg = <0x14c20000 0x100>; | |
| interrupts = <0 456 0>; | |
| clocks = <&clock_peric1 PCLK_UART1>, | |
| <&clock_peric1 SCLK_UART1>; | |
| clock-names = "uart", "clk_uart_baud0"; | |
| status = "disabled"; | |
| }; | |
| serial_2: serial@14c30000 { | |
| compatible = "samsung,exynos4210-uart"; | |
| reg = <0x14c30000 0x100>; | |
| interrupts = <0 457 0>; | |
| clocks = <&clock_peric1 PCLK_UART2>, | |
| <&clock_peric1 SCLK_UART2>; | |
| clock-names = "uart", "clk_uart_baud0"; | |
| status = "disabled"; | |
| }; | |
| serial_3: serial@14c40000 { | |
| compatible = "samsung,exynos4210-uart"; | |
| reg = <0x14c40000 0x100>; | |
| interrupts = <0 458 0>; | |
| clocks = <&clock_peric1 PCLK_UART3>, | |
| <&clock_peric1 SCLK_UART3>; | |
| clock-names = "uart", "clk_uart_baud0"; | |
| status = "disabled"; | |
| }; | |
| pinctrl_alive: pinctrl@10580000 { | |
| compatible = "samsung,exynos7-pinctrl"; | |
| reg = <0x10580000 0x1000>; | |
| wakeup-interrupt-controller { | |
| compatible = "samsung,exynos7-wakeup-eint"; | |
| interrupt-parent = <&gic>; | |
| interrupts = <0 16 0>; | |
| }; | |
| }; | |
| pinctrl_bus0: pinctrl@13470000 { | |
| compatible = "samsung,exynos7-pinctrl"; | |
| reg = <0x13470000 0x1000>; | |
| interrupts = <0 383 0>; | |
| }; | |
| pinctrl_nfc: pinctrl@14cd0000 { | |
| compatible = "samsung,exynos7-pinctrl"; | |
| reg = <0x14cd0000 0x1000>; | |
| interrupts = <0 473 0>; | |
| }; | |
| pinctrl_touch: pinctrl@14ce0000 { | |
| compatible = "samsung,exynos7-pinctrl"; | |
| reg = <0x14ce0000 0x1000>; | |
| interrupts = <0 474 0>; | |
| }; | |
| pinctrl_ff: pinctrl@14c90000 { | |
| compatible = "samsung,exynos7-pinctrl"; | |
| reg = <0x14c90000 0x1000>; | |
| interrupts = <0 475 0>; | |
| }; | |
| pinctrl_ese: pinctrl@14ca0000 { | |
| compatible = "samsung,exynos7-pinctrl"; | |
| reg = <0x14ca0000 0x1000>; | |
| interrupts = <0 476 0>; | |
| }; | |
| pinctrl_fsys0: pinctrl@10e60000 { | |
| compatible = "samsung,exynos7-pinctrl"; | |
| reg = <0x10e60000 0x1000>; | |
| interrupts = <0 221 0>; | |
| }; | |
| pinctrl_fsys1: pinctrl@15690000 { | |
| compatible = "samsung,exynos7-pinctrl"; | |
| reg = <0x15690000 0x1000>; | |
| interrupts = <0 203 0>; | |
| }; | |
| pinctrl_bus1: pinctrl@14870000 { | |
| compatible = "samsung,exynos7-pinctrl"; | |
| reg = <0x14870000 0x1000>; | |
| interrupts = <0 384 0>; | |
| }; | |
| hsi2c_0: hsi2c@13640000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x13640000 0x1000>; | |
| interrupts = <0 441 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c0_bus>; | |
| clocks = <&clock_peric0 PCLK_HSI2C0>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_1: hsi2c@13650000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x13650000 0x1000>; | |
| interrupts = <0 442 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c1_bus>; | |
| clocks = <&clock_peric0 PCLK_HSI2C1>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_2: hsi2c@14e60000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x14e60000 0x1000>; | |
| interrupts = <0 459 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c2_bus>; | |
| clocks = <&clock_peric1 PCLK_HSI2C2>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_3: hsi2c@14e70000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x14e70000 0x1000>; | |
| interrupts = <0 460 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c3_bus>; | |
| clocks = <&clock_peric1 PCLK_HSI2C3>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_4: hsi2c@13660000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x13660000 0x1000>; | |
| interrupts = <0 443 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c4_bus>; | |
| clocks = <&clock_peric0 PCLK_HSI2C4>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_5: hsi2c@13670000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x13670000 0x1000>; | |
| interrupts = <0 444 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c5_bus>; | |
| clocks = <&clock_peric0 PCLK_HSI2C5>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_6: hsi2c@14e00000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x14e00000 0x1000>; | |
| interrupts = <0 461 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c6_bus>; | |
| clocks = <&clock_peric1 PCLK_HSI2C6>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_7: hsi2c@13e10000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x13e10000 0x1000>; | |
| interrupts = <0 462 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c7_bus>; | |
| clocks = <&clock_peric1 PCLK_HSI2C7>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_8: hsi2c@14e20000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x14e20000 0x1000>; | |
| interrupts = <0 463 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c8_bus>; | |
| clocks = <&clock_peric1 PCLK_HSI2C8>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_9: hsi2c@13680000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x13680000 0x1000>; | |
| interrupts = <0 445 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c9_bus>; | |
| clocks = <&clock_peric0 PCLK_HSI2C9>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_10: hsi2c@13690000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x13690000 0x1000>; | |
| interrupts = <0 446 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c10_bus>; | |
| clocks = <&clock_peric0 PCLK_HSI2C10>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| hsi2c_11: hsi2c@136a0000 { | |
| compatible = "samsung,exynos7-hsi2c"; | |
| reg = <0x136a0000 0x1000>; | |
| interrupts = <0 447 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&hs_i2c11_bus>; | |
| clocks = <&clock_peric0 PCLK_HSI2C11>; | |
| clock-names = "hsi2c"; | |
| status = "disabled"; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <GIC_PPI 13 | |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 14 | |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 11 | |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 10 | |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; | |
| }; | |
| pmu_system_controller: system-controller@105c0000 { | |
| compatible = "samsung,exynos7-pmu", "syscon"; | |
| reg = <0x105c0000 0x5000>; | |
| }; | |
| reboot: syscon-reboot { | |
| compatible = "syscon-reboot"; | |
| regmap = <&pmu_system_controller>; | |
| offset = <0x0400>; | |
| mask = <0x1>; | |
| }; | |
| rtc: rtc@10590000 { | |
| compatible = "samsung,s3c6410-rtc"; | |
| reg = <0x10590000 0x100>; | |
| interrupts = <0 355 0>, <0 356 0>; | |
| clocks = <&clock_ccore PCLK_RTC>; | |
| clock-names = "rtc"; | |
| status = "disabled"; | |
| }; | |
| watchdog: watchdog@101d0000 { | |
| compatible = "samsung,exynos7-wdt"; | |
| reg = <0x101d0000 0x100>; | |
| interrupts = <0 110 0>; | |
| clocks = <&clock_peris PCLK_WDT>; | |
| clock-names = "watchdog"; | |
| samsung,syscon-phandle = <&pmu_system_controller>; | |
| status = "disabled"; | |
| }; | |
| mmc_0: mmc@15740000 { | |
| compatible = "samsung,exynos7-dw-mshc-smu"; | |
| interrupts = <0 201 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| reg = <0x15740000 0x2000>; | |
| clocks = <&clock_fsys1 ACLK_MMC0>, | |
| <&clock_top1 CLK_SCLK_MMC0>; | |
| clock-names = "biu", "ciu"; | |
| fifo-depth = <0x40>; | |
| status = "disabled"; | |
| }; | |
| mmc_1: mmc@15750000 { | |
| compatible = "samsung,exynos7-dw-mshc"; | |
| interrupts = <0 202 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| reg = <0x15750000 0x2000>; | |
| clocks = <&clock_fsys1 ACLK_MMC1>, | |
| <&clock_top1 CLK_SCLK_MMC1>; | |
| clock-names = "biu", "ciu"; | |
| fifo-depth = <0x40>; | |
| status = "disabled"; | |
| }; | |
| mmc_2: mmc@15560000 { | |
| compatible = "samsung,exynos7-dw-mshc-smu"; | |
| interrupts = <0 216 0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| reg = <0x15560000 0x2000>; | |
| clocks = <&clock_fsys0 ACLK_MMC2>, | |
| <&clock_top1 CLK_SCLK_MMC2>; | |
| clock-names = "biu", "ciu"; | |
| fifo-depth = <0x40>; | |
| status = "disabled"; | |
| }; | |
| adc: adc@13620000 { | |
| compatible = "samsung,exynos7-adc"; | |
| reg = <0x13620000 0x100>; | |
| interrupts = <0 448 0>; | |
| clocks = <&clock_peric0 PCLK_ADCIF>; | |
| clock-names = "adc"; | |
| #io-channel-cells = <1>; | |
| io-channel-ranges; | |
| status = "disabled"; | |
| }; | |
| pwm: pwm@136c0000 { | |
| compatible = "samsung,exynos4210-pwm"; | |
| reg = <0x136c0000 0x100>; | |
| samsung,pwm-outputs = <0>, <1>, <2>, <3>; | |
| #pwm-cells = <3>; | |
| clocks = <&clock_peric0 PCLK_PWM>; | |
| clock-names = "timers"; | |
| }; | |
| tmuctrl_0: tmu@10060000 { | |
| compatible = "samsung,exynos7-tmu"; | |
| reg = <0x10060000 0x200>; | |
| interrupts = <0 108 0>; | |
| clocks = <&clock_peris PCLK_TMU>, | |
| <&clock_peris SCLK_TMU>; | |
| clock-names = "tmu_apbif", "tmu_sclk"; | |
| #include "exynos7-tmu-sensor-conf.dtsi" | |
| }; | |
| thermal-zones { | |
| atlas_thermal: cluster0-thermal { | |
| polling-delay-passive = <0>; /* milliseconds */ | |
| polling-delay = <0>; /* milliseconds */ | |
| thermal-sensors = <&tmuctrl_0>; | |
| #include "exynos7-trip-points.dtsi" | |
| }; | |
| }; | |
| }; | |
| }; | |
| #include "exynos7-pinctrl.dtsi" |