| /* | |
| * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. | |
| * | |
| * This program is free software; you can redistribute it and/or modify | |
| * it under the terms of the GNU General Public License version 2 and | |
| * only version 2 as published by the Free Software Foundation. | |
| * | |
| * This program is distributed in the hope that it will be useful, | |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| * GNU General Public License for more details. | |
| */ | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| #include <dt-bindings/clock/qcom,gcc-msm8916.h> | |
| #include <dt-bindings/reset/qcom,gcc-msm8916.h> | |
| / { | |
| model = "Qualcomm Technologies, Inc. MSM8916"; | |
| compatible = "qcom,msm8916"; | |
| interrupt-parent = <&intc>; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| aliases { | |
| sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ | |
| sdhc2 = &sdhc_2; /* SDC2 SD card slot */ | |
| }; | |
| chosen { }; | |
| memory { | |
| device_type = "memory"; | |
| /* We expect the bootloader to fill in the reg */ | |
| reg = <0 0 0 0>; | |
| }; | |
| reserved-memory { | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| ranges; | |
| tz-apps@86000000 { | |
| reg = <0x0 0x86000000 0x0 0x300000>; | |
| no-map; | |
| }; | |
| smem_mem: smem_region@86300000 { | |
| reg = <0x0 0x86300000 0x0 0x100000>; | |
| no-map; | |
| }; | |
| hypervisor@86400000 { | |
| reg = <0x0 0x86400000 0x0 0x100000>; | |
| no-map; | |
| }; | |
| tz@86500000 { | |
| reg = <0x0 0x86500000 0x0 0x180000>; | |
| no-map; | |
| }; | |
| reserved@8668000 { | |
| reg = <0x0 0x86680000 0x0 0x80000>; | |
| no-map; | |
| }; | |
| rmtfs@86700000 { | |
| reg = <0x0 0x86700000 0x0 0xe0000>; | |
| no-map; | |
| }; | |
| rfsa@867e00000 { | |
| reg = <0x0 0x867e0000 0x0 0x20000>; | |
| no-map; | |
| }; | |
| mpss@86800000 { | |
| reg = <0x0 0x86800000 0x0 0x2b00000>; | |
| no-map; | |
| }; | |
| wcnss@89300000 { | |
| reg = <0x0 0x89300000 0x0 0x600000>; | |
| no-map; | |
| }; | |
| mba_mem: mba@8ea00000 { | |
| no-map; | |
| reg = <0 0x8ea00000 0 0x100000>; | |
| }; | |
| }; | |
| cpus { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| CPU0: cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x0>; | |
| next-level-cache = <&L2_0>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <&CPU_SPC>; | |
| }; | |
| CPU1: cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x1>; | |
| next-level-cache = <&L2_0>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <&CPU_SPC>; | |
| }; | |
| CPU2: cpu@2 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x2>; | |
| next-level-cache = <&L2_0>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <&CPU_SPC>; | |
| }; | |
| CPU3: cpu@3 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a53", "arm,armv8"; | |
| reg = <0x3>; | |
| next-level-cache = <&L2_0>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <&CPU_SPC>; | |
| }; | |
| L2_0: l2-cache { | |
| compatible = "cache"; | |
| cache-level = <2>; | |
| }; | |
| idle-states { | |
| CPU_SPC: spc { | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x40000002>; | |
| entry-latency-us = <130>; | |
| exit-latency-us = <150>; | |
| min-residency-us = <2000>; | |
| local-timer-stop; | |
| }; | |
| }; | |
| }; | |
| psci { | |
| compatible = "arm,psci-1.0"; | |
| method = "smc"; | |
| }; | |
| pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>; | |
| }; | |
| thermal-zones { | |
| cpu-thermal0 { | |
| polling-delay-passive = <250>; | |
| polling-delay = <1000>; | |
| thermal-sensors = <&tsens 4>; | |
| trips { | |
| cpu_alert0: trip0 { | |
| temperature = <75000>; | |
| hysteresis = <2000>; | |
| type = "passive"; | |
| }; | |
| cpu_crit0: trip1 { | |
| temperature = <110000>; | |
| hysteresis = <2000>; | |
| type = "critical"; | |
| }; | |
| }; | |
| }; | |
| cpu-thermal1 { | |
| polling-delay-passive = <250>; | |
| polling-delay = <1000>; | |
| thermal-sensors = <&tsens 3>; | |
| trips { | |
| cpu_alert1: trip0 { | |
| temperature = <75000>; | |
| hysteresis = <2000>; | |
| type = "passive"; | |
| }; | |
| cpu_crit1: trip1 { | |
| temperature = <110000>; | |
| hysteresis = <2000>; | |
| type = "critical"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| }; | |
| clocks { | |
| xo_board: xo_board { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <19200000>; | |
| }; | |
| sleep_clk: sleep_clk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <32768>; | |
| }; | |
| }; | |
| smem { | |
| compatible = "qcom,smem"; | |
| memory-region = <&smem_mem>; | |
| qcom,rpm-msg-ram = <&rpm_msg_ram>; | |
| hwlocks = <&tcsr_mutex 3>; | |
| }; | |
| firmware { | |
| scm: scm { | |
| compatible = "qcom,scm"; | |
| clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; | |
| clock-names = "core", "bus", "iface"; | |
| #reset-cells = <1>; | |
| }; | |
| }; | |
| soc: soc { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges = <0 0 0 0xffffffff>; | |
| compatible = "simple-bus"; | |
| restart@4ab000 { | |
| compatible = "qcom,pshold"; | |
| reg = <0x4ab000 0x4>; | |
| }; | |
| msmgpio: pinctrl@1000000 { | |
| compatible = "qcom,msm8916-pinctrl"; | |
| reg = <0x1000000 0x300000>; | |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| }; | |
| gcc: clock-controller@1800000 { | |
| compatible = "qcom,gcc-msm8916"; | |
| #clock-cells = <1>; | |
| #reset-cells = <1>; | |
| #power-domain-cells = <1>; | |
| reg = <0x1800000 0x80000>; | |
| }; | |
| tcsr_mutex_regs: syscon@1905000 { | |
| compatible = "syscon"; | |
| reg = <0x1905000 0x20000>; | |
| }; | |
| tcsr: syscon@1937000 { | |
| compatible = "qcom,tcsr-msm8916", "syscon"; | |
| reg = <0x1937000 0x30000>; | |
| }; | |
| tcsr_mutex: hwlock { | |
| compatible = "qcom,tcsr-mutex"; | |
| syscon = <&tcsr_mutex_regs 0 0x1000>; | |
| #hwlock-cells = <1>; | |
| }; | |
| rpm_msg_ram: memory@60000 { | |
| compatible = "qcom,rpm-msg-ram"; | |
| reg = <0x60000 0x8000>; | |
| }; | |
| blsp1_uart1: serial@78af000 { | |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| reg = <0x78af000 0x200>; | |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| dmas = <&blsp_dma 1>, <&blsp_dma 0>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| apcs: syscon@b011000 { | |
| compatible = "syscon"; | |
| reg = <0x0b011000 0x1000>; | |
| }; | |
| blsp1_uart2: serial@78b0000 { | |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| reg = <0x78b0000 0x200>; | |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| dmas = <&blsp_dma 3>, <&blsp_dma 2>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| blsp_dma: dma@7884000 { | |
| compatible = "qcom,bam-v1.7.0"; | |
| reg = <0x07884000 0x23000>; | |
| interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>; | |
| clock-names = "bam_clk"; | |
| #dma-cells = <1>; | |
| qcom,ee = <0>; | |
| status = "disabled"; | |
| }; | |
| blsp_spi1: spi@78b5000 { | |
| compatible = "qcom,spi-qup-v2.2.1"; | |
| reg = <0x078b5000 0x600>; | |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, | |
| <&gcc GCC_BLSP1_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| dmas = <&blsp_dma 5>, <&blsp_dma 4>; | |
| dma-names = "rx", "tx"; | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <&spi1_default>; | |
| pinctrl-1 = <&spi1_sleep>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| blsp_spi2: spi@78b6000 { | |
| compatible = "qcom,spi-qup-v2.2.1"; | |
| reg = <0x078b6000 0x600>; | |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, | |
| <&gcc GCC_BLSP1_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| dmas = <&blsp_dma 7>, <&blsp_dma 6>; | |
| dma-names = "rx", "tx"; | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <&spi2_default>; | |
| pinctrl-1 = <&spi2_sleep>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| blsp_spi3: spi@78b7000 { | |
| compatible = "qcom,spi-qup-v2.2.1"; | |
| reg = <0x078b7000 0x600>; | |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, | |
| <&gcc GCC_BLSP1_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| dmas = <&blsp_dma 9>, <&blsp_dma 8>; | |
| dma-names = "rx", "tx"; | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <&spi3_default>; | |
| pinctrl-1 = <&spi3_sleep>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| blsp_spi4: spi@78b8000 { | |
| compatible = "qcom,spi-qup-v2.2.1"; | |
| reg = <0x078b8000 0x600>; | |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, | |
| <&gcc GCC_BLSP1_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| dmas = <&blsp_dma 11>, <&blsp_dma 10>; | |
| dma-names = "rx", "tx"; | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <&spi4_default>; | |
| pinctrl-1 = <&spi4_sleep>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| blsp_spi5: spi@78b9000 { | |
| compatible = "qcom,spi-qup-v2.2.1"; | |
| reg = <0x078b9000 0x600>; | |
| interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, | |
| <&gcc GCC_BLSP1_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| dmas = <&blsp_dma 13>, <&blsp_dma 12>; | |
| dma-names = "rx", "tx"; | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <&spi5_default>; | |
| pinctrl-1 = <&spi5_sleep>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| blsp_spi6: spi@78ba000 { | |
| compatible = "qcom,spi-qup-v2.2.1"; | |
| reg = <0x078ba000 0x600>; | |
| interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, | |
| <&gcc GCC_BLSP1_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| dmas = <&blsp_dma 15>, <&blsp_dma 14>; | |
| dma-names = "rx", "tx"; | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <&spi6_default>; | |
| pinctrl-1 = <&spi6_sleep>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| blsp_i2c2: i2c@78b6000 { | |
| compatible = "qcom,i2c-qup-v2.2.1"; | |
| reg = <0x78b6000 0x1000>; | |
| interrupts = <GIC_SPI 96 0>; | |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>, | |
| <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; | |
| clock-names = "iface", "core"; | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <&i2c2_default>; | |
| pinctrl-1 = <&i2c2_sleep>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| blsp_i2c4: i2c@78b8000 { | |
| compatible = "qcom,i2c-qup-v2.2.1"; | |
| reg = <0x78b8000 0x1000>; | |
| interrupts = <GIC_SPI 98 0>; | |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>, | |
| <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; | |
| clock-names = "iface", "core"; | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <&i2c4_default>; | |
| pinctrl-1 = <&i2c4_sleep>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| blsp_i2c6: i2c@78ba000 { | |
| compatible = "qcom,i2c-qup-v2.2.1"; | |
| reg = <0x78ba000 0x1000>; | |
| interrupts = <GIC_SPI 100 0>; | |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>, | |
| <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; | |
| clock-names = "iface", "core"; | |
| pinctrl-names = "default", "sleep"; | |
| pinctrl-0 = <&i2c6_default>; | |
| pinctrl-1 = <&i2c6_sleep>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "disabled"; | |
| }; | |
| lpass: lpass@07708000 { | |
| status = "disabled"; | |
| compatible = "qcom,lpass-cpu-apq8016"; | |
| clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, | |
| <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, | |
| <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, | |
| <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, | |
| <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, | |
| <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, | |
| <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; | |
| clock-names = "ahbix-clk", | |
| "pcnoc-mport-clk", | |
| "pcnoc-sway-clk", | |
| "mi2s-bit-clk0", | |
| "mi2s-bit-clk1", | |
| "mi2s-bit-clk2", | |
| "mi2s-bit-clk3"; | |
| #sound-dai-cells = <1>; | |
| interrupts = <0 160 0>; | |
| interrupt-names = "lpass-irq-lpaif"; | |
| reg = <0x07708000 0x10000>; | |
| reg-names = "lpass-lpaif"; | |
| }; | |
| sdhc_1: sdhci@07824000 { | |
| compatible = "qcom,sdhci-msm-v4"; | |
| reg = <0x07824900 0x11c>, <0x07824000 0x800>; | |
| reg-names = "hc_mem", "core_mem"; | |
| interrupts = <0 123 0>, <0 138 0>; | |
| interrupt-names = "hc_irq", "pwr_irq"; | |
| clocks = <&gcc GCC_SDCC1_APPS_CLK>, | |
| <&gcc GCC_SDCC1_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| bus-width = <8>; | |
| non-removable; | |
| status = "disabled"; | |
| }; | |
| sdhc_2: sdhci@07864000 { | |
| compatible = "qcom,sdhci-msm-v4"; | |
| reg = <0x07864900 0x11c>, <0x07864000 0x800>; | |
| reg-names = "hc_mem", "core_mem"; | |
| interrupts = <0 125 0>, <0 221 0>; | |
| interrupt-names = "hc_irq", "pwr_irq"; | |
| clocks = <&gcc GCC_SDCC2_APPS_CLK>, | |
| <&gcc GCC_SDCC2_AHB_CLK>; | |
| clock-names = "core", "iface"; | |
| bus-width = <4>; | |
| status = "disabled"; | |
| }; | |
| usb_dev: usb@78d9000 { | |
| compatible = "qcom,ci-hdrc"; | |
| reg = <0x78d9000 0x400>; | |
| dr_mode = "peripheral"; | |
| interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
| usb-phy = <&usb_otg>; | |
| status = "disabled"; | |
| }; | |
| usb_host: ehci@78d9000 { | |
| compatible = "qcom,ehci-host"; | |
| reg = <0x78d9000 0x400>; | |
| interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
| usb-phy = <&usb_otg>; | |
| status = "disabled"; | |
| }; | |
| usb_otg: phy@78d9000 { | |
| compatible = "qcom,usb-otg-snps"; | |
| reg = <0x78d9000 0x400>; | |
| interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; | |
| qcom,vdd-levels = <500000 1000000 1320000>; | |
| qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>; | |
| dr_mode = "peripheral"; | |
| qcom,otg-control = <2>; // PMIC | |
| qcom,manual-pullup; | |
| clocks = <&gcc GCC_USB_HS_AHB_CLK>, | |
| <&gcc GCC_USB_HS_SYSTEM_CLK>, | |
| <&gcc GCC_USB2A_PHY_SLEEP_CLK>; | |
| clock-names = "iface", "core", "sleep"; | |
| resets = <&gcc GCC_USB2A_PHY_BCR>, | |
| <&gcc GCC_USB_HS_BCR>; | |
| reset-names = "phy", "link"; | |
| status = "disabled"; | |
| }; | |
| intc: interrupt-controller@b000000 { | |
| compatible = "qcom,msm-qgic2"; | |
| interrupt-controller; | |
| #interrupt-cells = <3>; | |
| reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; | |
| }; | |
| timer@b020000 { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges; | |
| compatible = "arm,armv7-timer-mem"; | |
| reg = <0xb020000 0x1000>; | |
| clock-frequency = <19200000>; | |
| frame@b021000 { | |
| frame-number = <0>; | |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| reg = <0xb021000 0x1000>, | |
| <0xb022000 0x1000>; | |
| }; | |
| frame@b023000 { | |
| frame-number = <1>; | |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| reg = <0xb023000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@b024000 { | |
| frame-number = <2>; | |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| reg = <0xb024000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@b025000 { | |
| frame-number = <3>; | |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| reg = <0xb025000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@b026000 { | |
| frame-number = <4>; | |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
| reg = <0xb026000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@b027000 { | |
| frame-number = <5>; | |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
| reg = <0xb027000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@b028000 { | |
| frame-number = <6>; | |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| reg = <0xb028000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| spmi_bus: spmi@200f000 { | |
| compatible = "qcom,spmi-pmic-arb"; | |
| reg = <0x200f000 0x001000>, | |
| <0x2400000 0x400000>, | |
| <0x2c00000 0x400000>, | |
| <0x3800000 0x200000>, | |
| <0x200a000 0x002100>; | |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
| interrupt-names = "periph_irq"; | |
| interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | |
| qcom,ee = <0>; | |
| qcom,channel = <0>; | |
| #address-cells = <2>; | |
| #size-cells = <0>; | |
| interrupt-controller; | |
| #interrupt-cells = <4>; | |
| }; | |
| rng@22000 { | |
| compatible = "qcom,prng"; | |
| reg = <0x00022000 0x200>; | |
| clocks = <&gcc GCC_PRNG_AHB_CLK>; | |
| clock-names = "core"; | |
| }; | |
| qfprom: qfprom@5c000 { | |
| compatible = "qcom,qfprom"; | |
| reg = <0x5c000 0x1000>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| tsens_caldata: caldata@d0 { | |
| reg = <0xd0 0x8>; | |
| }; | |
| tsens_calsel: calsel@ec { | |
| reg = <0xec 0x4>; | |
| }; | |
| }; | |
| tsens: thermal-sensor@4a8000 { | |
| compatible = "qcom,msm8916-tsens"; | |
| reg = <0x4a8000 0x2000>; | |
| nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; | |
| nvmem-cell-names = "calib", "calib_sel"; | |
| #thermal-sensor-cells = <1>; | |
| }; | |
| mdss: mdss@1a00000 { | |
| compatible = "qcom,mdss"; | |
| reg = <0x1a00000 0x1000>, | |
| <0x1ac8000 0x3000>; | |
| reg-names = "mdss_phys", "vbif_phys"; | |
| power-domains = <&gcc MDSS_GDSC>; | |
| clocks = <&gcc GCC_MDSS_AHB_CLK>, | |
| <&gcc GCC_MDSS_AXI_CLK>, | |
| <&gcc GCC_MDSS_VSYNC_CLK>; | |
| clock-names = "iface_clk", | |
| "bus_clk", | |
| "vsync_clk"; | |
| interrupts = <0 72 0>; | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges; | |
| mdp: mdp@1a01000 { | |
| compatible = "qcom,mdp5"; | |
| reg = <0x1a01000 0x90000>; | |
| reg-names = "mdp_phys"; | |
| interrupt-parent = <&mdss>; | |
| interrupts = <0 0>; | |
| clocks = <&gcc GCC_MDSS_AHB_CLK>, | |
| <&gcc GCC_MDSS_AXI_CLK>, | |
| <&gcc GCC_MDSS_MDP_CLK>, | |
| <&gcc GCC_MDSS_VSYNC_CLK>; | |
| clock-names = "iface_clk", | |
| "bus_clk", | |
| "core_clk", | |
| "vsync_clk"; | |
| ports { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| port@0 { | |
| reg = <0>; | |
| mdp5_intf1_out: endpoint { | |
| remote-endpoint = <&dsi0_in>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi0: dsi@1a98000 { | |
| compatible = "qcom,mdss-dsi-ctrl"; | |
| reg = <0x1a98000 0x25c>; | |
| reg-names = "dsi_ctrl"; | |
| interrupt-parent = <&mdss>; | |
| interrupts = <4 0>; | |
| assigned-clocks = <&gcc BYTE0_CLK_SRC>, | |
| <&gcc PCLK0_CLK_SRC>; | |
| assigned-clock-parents = <&dsi_phy0 0>, | |
| <&dsi_phy0 1>; | |
| clocks = <&gcc GCC_MDSS_MDP_CLK>, | |
| <&gcc GCC_MDSS_AHB_CLK>, | |
| <&gcc GCC_MDSS_AXI_CLK>, | |
| <&gcc GCC_MDSS_BYTE0_CLK>, | |
| <&gcc GCC_MDSS_PCLK0_CLK>, | |
| <&gcc GCC_MDSS_ESC0_CLK>; | |
| clock-names = "mdp_core_clk", | |
| "iface_clk", | |
| "bus_clk", | |
| "byte_clk", | |
| "pixel_clk", | |
| "core_clk"; | |
| phys = <&dsi_phy0>; | |
| phy-names = "dsi-phy"; | |
| ports { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| port@0 { | |
| reg = <0>; | |
| dsi0_in: endpoint { | |
| remote-endpoint = <&mdp5_intf1_out>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <1>; | |
| dsi0_out: endpoint { | |
| }; | |
| }; | |
| }; | |
| }; | |
| dsi_phy0: dsi-phy@1a98300 { | |
| compatible = "qcom,dsi-phy-28nm-lp"; | |
| reg = <0x1a98300 0xd4>, | |
| <0x1a98500 0x280>, | |
| <0x1a98780 0x30>; | |
| reg-names = "dsi_pll", | |
| "dsi_phy", | |
| "dsi_phy_regulator"; | |
| #clock-cells = <1>; | |
| clocks = <&gcc GCC_MDSS_AHB_CLK>; | |
| clock-names = "iface_clk"; | |
| }; | |
| }; | |
| }; | |
| smd { | |
| compatible = "qcom,smd"; | |
| rpm { | |
| interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; | |
| qcom,ipc = <&apcs 8 0>; | |
| qcom,smd-edge = <15>; | |
| rpm_requests { | |
| compatible = "qcom,rpm-msm8916"; | |
| qcom,smd-channels = "rpm_requests"; | |
| rpmcc: qcom,rpmcc { | |
| compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; | |
| #clock-cells = <1>; | |
| }; | |
| smd_rpm_regulators: pm8916-regulators { | |
| compatible = "qcom,rpm-pm8916-regulators"; | |
| pm8916_s1: s1 {}; | |
| pm8916_s3: s3 {}; | |
| pm8916_s4: s4 {}; | |
| pm8916_l1: l1 {}; | |
| pm8916_l2: l2 {}; | |
| pm8916_l3: l3 {}; | |
| pm8916_l4: l4 {}; | |
| pm8916_l5: l5 {}; | |
| pm8916_l6: l6 {}; | |
| pm8916_l7: l7 {}; | |
| pm8916_l8: l8 {}; | |
| pm8916_l9: l9 {}; | |
| pm8916_l10: l10 {}; | |
| pm8916_l11: l11 {}; | |
| pm8916_l12: l12 {}; | |
| pm8916_l13: l13 {}; | |
| pm8916_l14: l14 {}; | |
| pm8916_l15: l15 {}; | |
| pm8916_l16: l16 {}; | |
| pm8916_l17: l17 {}; | |
| pm8916_l18: l18 {}; | |
| }; | |
| }; | |
| }; | |
| }; | |
| hexagon-smp2p { | |
| compatible = "qcom,smp2p"; | |
| qcom,smem = <435>, <428>; | |
| interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; | |
| qcom,ipc = <&apcs 8 14>; | |
| qcom,local-pid = <0>; | |
| qcom,remote-pid = <1>; | |
| hexagon_smp2p_out: master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <1>; | |
| }; | |
| hexagon_smp2p_in: slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| }; | |
| }; | |
| wcnss-smp2p { | |
| compatible = "qcom,smp2p"; | |
| qcom,smem = <451>, <431>; | |
| interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; | |
| qcom,ipc = <&apcs 8 18>; | |
| qcom,local-pid = <0>; | |
| qcom,remote-pid = <4>; | |
| wcnss_smp2p_out: master-kernel { | |
| qcom,entry-name = "master-kernel"; | |
| #qcom,smem-state-cells = <1>; | |
| }; | |
| wcnss_smp2p_in: slave-kernel { | |
| qcom,entry-name = "slave-kernel"; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| }; | |
| }; | |
| smsm { | |
| compatible = "qcom,smsm"; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| qcom,ipc-1 = <&apcs 0 13>; | |
| qcom,ipc-6 = <&apcs 0 19>; | |
| apps_smsm: apps@0 { | |
| reg = <0>; | |
| #qcom,smem-state-cells = <1>; | |
| }; | |
| hexagon_smsm: hexagon@1 { | |
| reg = <1>; | |
| interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| }; | |
| wcnss_smsm: wcnss@6 { | |
| reg = <6>; | |
| interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| }; | |
| }; | |
| }; | |
| #include "msm8916-pins.dtsi" |