| /* | |
| * Device Tree Source for the r8a7796 SoC | |
| * | |
| * Copyright (C) 2016 Renesas Electronics Corp. | |
| * | |
| * This file is licensed under the terms of the GNU General Public License | |
| * version 2. This program is licensed "as is" without any warranty of any | |
| * kind, whether express or implied. | |
| */ | |
| #include <dt-bindings/clock/r8a7796-cpg-mssr.h> | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| #include <dt-bindings/power/r8a7796-sysc.h> | |
| / { | |
| compatible = "renesas,r8a7796"; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| psci { | |
| compatible = "arm,psci-0.2"; | |
| method = "smc"; | |
| }; | |
| cpus { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| /* 1 core only at this point */ | |
| a57_0: cpu@0 { | |
| compatible = "arm,cortex-a57", "arm,armv8"; | |
| reg = <0x0>; | |
| device_type = "cpu"; | |
| power-domains = <&sysc R8A7796_PD_CA57_CPU0>; | |
| next-level-cache = <&L2_CA57>; | |
| enable-method = "psci"; | |
| }; | |
| L2_CA57: cache-controller@0 { | |
| compatible = "cache"; | |
| reg = <0>; | |
| power-domains = <&sysc R8A7796_PD_CA57_SCU>; | |
| cache-unified; | |
| cache-level = <2>; | |
| }; | |
| }; | |
| extal_clk: extal { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| /* This value must be overridden by the board */ | |
| clock-frequency = <0>; | |
| }; | |
| extalr_clk: extalr { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| /* This value must be overridden by the board */ | |
| clock-frequency = <0>; | |
| }; | |
| /* External SCIF clock - to be overridden by boards that provide it */ | |
| scif_clk: scif { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <0>; | |
| }; | |
| soc { | |
| compatible = "simple-bus"; | |
| interrupt-parent = <&gic>; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| ranges; | |
| gic: interrupt-controller@f1010000 { | |
| compatible = "arm,gic-400"; | |
| #interrupt-cells = <3>; | |
| #address-cells = <0>; | |
| interrupt-controller; | |
| reg = <0x0 0xf1010000 0 0x1000>, | |
| <0x0 0xf1020000 0 0x20000>, | |
| <0x0 0xf1040000 0 0x20000>, | |
| <0x0 0xf1060000 0 0x20000>; | |
| interrupts = <GIC_PPI 9 | |
| (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <GIC_PPI 13 | |
| (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 14 | |
| (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 11 | |
| (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 10 | |
| (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; | |
| }; | |
| wdt0: watchdog@e6020000 { | |
| compatible = "renesas,r8a7796-wdt", | |
| "renesas,rcar-gen3-wdt"; | |
| reg = <0 0xe6020000 0 0x0c>; | |
| clocks = <&cpg CPG_MOD 402>; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| status = "disabled"; | |
| }; | |
| gpio0: gpio@e6050000 { | |
| compatible = "renesas,gpio-r8a7796", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6050000 0 0x50>; | |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 0 16>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 912>; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| }; | |
| gpio1: gpio@e6051000 { | |
| compatible = "renesas,gpio-r8a7796", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6051000 0 0x50>; | |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 32 29>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 911>; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| }; | |
| gpio2: gpio@e6052000 { | |
| compatible = "renesas,gpio-r8a7796", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6052000 0 0x50>; | |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 64 15>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 910>; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| }; | |
| gpio3: gpio@e6053000 { | |
| compatible = "renesas,gpio-r8a7796", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6053000 0 0x50>; | |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 96 16>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 909>; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| }; | |
| gpio4: gpio@e6054000 { | |
| compatible = "renesas,gpio-r8a7796", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6054000 0 0x50>; | |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 128 18>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 908>; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| }; | |
| gpio5: gpio@e6055000 { | |
| compatible = "renesas,gpio-r8a7796", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6055000 0 0x50>; | |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 160 26>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 907>; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| }; | |
| gpio6: gpio@e6055400 { | |
| compatible = "renesas,gpio-r8a7796", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6055400 0 0x50>; | |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 192 32>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 906>; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| }; | |
| gpio7: gpio@e6055800 { | |
| compatible = "renesas,gpio-r8a7796", | |
| "renesas,gpio-rcar"; | |
| reg = <0 0xe6055800 0 0x50>; | |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| gpio-ranges = <&pfc 0 224 4>; | |
| #interrupt-cells = <2>; | |
| interrupt-controller; | |
| clocks = <&cpg CPG_MOD 905>; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| }; | |
| pfc: pin-controller@e6060000 { | |
| compatible = "renesas,pfc-r8a7796"; | |
| reg = <0 0xe6060000 0 0x50c>; | |
| }; | |
| cpg: clock-controller@e6150000 { | |
| compatible = "renesas,r8a7796-cpg-mssr"; | |
| reg = <0 0xe6150000 0 0x1000>; | |
| clocks = <&extal_clk>, <&extalr_clk>; | |
| clock-names = "extal", "extalr"; | |
| #clock-cells = <2>; | |
| #power-domain-cells = <0>; | |
| }; | |
| sysc: system-controller@e6180000 { | |
| compatible = "renesas,r8a7796-sysc"; | |
| reg = <0 0xe6180000 0 0x0400>; | |
| #power-domain-cells = <1>; | |
| }; | |
| scif2: serial@e6e88000 { | |
| compatible = "renesas,scif-r8a7796", | |
| "renesas,rcar-gen3-scif", "renesas,scif"; | |
| reg = <0 0xe6e88000 0 64>; | |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cpg CPG_MOD 310>, | |
| <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
| <&scif_clk>; | |
| clock-names = "fck", "brg_int", "scif_clk"; | |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| }; |