| XILINX AXI ETHERNET Device Tree Bindings | |
| -------------------------------------------------------- | |
| Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core | |
| provides connectivity to an external ethernet PHY supporting different | |
| interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two | |
| segments of memory for buffering TX and RX, as well as the capability of | |
| offloading TX/RX checksum calculation off the processor. | |
| Management configuration is done through the AXI interface, while payload is | |
| sent and received through means of an AXI DMA controller. This driver | |
| includes the DMA driver code, so this driver is incompatible with AXI DMA | |
| driver. | |
| For more details about mdio please refer phy.txt file in the same directory. | |
| Required properties: | |
| - compatible : Must be one of "xlnx,axi-ethernet-1.00.a", | |
| "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a" | |
| - reg : Address and length of the IO space. | |
| - interrupts : Should be a list of two interrupt, TX and RX. | |
| - phy-handle : Should point to the external phy device. | |
| See ethernet.txt file in the same directory. | |
| - xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware | |
| Optional properties: | |
| - phy-mode : See ethernet.txt | |
| - xlnx,phy-type : Deprecated, do not use, but still accepted in preference | |
| to phy-mode. | |
| - xlnx,txcsum : 0 or empty for disabling TX checksum offload, | |
| 1 to enable partial TX checksum offload, | |
| 2 to enable full TX checksum offload | |
| - xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload | |
| Example: | |
| axi_ethernet_eth: ethernet@40c00000 { | |
| compatible = "xlnx,axi-ethernet-1.00.a"; | |
| device_type = "network"; | |
| interrupt-parent = <µblaze_0_axi_intc>; | |
| interrupts = <2 0>; | |
| phy-mode = "mii"; | |
| reg = <0x40c00000 0x40000>; | |
| xlnx,rxcsum = <0x2>; | |
| xlnx,rxmem = <0x800>; | |
| xlnx,txcsum = <0x2>; | |
| phy-handle = <&phy0>; | |
| axi_ethernetlite_0_mdio: mdio { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| phy0: phy@0 { | |
| device_type = "ethernet-phy"; | |
| reg = <1>; | |
| }; | |
| }; | |
| }; |