| /* | |
| * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com> | |
| * | |
| * This code is released using a dual license strategy: BSD/GPL | |
| * You can choose the licence that better fits your requirements. | |
| * | |
| * Released under the terms of 3-clause BSD License | |
| * Released under the terms of GNU General Public License Version 2.0 | |
| * | |
| */ | |
| /* Clock Control Unit 1 (CCU1) clock offsets */ | |
| #define CLK_APB3_BUS 0x100 | |
| #define CLK_APB3_I2C1 0x108 | |
| #define CLK_APB3_DAC 0x110 | |
| #define CLK_APB3_ADC0 0x118 | |
| #define CLK_APB3_ADC1 0x120 | |
| #define CLK_APB3_CAN0 0x128 | |
| #define CLK_APB1_BUS 0x200 | |
| #define CLK_APB1_MOTOCON_PWM 0x208 | |
| #define CLK_APB1_I2C0 0x210 | |
| #define CLK_APB1_I2S 0x218 | |
| #define CLK_APB1_CAN1 0x220 | |
| #define CLK_SPIFI 0x300 | |
| #define CLK_CPU_BUS 0x400 | |
| #define CLK_CPU_SPIFI 0x408 | |
| #define CLK_CPU_GPIO 0x410 | |
| #define CLK_CPU_LCD 0x418 | |
| #define CLK_CPU_ETHERNET 0x420 | |
| #define CLK_CPU_USB0 0x428 | |
| #define CLK_CPU_EMC 0x430 | |
| #define CLK_CPU_SDIO 0x438 | |
| #define CLK_CPU_DMA 0x440 | |
| #define CLK_CPU_CORE 0x448 | |
| #define CLK_CPU_SCT 0x468 | |
| #define CLK_CPU_USB1 0x470 | |
| #define CLK_CPU_EMCDIV 0x478 | |
| #define CLK_CPU_FLASHA 0x480 | |
| #define CLK_CPU_FLASHB 0x488 | |
| #define CLK_CPU_M0APP 0x490 | |
| #define CLK_CPU_ADCHS 0x498 | |
| #define CLK_CPU_EEPROM 0x4a0 | |
| #define CLK_CPU_WWDT 0x500 | |
| #define CLK_CPU_UART0 0x508 | |
| #define CLK_CPU_UART1 0x510 | |
| #define CLK_CPU_SSP0 0x518 | |
| #define CLK_CPU_TIMER0 0x520 | |
| #define CLK_CPU_TIMER1 0x528 | |
| #define CLK_CPU_SCU 0x530 | |
| #define CLK_CPU_CREG 0x538 | |
| #define CLK_CPU_RITIMER 0x600 | |
| #define CLK_CPU_UART2 0x608 | |
| #define CLK_CPU_UART3 0x610 | |
| #define CLK_CPU_TIMER2 0x618 | |
| #define CLK_CPU_TIMER3 0x620 | |
| #define CLK_CPU_SSP1 0x628 | |
| #define CLK_CPU_QEI 0x630 | |
| #define CLK_PERIPH_BUS 0x700 | |
| #define CLK_PERIPH_CORE 0x710 | |
| #define CLK_PERIPH_SGPIO 0x718 | |
| #define CLK_USB0 0x800 | |
| #define CLK_USB1 0x900 | |
| #define CLK_SPI 0xA00 | |
| #define CLK_ADCHS 0xB00 | |
| /* Clock Control Unit 2 (CCU2) clock offsets */ | |
| #define CLK_AUDIO 0x100 | |
| #define CLK_APB2_UART3 0x200 | |
| #define CLK_APB2_UART2 0x300 | |
| #define CLK_APB0_UART1 0x400 | |
| #define CLK_APB0_UART0 0x500 | |
| #define CLK_APB2_SSP1 0x600 | |
| #define CLK_APB0_SSP0 0x700 | |
| #define CLK_SDIO 0x800 |