| * Clock bindings for Freescale i.MX25 | |
| Required properties: | |
| - compatible: Should be "fsl,imx25-ccm" | |
| - reg: Address and length of the register set | |
| - interrupts: Should contain CCM interrupt | |
| - #clock-cells: Should be <1> | |
| The clock consumer should specify the desired clock by having the clock | |
| ID in its "clocks" phandle cell. The following is a full list of i.MX25 | |
| clocks and IDs. | |
| Clock ID | |
| --------------------------- | |
| dummy 0 | |
| osc 1 | |
| mpll 2 | |
| upll 3 | |
| mpll_cpu_3_4 4 | |
| cpu_sel 5 | |
| cpu 6 | |
| ahb 7 | |
| usb_div 8 | |
| ipg 9 | |
| per0_sel 10 | |
| per1_sel 11 | |
| per2_sel 12 | |
| per3_sel 13 | |
| per4_sel 14 | |
| per5_sel 15 | |
| per6_sel 16 | |
| per7_sel 17 | |
| per8_sel 18 | |
| per9_sel 19 | |
| per10_sel 20 | |
| per11_sel 21 | |
| per12_sel 22 | |
| per13_sel 23 | |
| per14_sel 24 | |
| per15_sel 25 | |
| per0 26 | |
| per1 27 | |
| per2 28 | |
| per3 29 | |
| per4 30 | |
| per5 31 | |
| per6 32 | |
| per7 33 | |
| per8 34 | |
| per9 35 | |
| per10 36 | |
| per11 37 | |
| per12 38 | |
| per13 39 | |
| per14 40 | |
| per15 41 | |
| csi_ipg_per 42 | |
| epit_ipg_per 43 | |
| esai_ipg_per 44 | |
| esdhc1_ipg_per 45 | |
| esdhc2_ipg_per 46 | |
| gpt_ipg_per 47 | |
| i2c_ipg_per 48 | |
| lcdc_ipg_per 49 | |
| nfc_ipg_per 50 | |
| owire_ipg_per 51 | |
| pwm_ipg_per 52 | |
| sim1_ipg_per 53 | |
| sim2_ipg_per 54 | |
| ssi1_ipg_per 55 | |
| ssi2_ipg_per 56 | |
| uart_ipg_per 57 | |
| ata_ahb 58 | |
| reserved 59 | |
| csi_ahb 60 | |
| emi_ahb 61 | |
| esai_ahb 62 | |
| esdhc1_ahb 63 | |
| esdhc2_ahb 64 | |
| fec_ahb 65 | |
| lcdc_ahb 66 | |
| rtic_ahb 67 | |
| sdma_ahb 68 | |
| slcdc_ahb 69 | |
| usbotg_ahb 70 | |
| reserved 71 | |
| reserved 72 | |
| reserved 73 | |
| reserved 74 | |
| can1_ipg 75 | |
| can2_ipg 76 | |
| csi_ipg 77 | |
| cspi1_ipg 78 | |
| cspi2_ipg 79 | |
| cspi3_ipg 80 | |
| dryice_ipg 81 | |
| ect_ipg 82 | |
| epit1_ipg 83 | |
| epit2_ipg 84 | |
| reserved 85 | |
| esdhc1_ipg 86 | |
| esdhc2_ipg 87 | |
| fec_ipg 88 | |
| reserved 89 | |
| reserved 90 | |
| reserved 91 | |
| gpt1_ipg 92 | |
| gpt2_ipg 93 | |
| gpt3_ipg 94 | |
| gpt4_ipg 95 | |
| reserved 96 | |
| reserved 97 | |
| reserved 98 | |
| iim_ipg 99 | |
| reserved 100 | |
| reserved 101 | |
| kpp_ipg 102 | |
| lcdc_ipg 103 | |
| reserved 104 | |
| pwm1_ipg 105 | |
| pwm2_ipg 106 | |
| pwm3_ipg 107 | |
| pwm4_ipg 108 | |
| rngb_ipg 109 | |
| reserved 110 | |
| scc_ipg 111 | |
| sdma_ipg 112 | |
| sim1_ipg 113 | |
| sim2_ipg 114 | |
| slcdc_ipg 115 | |
| spba_ipg 116 | |
| ssi1_ipg 117 | |
| ssi2_ipg 118 | |
| tsc_ipg 119 | |
| uart1_ipg 120 | |
| uart2_ipg 121 | |
| uart3_ipg 122 | |
| uart4_ipg 123 | |
| uart5_ipg 124 | |
| reserved 125 | |
| wdt_ipg 126 | |
| cko_div 127 | |
| cko_sel 128 | |
| cko 129 | |
| Examples: | |
| clks: ccm@53f80000 { | |
| compatible = "fsl,imx25-ccm"; | |
| reg = <0x53f80000 0x4000>; | |
| interrupts = <31>; | |
| }; | |
| uart1: serial@43f90000 { | |
| compatible = "fsl,imx25-uart", "fsl,imx21-uart"; | |
| reg = <0x43f90000 0x4000>; | |
| interrupts = <45>; | |
| clocks = <&clks 79>, <&clks 50>; | |
| clock-names = "ipg", "per"; | |
| }; |