Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt

Rockchip RK3288 specific extensions to the Analogix Display Port
================================

Required properties:
- compatible: "rockchip,rk3288-dp",
	      "rockchip,rk3399-edp";

- reg: physical base address of the controller and length

- clocks: from common clock binding: handle to dp clock.
	  of memory mapped region.

- clock-names: from common clock binding:
	       Required elements: "dp" "pclk"

- resets: Must contain an entry for each entry in reset-names.
	  See ../reset/reset.txt for details.

- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
- pinctrl-0: pin-control mode. should be <&edp_hpd>

- reset-names: Must include the name "dp"

- rockchip,grf: this soc should set GRF regs, so need get grf here.

- ports: there are 2 port nodes with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt.
    Port 0: contained 2 endpoints, connecting to the output of vop.
    Port 1: contained 1 endpoint, connecting to the input of panel.

Optional property for different chips:
- clocks: from common clock binding: handle to grf_vio clock.

- clock-names: from common clock binding:
	       Required elements: "grf"

For the below properties, please refer to Analogix DP binding document:
 * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
- phys (required)
- phy-names (required)
- hpd-gpios (optional)
- force-hpd (optional)
-------------------------------------------------------------------------------

Example:
	dp-controller: dp@ff970000 {
		compatible = "rockchip,rk3288-dp";
		reg = <0xff970000 0x4000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
		clock-names = "dp", "pclk";
		phys = <&dp_phy>;
		phy-names = "dp";

		rockchip,grf = <&grf>;
		resets = <&cru 111>;
		reset-names = "dp";

		pinctrl-names = "default";
		pinctrl-0 = <&edp_hpd>;


		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			edp_in: port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;
				edp_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_edp>;
				};
				edp_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_edp>;
				};
			};

			edp_out: port@1 {
				reg = <1>;
				#address-cells = <1>;
				#size-cells = <0>;
				edp_out_panel: endpoint {
					reg = <0>;
					remote-endpoint = <&panel_in_edp>
				};
			};
		};
	};

	pinctrl {
		edp {
			edp_hpd: edp-hpd {
				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
			};
		};
	};