| * Amlogic Meson SAR (Successive Approximation Register) A/D converter |
| |
| Required properties: |
| - compatible: depending on the SoC this should be one of: |
| - "amlogic,meson8-saradc" for Meson8 |
| - "amlogic,meson8b-saradc" for Meson8b |
| - "amlogic,meson-gxbb-saradc" for GXBB |
| - "amlogic,meson-gxl-saradc" for GXL |
| - "amlogic,meson-gxm-saradc" for GXM |
| along with the generic "amlogic,meson-saradc" |
| - reg: the physical base address and length of the registers |
| - interrupts: the interrupt indicating end of sampling |
| - clocks: phandle and clock identifier (see clock-names) |
| - clock-names: mandatory clocks: |
| - "clkin" for the reference clock (typically XTAL) |
| - "core" for the SAR ADC core clock |
| optional clocks: |
| - "sana" for the analog clock |
| - "adc_clk" for the ADC (sampling) clock |
| - "adc_sel" for the ADC (sampling) clock mux |
| - vref-supply: the regulator supply for the ADC reference voltage |
| - #io-channel-cells: must be 1, see ../iio-bindings.txt |
| |
| Example: |
| saradc: adc@8680 { |
| compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; |
| #io-channel-cells = <1>; |
| reg = <0x0 0x8680 0x0 0x34>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&xtal>, |
| <&clkc CLKID_SAR_ADC>, |
| <&clkc CLKID_SANA>, |
| <&clkc CLKID_SAR_ADC_CLK>, |
| <&clkc CLKID_SAR_ADC_SEL>; |
| clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; |
| }; |
