| Freescale vf610 Analog to Digital Converter bindings |
| |
| The devicetree bindings are for the new ADC driver written for |
| vf610/i.MX6slx and upward SoCs from Freescale. |
| |
| Required properties: |
| - compatible: Should contain "fsl,vf610-adc" |
| - reg: Offset and length of the register set for the device |
| - interrupts: Should contain the interrupt for the device |
| - clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock. |
| - clock-names: Must contain "adc", matching entry in the clocks property. |
| - vref-supply: The regulator supply ADC reference voltage. |
| |
| Recommended properties: |
| - fsl,adck-max-frequency: Maximum frequencies according to datasheets operating |
| requirements. Three values are required, depending on conversion mode: |
| - Frequency in normal mode (ADLPC=0, ADHSC=0) |
| - Frequency in high-speed mode (ADLPC=0, ADHSC=1) |
| - Frequency in low-power mode (ADLPC=1, ADHSC=0) |
| - min-sample-time: Minimum sampling time in nanoseconds. This value has |
| to be chosen according to the conversion mode and the connected analog |
| source resistance (R_as) and capacitance (C_as). Refer the datasheet's |
| operating requirements. A safe default across a wide range of R_as and |
| C_as as well as conversion modes is 1000ns. |
| |
| Example: |
| adc0: adc@4003b000 { |
| compatible = "fsl,vf610-adc"; |
| reg = <0x4003b000 0x1000>; |
| interrupts = <0 53 0x04>; |
| clocks = <&clks VF610_CLK_ADC0>; |
| clock-names = "adc"; |
| fsl,adck-max-frequency = <30000000>, <40000000>, |
| <20000000>; |
| vref-supply = <®_vcc_3v3_mcu>; |
| }; |
