| /* |
| * skl-tplg-interface.h - Intel DSP FW private data interface |
| * |
| * Copyright (C) 2015 Intel Corp |
| * Author: Jeeja KP <jeeja.kp@intel.com> |
| * Nilofer, Samreen <samreen.nilofer@intel.com> |
| * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as version 2, as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, but |
| * WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| * General Public License for more details. |
| */ |
| |
| #ifndef __HDA_TPLG_INTERFACE_H__ |
| #define __HDA_TPLG_INTERFACE_H__ |
| |
| /** |
| * enum skl_ch_cfg - channel configuration |
| * |
| * @SKL_CH_CFG_MONO: One channel only |
| * @SKL_CH_CFG_STEREO: L & R |
| * @SKL_CH_CFG_2_1: L, R & LFE |
| * @SKL_CH_CFG_3_0: L, C & R |
| * @SKL_CH_CFG_3_1: L, C, R & LFE |
| * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs |
| * @SKL_CH_CFG_4_0: L, C, R & Cs |
| * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs |
| * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE |
| * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two |
| * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ] |
| * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ] |
| * @SKL_CH_CFG_INVALID: Invalid |
| */ |
| enum skl_ch_cfg { |
| SKL_CH_CFG_MONO = 0, |
| SKL_CH_CFG_STEREO = 1, |
| SKL_CH_CFG_2_1 = 2, |
| SKL_CH_CFG_3_0 = 3, |
| SKL_CH_CFG_3_1 = 4, |
| SKL_CH_CFG_QUATRO = 5, |
| SKL_CH_CFG_4_0 = 6, |
| SKL_CH_CFG_5_0 = 7, |
| SKL_CH_CFG_5_1 = 8, |
| SKL_CH_CFG_DUAL_MONO = 9, |
| SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10, |
| SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11, |
| SKL_CH_CFG_INVALID |
| }; |
| |
| enum skl_module_type { |
| SKL_MODULE_TYPE_MIXER = 0, |
| SKL_MODULE_TYPE_COPIER, |
| SKL_MODULE_TYPE_UPDWMIX, |
| SKL_MODULE_TYPE_SRCINT |
| }; |
| |
| enum skl_core_affinity { |
| SKL_AFFINITY_CORE_0 = 0, |
| SKL_AFFINITY_CORE_1, |
| SKL_AFFINITY_CORE_MAX |
| }; |
| |
| enum skl_pipe_conn_type { |
| SKL_PIPE_CONN_TYPE_NONE = 0, |
| SKL_PIPE_CONN_TYPE_FE, |
| SKL_PIPE_CONN_TYPE_BE |
| }; |
| |
| enum skl_hw_conn_type { |
| SKL_CONN_NONE = 0, |
| SKL_CONN_SOURCE = 1, |
| SKL_CONN_SINK = 2 |
| }; |
| |
| enum skl_dev_type { |
| SKL_DEVICE_BT = 0x0, |
| SKL_DEVICE_DMIC = 0x1, |
| SKL_DEVICE_I2S = 0x2, |
| SKL_DEVICE_SLIMBUS = 0x3, |
| SKL_DEVICE_HDALINK = 0x4, |
| SKL_DEVICE_NONE |
| }; |
| #endif |
