| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version |
| from ../../inst/crisp/doc/cpu_vect.r |
| version . */ |
| |
| #ifndef _______INST_CRISP_DOC_CPU_VECT_R |
| #define _______INST_CRISP_DOC_CPU_VECT_R |
| #define NMI_INTR_VECT 0x00 |
| #define RESERVED_1_INTR_VECT 0x01 |
| #define RESERVED_2_INTR_VECT 0x02 |
| #define SINGLE_STEP_INTR_VECT 0x03 |
| #define INSTR_TLB_REFILL_INTR_VECT 0x04 |
| #define INSTR_TLB_INV_INTR_VECT 0x05 |
| #define INSTR_TLB_ACC_INTR_VECT 0x06 |
| #define TLB_EX_INTR_VECT 0x07 |
| #define DATA_TLB_REFILL_INTR_VECT 0x08 |
| #define DATA_TLB_INV_INTR_VECT 0x09 |
| #define DATA_TLB_ACC_INTR_VECT 0x0a |
| #define DATA_TLB_WE_INTR_VECT 0x0b |
| #define HW_BP_INTR_VECT 0x0c |
| #define RESERVED_D_INTR_VECT 0x0d |
| #define RESERVED_E_INTR_VECT 0x0e |
| #define RESERVED_F_INTR_VECT 0x0f |
| #define BREAK_0_INTR_VECT 0x10 |
| #define BREAK_1_INTR_VECT 0x11 |
| #define BREAK_2_INTR_VECT 0x12 |
| #define BREAK_3_INTR_VECT 0x13 |
| #define BREAK_4_INTR_VECT 0x14 |
| #define BREAK_5_INTR_VECT 0x15 |
| #define BREAK_6_INTR_VECT 0x16 |
| #define BREAK_7_INTR_VECT 0x17 |
| #define BREAK_8_INTR_VECT 0x18 |
| #define BREAK_9_INTR_VECT 0x19 |
| #define BREAK_10_INTR_VECT 0x1a |
| #define BREAK_11_INTR_VECT 0x1b |
| #define BREAK_12_INTR_VECT 0x1c |
| #define BREAK_13_INTR_VECT 0x1d |
| #define BREAK_14_INTR_VECT 0x1e |
| #define BREAK_15_INTR_VECT 0x1f |
| #define MULTIPLE_INTR_VECT 0x30 |
| |
| #endif |
