| NVIDIA Tegra20/Tegra30 SLINK controller. |
| |
| Required properties: |
| - compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink". |
| - reg: Should contain SLINK registers location and length. |
| - interrupts: Should contain SLINK interrupts. |
| - clocks : Must contain one entry, for the module clock. |
| See ../clocks/clock-bindings.txt for details. |
| - resets : Must contain an entry for each entry in reset-names. |
| See ../reset/reset.txt for details. |
| - reset-names : Must include the following entries: |
| - spi |
| - dmas : Must contain an entry for each entry in clock-names. |
| See ../dma/dma.txt for details. |
| - dma-names : Must include the following entries: |
| - rx |
| - tx |
| |
| Recommended properties: |
| - spi-max-frequency: Definition as per |
| Documentation/devicetree/bindings/spi/spi-bus.txt |
| |
| Example: |
| |
| spi@7000d600 { |
| compatible = "nvidia,tegra20-slink"; |
| reg = <0x7000d600 0x200>; |
| interrupts = <0 82 0x04>; |
| spi-max-frequency = <25000000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 44>; |
| resets = <&tegra_car 44>; |
| reset-names = "spi"; |
| dmas = <&apbdma 16>, <&apbdma 16>; |
| dma-names = "rx", "tx"; |
| }; |
