| NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. |
| |
| Required properties: |
| - compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". |
| - reg: Should contain UART controller registers location and length. |
| - interrupts: Should contain UART controller interrupts. |
| - clocks: Must contain one entry, for the module clock. |
| See ../clocks/clock-bindings.txt for details. |
| - resets : Must contain an entry for each entry in reset-names. |
| See ../reset/reset.txt for details. |
| - reset-names : Must include the following entries: |
| - serial |
| - dmas : Must contain an entry for each entry in dma-names. |
| See ../dma/dma.txt for details. |
| - dma-names : Must include the following entries: |
| - rx |
| - tx |
| |
| Optional properties: |
| - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable |
| only if all 8 lines of UART controller are pinmuxed. |
| |
| Example: |
| |
| serial@70006000 { |
| compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart"; |
| reg = <0x70006000 0x40>; |
| reg-shift = <2>; |
| interrupts = <0 36 0x04>; |
| nvidia,enable-modem-interrupt; |
| clocks = <&tegra_car 6>; |
| resets = <&tegra_car 6>; |
| reset-names = "serial"; |
| dmas = <&apbdma 8>, <&apbdma 8>; |
| dma-names = "rx", "tx"; |
| }; |
