| config BF51x | |
| def_bool y | |
| depends on (BF512 || BF514 || BF516 || BF518) | |
| if (BF51x) | |
| source "arch/blackfin/mach-bf518/boards/Kconfig" | |
| menu "BF518 Specific Configuration" | |
| comment "Alternative Multiplexing Scheme" | |
| choice | |
| prompt "PWM Channel Pins" | |
| default BF518_PWM_ALL_PORTF | |
| help | |
| Select pins used for the PWM channels: | |
| PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL | |
| See the Hardware Reference Manual for more details. | |
| config BF518_PWM_ALL_PORTF | |
| bool "PF1 - PF6" | |
| help | |
| PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL} | |
| config BF518_PWM_PORTF_PORTG | |
| bool "PF11 - PF14 / PG1 - PG2" | |
| help | |
| PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL} | |
| PG{1,2} <-> PWM_{CH,CL} | |
| endchoice | |
| choice | |
| prompt "PWM Sync Pin" | |
| default BF518_PWM_SYNC_PF7 | |
| help | |
| Select the pin used for PWM_SYNC. | |
| See the Hardware Reference Manual for more details. | |
| config BF518_PWM_SYNC_PF7 | |
| bool "PF7" | |
| config BF518_PWM_SYNC_PF15 | |
| bool "PF15" | |
| endchoice | |
| choice | |
| prompt "PWM Trip B Pin" | |
| default BF518_PWM_TRIPB_PG10 | |
| help | |
| Select the pin used for PWM_TRIPB. | |
| See the Hardware Reference Manual for more details. | |
| config BF518_PWM_TRIPB_PG10 | |
| bool "PG10" | |
| config BF518_PWM_TRIPB_PG14 | |
| bool "PG14" | |
| endchoice | |
| choice | |
| prompt "PPI / Timer Pins" | |
| default BF518_PPI_TMR_PG5 | |
| help | |
| Select pins used for PPI/Timer: | |
| PPICLK PPIFS1 PPIFS2 | |
| TMRCLK TMR0 TMR1 | |
| See the Hardware Reference Manual for more details. | |
| config BF518_PPI_TMR_PG5 | |
| bool "PG5 - PG7" | |
| help | |
| PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2} | |
| config BF518_PPI_TMR_PG12 | |
| bool "PG12 - PG14" | |
| help | |
| PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2} | |
| endchoice | |
| comment "Hysteresis/Schmitt Trigger Control" | |
| config BFIN_HYSTERESIS_CONTROL | |
| bool "Enable Hysteresis Control" | |
| help | |
| The ADSP-BF51x allows to control input hysteresis for Port F, | |
| Port G and Port H and other processor signal inputs. | |
| The Schmitt trigger enables can be set only for pin groups. | |
| Saying Y will overwrite the default reset or boot loader | |
| initialization. | |
| menu "PORT F" | |
| depends on BFIN_HYSTERESIS_CONTROL | |
| config GPIO_HYST_PORTF_0_7 | |
| bool "Enable Hysteresis on PORTF {0...7}" | |
| config GPIO_HYST_PORTF_8_9 | |
| bool "Enable Hysteresis on PORTF {8, 9}" | |
| config GPIO_HYST_PORTF_10 | |
| bool "Enable Hysteresis on PORTF 10" | |
| config GPIO_HYST_PORTF_11 | |
| bool "Enable Hysteresis on PORTF 11" | |
| config GPIO_HYST_PORTF_12_13 | |
| bool "Enable Hysteresis on PORTF {12, 13}" | |
| config GPIO_HYST_PORTF_14_15 | |
| bool "Enable Hysteresis on PORTF {14, 15}" | |
| endmenu | |
| menu "PORT G" | |
| depends on BFIN_HYSTERESIS_CONTROL | |
| config GPIO_HYST_PORTG_0 | |
| bool "Enable Hysteresis on PORTG 0" | |
| config GPIO_HYST_PORTG_1_4 | |
| bool "Enable Hysteresis on PORTG {1...4}" | |
| config GPIO_HYST_PORTG_5_6 | |
| bool "Enable Hysteresis on PORTG {5, 6}" | |
| config GPIO_HYST_PORTG_7_8 | |
| bool "Enable Hysteresis on PORTG {7, 8}" | |
| config GPIO_HYST_PORTG_9 | |
| bool "Enable Hysteresis on PORTG 9" | |
| config GPIO_HYST_PORTG_10 | |
| bool "Enable Hysteresis on PORTG 10" | |
| config GPIO_HYST_PORTG_11_13 | |
| bool "Enable Hysteresis on PORTG {11...13}" | |
| config GPIO_HYST_PORTG_14_15 | |
| bool "Enable Hysteresis on PORTG {14, 15}" | |
| endmenu | |
| menu "PORT H" | |
| depends on BFIN_HYSTERESIS_CONTROL | |
| config GPIO_HYST_PORTH_0_7 | |
| bool "Enable Hysteresis on PORTH {0...7}" | |
| endmenu | |
| menu "None-GPIO" | |
| depends on BFIN_HYSTERESIS_CONTROL | |
| config NONEGPIO_HYST_NMI_RST_BMODE | |
| bool "Enable Hysteresis on {NMI, RESET, BMODE}" | |
| config NONEGPIO_HYST_JTAG | |
| bool "Enable Hysteresis on JTAG" | |
| endmenu | |
| comment "Interrupt Priority Assignment" | |
| menu "Priority" | |
| config IRQ_PLL_WAKEUP | |
| int "IRQ_PLL_WAKEUP" | |
| default 7 | |
| config IRQ_DMA0_ERROR | |
| int "IRQ_DMA0_ERROR" | |
| default 7 | |
| config IRQ_DMAR0_BLK | |
| int "IRQ_DMAR0_BLK" | |
| default 7 | |
| config IRQ_DMAR1_BLK | |
| int "IRQ_DMAR1_BLK" | |
| default 7 | |
| config IRQ_DMAR0_OVR | |
| int "IRQ_DMAR0_OVR" | |
| default 7 | |
| config IRQ_DMAR1_OVR | |
| int "IRQ_DMAR1_OVR" | |
| default 7 | |
| config IRQ_PPI_ERROR | |
| int "IRQ_PPI_ERROR" | |
| default 7 | |
| config IRQ_MAC_ERROR | |
| int "IRQ_MAC_ERROR" | |
| default 7 | |
| config IRQ_SPORT0_ERROR | |
| int "IRQ_SPORT0_ERROR" | |
| default 7 | |
| config IRQ_SPORT1_ERROR | |
| int "IRQ_SPORT1_ERROR" | |
| default 7 | |
| config IRQ_PTP_ERROR | |
| int "IRQ_PTP_ERROR" | |
| default 7 | |
| config IRQ_UART0_ERROR | |
| int "IRQ_UART0_ERROR" | |
| default 7 | |
| config IRQ_UART1_ERROR | |
| int "IRQ_UART1_ERROR" | |
| default 7 | |
| config IRQ_RTC | |
| int "IRQ_RTC" | |
| default 8 | |
| config IRQ_PPI | |
| int "IRQ_PPI" | |
| default 8 | |
| config IRQ_SPORT0_RX | |
| int "IRQ_SPORT0_RX" | |
| default 9 | |
| config IRQ_SPORT0_TX | |
| int "IRQ_SPORT0_TX" | |
| default 9 | |
| config IRQ_SPORT1_RX | |
| int "IRQ_SPORT1_RX" | |
| default 9 | |
| config IRQ_SPORT1_TX | |
| int "IRQ_SPORT1_TX" | |
| default 9 | |
| config IRQ_TWI | |
| int "IRQ_TWI" | |
| default 10 | |
| config IRQ_SPI0 | |
| int "IRQ_SPI" | |
| default 10 | |
| config IRQ_UART0_RX | |
| int "IRQ_UART0_RX" | |
| default 10 | |
| config IRQ_UART0_TX | |
| int "IRQ_UART0_TX" | |
| default 10 | |
| config IRQ_UART1_RX | |
| int "IRQ_UART1_RX" | |
| default 10 | |
| config IRQ_UART1_TX | |
| int "IRQ_UART1_TX" | |
| default 10 | |
| config IRQ_OPTSEC | |
| int "IRQ_OPTSEC" | |
| default 11 | |
| config IRQ_CNT | |
| int "IRQ_CNT" | |
| default 11 | |
| config IRQ_MAC_RX | |
| int "IRQ_MAC_RX" | |
| default 11 | |
| config IRQ_PORTH_INTA | |
| int "IRQ_PORTH_INTA" | |
| default 11 | |
| config IRQ_MAC_TX | |
| int "IRQ_MAC_TX/NFC" | |
| default 11 | |
| config IRQ_PORTH_INTB | |
| int "IRQ_PORTH_INTB" | |
| default 11 | |
| config IRQ_TIMER0 | |
| int "IRQ_TIMER0" | |
| default 7 if TICKSOURCE_GPTMR0 | |
| default 8 | |
| config IRQ_TIMER1 | |
| int "IRQ_TIMER1" | |
| default 12 | |
| config IRQ_TIMER2 | |
| int "IRQ_TIMER2" | |
| default 12 | |
| config IRQ_TIMER3 | |
| int "IRQ_TIMER3" | |
| default 12 | |
| config IRQ_TIMER4 | |
| int "IRQ_TIMER4" | |
| default 12 | |
| config IRQ_TIMER5 | |
| int "IRQ_TIMER5" | |
| default 12 | |
| config IRQ_TIMER6 | |
| int "IRQ_TIMER6" | |
| default 12 | |
| config IRQ_TIMER7 | |
| int "IRQ_TIMER7" | |
| default 12 | |
| config IRQ_PORTG_INTA | |
| int "IRQ_PORTG_INTA" | |
| default 12 | |
| config IRQ_PORTG_INTB | |
| int "IRQ_PORTG_INTB" | |
| default 12 | |
| config IRQ_MEM_DMA0 | |
| int "IRQ_MEM_DMA0" | |
| default 13 | |
| config IRQ_MEM_DMA1 | |
| int "IRQ_MEM_DMA1" | |
| default 13 | |
| config IRQ_WATCH | |
| int "IRQ_WATCH" | |
| default 13 | |
| config IRQ_PORTF_INTA | |
| int "IRQ_PORTF_INTA" | |
| default 13 | |
| config IRQ_PORTF_INTB | |
| int "IRQ_PORTF_INTB" | |
| default 13 | |
| config IRQ_SPI0_ERROR | |
| int "IRQ_SPI0_ERROR" | |
| default 7 | |
| config IRQ_SPI1_ERROR | |
| int "IRQ_SPI1_ERROR" | |
| default 7 | |
| config IRQ_RSI_INT0 | |
| int "IRQ_RSI_INT0" | |
| default 7 | |
| config IRQ_RSI_INT1 | |
| int "IRQ_RSI_INT1" | |
| default 7 | |
| config IRQ_PWM_TRIP | |
| int "IRQ_PWM_TRIP" | |
| default 10 | |
| config IRQ_PWM_SYNC | |
| int "IRQ_PWM_SYNC" | |
| default 10 | |
| config IRQ_PTP_STAT | |
| int "IRQ_PTP_STAT" | |
| default 10 | |
| help | |
| Enter the priority numbers between 7-13 ONLY. Others are Reserved. | |
| This applies to all the above. It is not recommended to assign the | |
| highest priority number 7 to UART or any other device. | |
| endmenu | |
| endmenu | |
| endif |