Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 1 | /* |
| 2 | * AMD Alchemy DB1200 Referrence Board |
| 3 | * Board Registers defines. |
| 4 | * |
| 5 | * ######################################################################## |
| 6 | * |
| 7 | * This program is free software; you can distribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License (Version 2) as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 18 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 19 | * |
| 20 | * ######################################################################## |
| 21 | * |
| 22 | * |
| 23 | */ |
| 24 | #ifndef __ASM_DB1200_H |
| 25 | #define __ASM_DB1200_H |
| 26 | |
| 27 | #include <linux/types.h> |
| 28 | |
| 29 | // This is defined in au1000.h with bogus value |
| 30 | #undef AU1X00_EXTERNAL_INT |
| 31 | |
| 32 | #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX |
| 33 | #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX |
| 34 | #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX |
| 35 | #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX |
| 36 | |
| 37 | /* SPI and SMB are muxed on the Pb1200 board. |
| 38 | Refer to board documentation. |
| 39 | */ |
| 40 | #define SPI_PSC_BASE PSC0_BASE_ADDR |
| 41 | #define SMBUS_PSC_BASE PSC0_BASE_ADDR |
| 42 | /* AC97 and I2S are muxed on the Pb1200 board. |
| 43 | Refer to board documentation. |
| 44 | */ |
| 45 | #define AC97_PSC_BASE PSC1_BASE_ADDR |
| 46 | #define I2S_PSC_BASE PSC1_BASE_ADDR |
| 47 | |
| 48 | #define BCSR_KSEG1_ADDR 0xB9800000 |
| 49 | |
| 50 | typedef volatile struct |
| 51 | { |
| 52 | /*00*/ u16 whoami; |
| 53 | u16 reserved0; |
| 54 | /*04*/ u16 status; |
| 55 | u16 reserved1; |
| 56 | /*08*/ u16 switches; |
| 57 | u16 reserved2; |
| 58 | /*0C*/ u16 resets; |
| 59 | u16 reserved3; |
| 60 | |
| 61 | /*10*/ u16 pcmcia; |
| 62 | u16 reserved4; |
| 63 | /*14*/ u16 board; |
| 64 | u16 reserved5; |
| 65 | /*18*/ u16 disk_leds; |
| 66 | u16 reserved6; |
| 67 | /*1C*/ u16 system; |
| 68 | u16 reserved7; |
| 69 | |
| 70 | /*20*/ u16 intclr; |
| 71 | u16 reserved8; |
| 72 | /*24*/ u16 intset; |
| 73 | u16 reserved9; |
| 74 | /*28*/ u16 intclr_mask; |
| 75 | u16 reserved10; |
| 76 | /*2C*/ u16 intset_mask; |
| 77 | u16 reserved11; |
| 78 | |
| 79 | /*30*/ u16 sig_status; |
| 80 | u16 reserved12; |
| 81 | /*34*/ u16 int_status; |
| 82 | u16 reserved13; |
| 83 | /*38*/ u16 reserved14; |
| 84 | u16 reserved15; |
| 85 | /*3C*/ u16 reserved16; |
| 86 | u16 reserved17; |
| 87 | |
| 88 | } BCSR; |
| 89 | |
| 90 | static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; |
| 91 | |
| 92 | /* |
| 93 | * Register bit definitions for the BCSRs |
| 94 | */ |
| 95 | #define BCSR_WHOAMI_DCID 0x000F |
| 96 | #define BCSR_WHOAMI_CPLD 0x00F0 |
| 97 | #define BCSR_WHOAMI_BOARD 0x0F00 |
| 98 | |
| 99 | #define BCSR_STATUS_PCMCIA0VS 0x0003 |
| 100 | #define BCSR_STATUS_PCMCIA1VS 0x000C |
| 101 | #define BCSR_STATUS_SWAPBOOT 0x0040 |
| 102 | #define BCSR_STATUS_FLASHBUSY 0x0100 |
| 103 | #define BCSR_STATUS_IDECBLID 0x0200 |
| 104 | #define BCSR_STATUS_SD0WP 0x0400 |
| 105 | #define BCSR_STATUS_U0RXD 0x1000 |
| 106 | #define BCSR_STATUS_U1RXD 0x2000 |
| 107 | |
| 108 | #define BCSR_SWITCHES_OCTAL 0x00FF |
| 109 | #define BCSR_SWITCHES_DIP_1 0x0080 |
| 110 | #define BCSR_SWITCHES_DIP_2 0x0040 |
| 111 | #define BCSR_SWITCHES_DIP_3 0x0020 |
| 112 | #define BCSR_SWITCHES_DIP_4 0x0010 |
| 113 | #define BCSR_SWITCHES_DIP_5 0x0008 |
| 114 | #define BCSR_SWITCHES_DIP_6 0x0004 |
| 115 | #define BCSR_SWITCHES_DIP_7 0x0002 |
| 116 | #define BCSR_SWITCHES_DIP_8 0x0001 |
| 117 | #define BCSR_SWITCHES_ROTARY 0x0F00 |
| 118 | |
| 119 | #define BCSR_RESETS_ETH 0x0001 |
| 120 | #define BCSR_RESETS_CAMERA 0x0002 |
| 121 | #define BCSR_RESETS_DC 0x0004 |
| 122 | #define BCSR_RESETS_IDE 0x0008 |
| 123 | #define BCSR_RESETS_TV 0x0010 |
| 124 | /* not resets but in the same register */ |
| 125 | #define BCSR_RESETS_PWMR1mUX 0x0800 |
| 126 | #define BCSR_RESETS_PCS0MUX 0x1000 |
| 127 | #define BCSR_RESETS_PCS1MUX 0x2000 |
| 128 | #define BCSR_RESETS_SPISEL 0x4000 |
| 129 | |
| 130 | #define BCSR_PCMCIA_PC0VPP 0x0003 |
| 131 | #define BCSR_PCMCIA_PC0VCC 0x000C |
| 132 | #define BCSR_PCMCIA_PC0DRVEN 0x0010 |
| 133 | #define BCSR_PCMCIA_PC0RST 0x0080 |
| 134 | #define BCSR_PCMCIA_PC1VPP 0x0300 |
| 135 | #define BCSR_PCMCIA_PC1VCC 0x0C00 |
| 136 | #define BCSR_PCMCIA_PC1DRVEN 0x1000 |
| 137 | #define BCSR_PCMCIA_PC1RST 0x8000 |
| 138 | |
| 139 | #define BCSR_BOARD_LCDVEE 0x0001 |
| 140 | #define BCSR_BOARD_LCDVDD 0x0002 |
| 141 | #define BCSR_BOARD_LCDBL 0x0004 |
| 142 | #define BCSR_BOARD_CAMSNAP 0x0010 |
| 143 | #define BCSR_BOARD_CAMPWR 0x0020 |
| 144 | #define BCSR_BOARD_SD0PWR 0x0040 |
| 145 | |
| 146 | #define BCSR_LEDS_DECIMALS 0x0003 |
| 147 | #define BCSR_LEDS_LED0 0x0100 |
| 148 | #define BCSR_LEDS_LED1 0x0200 |
| 149 | #define BCSR_LEDS_LED2 0x0400 |
| 150 | #define BCSR_LEDS_LED3 0x0800 |
| 151 | |
| 152 | #define BCSR_SYSTEM_POWEROFF 0x4000 |
| 153 | #define BCSR_SYSTEM_RESET 0x8000 |
| 154 | |
| 155 | /* Bit positions for the different interrupt sources */ |
| 156 | #define BCSR_INT_IDE 0x0001 |
| 157 | #define BCSR_INT_ETH 0x0002 |
| 158 | #define BCSR_INT_PC0 0x0004 |
| 159 | #define BCSR_INT_PC0STSCHG 0x0008 |
| 160 | #define BCSR_INT_PC1 0x0010 |
| 161 | #define BCSR_INT_PC1STSCHG 0x0020 |
| 162 | #define BCSR_INT_DC 0x0040 |
| 163 | #define BCSR_INT_FLASHBUSY 0x0080 |
| 164 | #define BCSR_INT_PC0INSERT 0x0100 |
| 165 | #define BCSR_INT_PC0EJECT 0x0200 |
| 166 | #define BCSR_INT_PC1INSERT 0x0400 |
| 167 | #define BCSR_INT_PC1EJECT 0x0800 |
| 168 | #define BCSR_INT_SD0INSERT 0x1000 |
| 169 | #define BCSR_INT_SD0EJECT 0x2000 |
| 170 | |
| 171 | #define AU1XXX_SMC91111_PHYS_ADDR (0x19000300) |
| 172 | #define AU1XXX_SMC91111_IRQ DB1200_ETH_INT |
| 173 | |
| 174 | #define AU1XXX_ATA_PHYS_ADDR (0x18800000) |
| 175 | #define AU1XXX_ATA_PHYS_LEN (0x100) |
| 176 | #define AU1XXX_ATA_REG_OFFSET (5) |
| 177 | #define AU1XXX_ATA_INT DB1200_IDE_INT |
| 178 | #define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1; |
| 179 | #define AU1XXX_ATA_RQSIZE 128 |
| 180 | |
| 181 | #define NAND_PHYS_ADDR 0x20000000 |
| 182 | |
| 183 | /* |
| 184 | * External Interrupts for Pb1200 as of 8/6/2004. |
| 185 | * Bit positions in the CPLD registers can be calculated by taking |
| 186 | * the interrupt define and subtracting the DB1200_INT_BEGIN value. |
| 187 | * *example: IDE bis pos is = 64 - 64 |
| 188 | ETH bit pos is = 65 - 64 |
| 189 | */ |
| 190 | #define DB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1) |
| 191 | #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0) |
| 192 | #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1) |
| 193 | #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2) |
| 194 | #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3) |
| 195 | #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4) |
| 196 | #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5) |
| 197 | #define DB1200_DC_INT (DB1200_INT_BEGIN + 6) |
| 198 | #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7) |
| 199 | #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8) |
| 200 | #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9) |
| 201 | #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10) |
| 202 | #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11) |
| 203 | #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12) |
| 204 | #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13) |
| 205 | |
| 206 | #define DB1200_INT_END (DB1200_INT_BEGIN + 15) |
| 207 | |
| 208 | /* For drivers/pcmcia/au1000_db1x00.c */ |
Pete Popov | d646082 | 2005-09-17 00:38:10 +0000 | [diff] [blame] | 209 | |
| 210 | /* PCMCIA Db1x00 specific defines */ |
| 211 | |
| 212 | #define PCMCIA_MAX_SOCK 1 |
| 213 | #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) |
| 214 | |
| 215 | /* VPP/VCC */ |
| 216 | #define SET_VCC_VPP(VCC, VPP, SLOT)\ |
| 217 | ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) |
| 218 | |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 219 | #define BOARD_PC0_INT DB1200_PC0_INT |
| 220 | #define BOARD_PC1_INT DB1200_PC1_INT |
| 221 | #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) |
| 222 | |
Ralf Baechle | bdc3c3c | 2005-11-17 16:23:42 +0000 | [diff] [blame] | 223 | /* Nand chip select */ |
| 224 | #define NAND_CS 1 |
| 225 | |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 226 | #endif /* __ASM_DB1200_H */ |
| 227 | |