Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ohci1394.c - driver for OHCI 1394 boards |
| 3 | * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au> |
| 4 | * Gord Peters <GordPeters@smarttech.com> |
| 5 | * 2001 Ben Collins <bcollins@debian.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software Foundation, |
| 19 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * Things known to be working: |
| 24 | * . Async Request Transmit |
| 25 | * . Async Response Receive |
| 26 | * . Async Request Receive |
| 27 | * . Async Response Transmit |
| 28 | * . Iso Receive |
| 29 | * . DMA mmap for iso receive |
| 30 | * . Config ROM generation |
| 31 | * |
| 32 | * Things implemented, but still in test phase: |
| 33 | * . Iso Transmit |
| 34 | * . Async Stream Packets Transmit (Receive done via Iso interface) |
| 35 | * |
| 36 | * Things not implemented: |
| 37 | * . DMA error recovery |
| 38 | * |
| 39 | * Known bugs: |
| 40 | * . devctl BUS_RESET arg confusion (reset type or root holdoff?) |
| 41 | * added LONG_RESET_ROOT and SHORT_RESET_ROOT for root holdoff --kk |
| 42 | */ |
| 43 | |
| 44 | /* |
| 45 | * Acknowledgments: |
| 46 | * |
| 47 | * Adam J Richter <adam@yggdrasil.com> |
| 48 | * . Use of pci_class to find device |
| 49 | * |
| 50 | * Emilie Chung <emilie.chung@axis.com> |
| 51 | * . Tip on Async Request Filter |
| 52 | * |
| 53 | * Pascal Drolet <pascal.drolet@informission.ca> |
| 54 | * . Various tips for optimization and functionnalities |
| 55 | * |
| 56 | * Robert Ficklin <rficklin@westengineering.com> |
| 57 | * . Loop in irq_handler |
| 58 | * |
| 59 | * James Goodwin <jamesg@Filanet.com> |
| 60 | * . Various tips on initialization, self-id reception, etc. |
| 61 | * |
| 62 | * Albrecht Dress <ad@mpifr-bonn.mpg.de> |
| 63 | * . Apple PowerBook detection |
| 64 | * |
| 65 | * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de> |
| 66 | * . Reset the board properly before leaving + misc cleanups |
| 67 | * |
| 68 | * Leon van Stuivenberg <leonvs@iae.nl> |
| 69 | * . Bug fixes |
| 70 | * |
| 71 | * Ben Collins <bcollins@debian.org> |
| 72 | * . Working big-endian support |
| 73 | * . Updated to 2.4.x module scheme (PCI aswell) |
| 74 | * . Config ROM generation |
| 75 | * |
| 76 | * Manfred Weihs <weihs@ict.tuwien.ac.at> |
| 77 | * . Reworked code for initiating bus resets |
| 78 | * (long, short, with or without hold-off) |
| 79 | * |
| 80 | * Nandu Santhi <contactnandu@users.sourceforge.net> |
| 81 | * . Added support for nVidia nForce2 onboard Firewire chipset |
| 82 | * |
| 83 | */ |
| 84 | |
| 85 | #include <linux/config.h> |
| 86 | #include <linux/kernel.h> |
| 87 | #include <linux/list.h> |
| 88 | #include <linux/slab.h> |
| 89 | #include <linux/interrupt.h> |
| 90 | #include <linux/wait.h> |
| 91 | #include <linux/errno.h> |
| 92 | #include <linux/module.h> |
| 93 | #include <linux/moduleparam.h> |
| 94 | #include <linux/pci.h> |
| 95 | #include <linux/fs.h> |
| 96 | #include <linux/poll.h> |
| 97 | #include <asm/byteorder.h> |
| 98 | #include <asm/atomic.h> |
| 99 | #include <asm/uaccess.h> |
| 100 | #include <linux/delay.h> |
| 101 | #include <linux/spinlock.h> |
| 102 | |
| 103 | #include <asm/pgtable.h> |
| 104 | #include <asm/page.h> |
| 105 | #include <asm/irq.h> |
| 106 | #include <linux/sched.h> |
| 107 | #include <linux/types.h> |
| 108 | #include <linux/vmalloc.h> |
| 109 | #include <linux/init.h> |
| 110 | |
| 111 | #ifdef CONFIG_PPC_PMAC |
| 112 | #include <asm/machdep.h> |
| 113 | #include <asm/pmac_feature.h> |
| 114 | #include <asm/prom.h> |
| 115 | #include <asm/pci-bridge.h> |
| 116 | #endif |
| 117 | |
| 118 | #include "csr1212.h" |
| 119 | #include "ieee1394.h" |
| 120 | #include "ieee1394_types.h" |
| 121 | #include "hosts.h" |
| 122 | #include "dma.h" |
| 123 | #include "iso.h" |
| 124 | #include "ieee1394_core.h" |
| 125 | #include "highlevel.h" |
| 126 | #include "ohci1394.h" |
| 127 | |
| 128 | #ifdef CONFIG_IEEE1394_VERBOSEDEBUG |
| 129 | #define OHCI1394_DEBUG |
| 130 | #endif |
| 131 | |
| 132 | #ifdef DBGMSG |
| 133 | #undef DBGMSG |
| 134 | #endif |
| 135 | |
| 136 | #ifdef OHCI1394_DEBUG |
| 137 | #define DBGMSG(fmt, args...) \ |
| 138 | printk(KERN_INFO "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args) |
| 139 | #else |
| 140 | #define DBGMSG(fmt, args...) |
| 141 | #endif |
| 142 | |
| 143 | #ifdef CONFIG_IEEE1394_OHCI_DMA_DEBUG |
| 144 | #define OHCI_DMA_ALLOC(fmt, args...) \ |
| 145 | HPSB_ERR("%s(%s)alloc(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \ |
| 146 | ++global_outstanding_dmas, ## args) |
| 147 | #define OHCI_DMA_FREE(fmt, args...) \ |
| 148 | HPSB_ERR("%s(%s)free(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \ |
| 149 | --global_outstanding_dmas, ## args) |
| 150 | static int global_outstanding_dmas = 0; |
| 151 | #else |
| 152 | #define OHCI_DMA_ALLOC(fmt, args...) |
| 153 | #define OHCI_DMA_FREE(fmt, args...) |
| 154 | #endif |
| 155 | |
| 156 | /* print general (card independent) information */ |
| 157 | #define PRINT_G(level, fmt, args...) \ |
| 158 | printk(level "%s: " fmt "\n" , OHCI1394_DRIVER_NAME , ## args) |
| 159 | |
| 160 | /* print card specific information */ |
| 161 | #define PRINT(level, fmt, args...) \ |
| 162 | printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args) |
| 163 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | /* Module Parameters */ |
| 165 | static int phys_dma = 1; |
Ben Collins | fa9b739 | 2006-06-12 18:13:42 -0400 | [diff] [blame] | 166 | module_param(phys_dma, int, 0444); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | MODULE_PARM_DESC(phys_dma, "Enable physical dma (default = 1)."); |
| 168 | |
| 169 | static void dma_trm_tasklet(unsigned long data); |
| 170 | static void dma_trm_reset(struct dma_trm_ctx *d); |
| 171 | |
| 172 | static int alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d, |
| 173 | enum context_type type, int ctx, int num_desc, |
| 174 | int buf_size, int split_buf_size, int context_base); |
| 175 | static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d); |
| 176 | static void free_dma_rcv_ctx(struct dma_rcv_ctx *d); |
| 177 | |
| 178 | static int alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d, |
| 179 | enum context_type type, int ctx, int num_desc, |
| 180 | int context_base); |
| 181 | |
| 182 | static void ohci1394_pci_remove(struct pci_dev *pdev); |
| 183 | |
| 184 | #ifndef __LITTLE_ENDIAN |
| 185 | static unsigned hdr_sizes[] = |
| 186 | { |
| 187 | 3, /* TCODE_WRITEQ */ |
| 188 | 4, /* TCODE_WRITEB */ |
| 189 | 3, /* TCODE_WRITE_RESPONSE */ |
| 190 | 0, /* ??? */ |
| 191 | 3, /* TCODE_READQ */ |
| 192 | 4, /* TCODE_READB */ |
| 193 | 3, /* TCODE_READQ_RESPONSE */ |
| 194 | 4, /* TCODE_READB_RESPONSE */ |
| 195 | 1, /* TCODE_CYCLE_START (???) */ |
| 196 | 4, /* TCODE_LOCK_REQUEST */ |
| 197 | 2, /* TCODE_ISO_DATA */ |
| 198 | 4, /* TCODE_LOCK_RESPONSE */ |
| 199 | }; |
| 200 | |
| 201 | /* Swap headers */ |
| 202 | static inline void packet_swab(quadlet_t *data, int tcode) |
| 203 | { |
| 204 | size_t size = hdr_sizes[tcode]; |
| 205 | |
| 206 | if (tcode > TCODE_LOCK_RESPONSE || hdr_sizes[tcode] == 0) |
| 207 | return; |
| 208 | |
| 209 | while (size--) |
| 210 | data[size] = swab32(data[size]); |
| 211 | } |
| 212 | #else |
| 213 | /* Don't waste cycles on same sex byte swaps */ |
| 214 | #define packet_swab(w,x) |
| 215 | #endif /* !LITTLE_ENDIAN */ |
| 216 | |
| 217 | /*********************************** |
| 218 | * IEEE-1394 functionality section * |
| 219 | ***********************************/ |
| 220 | |
| 221 | static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr) |
| 222 | { |
| 223 | int i; |
| 224 | unsigned long flags; |
| 225 | quadlet_t r; |
| 226 | |
| 227 | spin_lock_irqsave (&ohci->phy_reg_lock, flags); |
| 228 | |
| 229 | reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000); |
| 230 | |
| 231 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { |
| 232 | if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000) |
| 233 | break; |
| 234 | |
| 235 | mdelay(1); |
| 236 | } |
| 237 | |
| 238 | r = reg_read(ohci, OHCI1394_PhyControl); |
| 239 | |
| 240 | if (i >= OHCI_LOOP_COUNT) |
| 241 | PRINT (KERN_ERR, "Get PHY Reg timeout [0x%08x/0x%08x/%d]", |
| 242 | r, r & 0x80000000, i); |
| 243 | |
| 244 | spin_unlock_irqrestore (&ohci->phy_reg_lock, flags); |
| 245 | |
| 246 | return (r & 0x00ff0000) >> 16; |
| 247 | } |
| 248 | |
| 249 | static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data) |
| 250 | { |
| 251 | int i; |
| 252 | unsigned long flags; |
| 253 | u32 r = 0; |
| 254 | |
| 255 | spin_lock_irqsave (&ohci->phy_reg_lock, flags); |
| 256 | |
| 257 | reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000); |
| 258 | |
| 259 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { |
| 260 | r = reg_read(ohci, OHCI1394_PhyControl); |
| 261 | if (!(r & 0x00004000)) |
| 262 | break; |
| 263 | |
| 264 | mdelay(1); |
| 265 | } |
| 266 | |
| 267 | if (i == OHCI_LOOP_COUNT) |
| 268 | PRINT (KERN_ERR, "Set PHY Reg timeout [0x%08x/0x%08x/%d]", |
| 269 | r, r & 0x00004000, i); |
| 270 | |
| 271 | spin_unlock_irqrestore (&ohci->phy_reg_lock, flags); |
| 272 | |
| 273 | return; |
| 274 | } |
| 275 | |
| 276 | /* Or's our value into the current value */ |
| 277 | static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data) |
| 278 | { |
| 279 | u8 old; |
| 280 | |
| 281 | old = get_phy_reg (ohci, addr); |
| 282 | old |= data; |
| 283 | set_phy_reg (ohci, addr, old); |
| 284 | |
| 285 | return; |
| 286 | } |
| 287 | |
| 288 | static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host, |
| 289 | int phyid, int isroot) |
| 290 | { |
| 291 | quadlet_t *q = ohci->selfid_buf_cpu; |
| 292 | quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount); |
| 293 | size_t size; |
| 294 | quadlet_t q0, q1; |
| 295 | |
| 296 | /* Check status of self-id reception */ |
| 297 | |
| 298 | if (ohci->selfid_swap) |
| 299 | q0 = le32_to_cpu(q[0]); |
| 300 | else |
| 301 | q0 = q[0]; |
| 302 | |
| 303 | if ((self_id_count & 0x80000000) || |
| 304 | ((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) { |
| 305 | PRINT(KERN_ERR, |
| 306 | "Error in reception of SelfID packets [0x%08x/0x%08x] (count: %d)", |
| 307 | self_id_count, q0, ohci->self_id_errors); |
| 308 | |
| 309 | /* Tip by James Goodwin <jamesg@Filanet.com>: |
| 310 | * We had an error, generate another bus reset in response. */ |
| 311 | if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) { |
| 312 | set_phy_reg_mask (ohci, 1, 0x40); |
| 313 | ohci->self_id_errors++; |
| 314 | } else { |
| 315 | PRINT(KERN_ERR, |
| 316 | "Too many errors on SelfID error reception, giving up!"); |
| 317 | } |
| 318 | return; |
| 319 | } |
| 320 | |
| 321 | /* SelfID Ok, reset error counter. */ |
| 322 | ohci->self_id_errors = 0; |
| 323 | |
| 324 | size = ((self_id_count & 0x00001FFC) >> 2) - 1; |
| 325 | q++; |
| 326 | |
| 327 | while (size > 0) { |
| 328 | if (ohci->selfid_swap) { |
| 329 | q0 = le32_to_cpu(q[0]); |
| 330 | q1 = le32_to_cpu(q[1]); |
| 331 | } else { |
| 332 | q0 = q[0]; |
| 333 | q1 = q[1]; |
| 334 | } |
| 335 | |
| 336 | if (q0 == ~q1) { |
| 337 | DBGMSG ("SelfID packet 0x%x received", q0); |
| 338 | hpsb_selfid_received(host, cpu_to_be32(q0)); |
| 339 | if (((q0 & 0x3f000000) >> 24) == phyid) |
| 340 | DBGMSG ("SelfID for this node is 0x%08x", q0); |
| 341 | } else { |
| 342 | PRINT(KERN_ERR, |
| 343 | "SelfID is inconsistent [0x%08x/0x%08x]", q0, q1); |
| 344 | } |
| 345 | q += 2; |
| 346 | size -= 2; |
| 347 | } |
| 348 | |
| 349 | DBGMSG("SelfID complete"); |
| 350 | |
| 351 | return; |
| 352 | } |
| 353 | |
| 354 | static void ohci_soft_reset(struct ti_ohci *ohci) { |
| 355 | int i; |
| 356 | |
| 357 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); |
| 358 | |
| 359 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { |
| 360 | if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset)) |
| 361 | break; |
| 362 | mdelay(1); |
| 363 | } |
| 364 | DBGMSG ("Soft reset finished"); |
| 365 | } |
| 366 | |
| 367 | |
| 368 | /* Generate the dma receive prgs and start the context */ |
| 369 | static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d, int generate_irq) |
| 370 | { |
| 371 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); |
| 372 | int i; |
| 373 | |
| 374 | ohci1394_stop_context(ohci, d->ctrlClear, NULL); |
| 375 | |
| 376 | for (i=0; i<d->num_desc; i++) { |
| 377 | u32 c; |
| 378 | |
| 379 | c = DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | DMA_CTL_BRANCH; |
| 380 | if (generate_irq) |
| 381 | c |= DMA_CTL_IRQ; |
| 382 | |
| 383 | d->prg_cpu[i]->control = cpu_to_le32(c | d->buf_size); |
| 384 | |
| 385 | /* End of descriptor list? */ |
| 386 | if (i + 1 < d->num_desc) { |
| 387 | d->prg_cpu[i]->branchAddress = |
| 388 | cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1); |
| 389 | } else { |
| 390 | d->prg_cpu[i]->branchAddress = |
| 391 | cpu_to_le32((d->prg_bus[0] & 0xfffffff0)); |
| 392 | } |
| 393 | |
| 394 | d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]); |
| 395 | d->prg_cpu[i]->status = cpu_to_le32(d->buf_size); |
| 396 | } |
| 397 | |
| 398 | d->buf_ind = 0; |
| 399 | d->buf_offset = 0; |
| 400 | |
| 401 | if (d->type == DMA_CTX_ISO) { |
| 402 | /* Clear contextControl */ |
| 403 | reg_write(ohci, d->ctrlClear, 0xffffffff); |
| 404 | |
| 405 | /* Set bufferFill, isochHeader, multichannel for IR context */ |
| 406 | reg_write(ohci, d->ctrlSet, 0xd0000000); |
| 407 | |
| 408 | /* Set the context match register to match on all tags */ |
| 409 | reg_write(ohci, d->ctxtMatch, 0xf0000000); |
| 410 | |
| 411 | /* Clear the multi channel mask high and low registers */ |
| 412 | reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff); |
| 413 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff); |
| 414 | |
| 415 | /* Set up isoRecvIntMask to generate interrupts */ |
| 416 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx); |
| 417 | } |
| 418 | |
| 419 | /* Tell the controller where the first AR program is */ |
| 420 | reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1); |
| 421 | |
| 422 | /* Run context */ |
| 423 | reg_write(ohci, d->ctrlSet, 0x00008000); |
| 424 | |
| 425 | DBGMSG("Receive DMA ctx=%d initialized", d->ctx); |
| 426 | } |
| 427 | |
| 428 | /* Initialize the dma transmit context */ |
| 429 | static void initialize_dma_trm_ctx(struct dma_trm_ctx *d) |
| 430 | { |
| 431 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); |
| 432 | |
| 433 | /* Stop the context */ |
| 434 | ohci1394_stop_context(ohci, d->ctrlClear, NULL); |
| 435 | |
| 436 | d->prg_ind = 0; |
| 437 | d->sent_ind = 0; |
| 438 | d->free_prgs = d->num_desc; |
| 439 | d->branchAddrPtr = NULL; |
| 440 | INIT_LIST_HEAD(&d->fifo_list); |
| 441 | INIT_LIST_HEAD(&d->pending_list); |
| 442 | |
| 443 | if (d->type == DMA_CTX_ISO) { |
| 444 | /* enable interrupts */ |
| 445 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx); |
| 446 | } |
| 447 | |
| 448 | DBGMSG("Transmit DMA ctx=%d initialized", d->ctx); |
| 449 | } |
| 450 | |
| 451 | /* Count the number of available iso contexts */ |
| 452 | static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg) |
| 453 | { |
| 454 | int i,ctx=0; |
| 455 | u32 tmp; |
| 456 | |
| 457 | reg_write(ohci, reg, 0xffffffff); |
| 458 | tmp = reg_read(ohci, reg); |
| 459 | |
| 460 | DBGMSG("Iso contexts reg: %08x implemented: %08x", reg, tmp); |
| 461 | |
| 462 | /* Count the number of contexts */ |
| 463 | for (i=0; i<32; i++) { |
| 464 | if (tmp & 1) ctx++; |
| 465 | tmp >>= 1; |
| 466 | } |
| 467 | return ctx; |
| 468 | } |
| 469 | |
| 470 | /* Global initialization */ |
| 471 | static void ohci_initialize(struct ti_ohci *ohci) |
| 472 | { |
| 473 | char irq_buf[16]; |
| 474 | quadlet_t buf; |
| 475 | int num_ports, i; |
| 476 | |
| 477 | spin_lock_init(&ohci->phy_reg_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 478 | |
| 479 | /* Put some defaults to these undefined bus options */ |
| 480 | buf = reg_read(ohci, OHCI1394_BusOptions); |
| 481 | buf |= 0x60000000; /* Enable CMC and ISC */ |
Ben Collins | 1934b8b | 2005-07-09 20:01:23 -0400 | [diff] [blame] | 482 | if (hpsb_disable_irm) |
| 483 | buf &= ~0x80000000; |
| 484 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | buf |= 0x80000000; /* Enable IRMC */ |
| 486 | buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */ |
| 487 | buf &= ~0x18000000; /* Disable PMC and BMC */ |
| 488 | reg_write(ohci, OHCI1394_BusOptions, buf); |
| 489 | |
| 490 | /* Set the bus number */ |
| 491 | reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); |
| 492 | |
| 493 | /* Enable posted writes */ |
| 494 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable); |
| 495 | |
| 496 | /* Clear link control register */ |
| 497 | reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); |
| 498 | |
| 499 | /* Enable cycle timer and cycle master and set the IRM |
| 500 | * contender bit in our self ID packets if appropriate. */ |
| 501 | reg_write(ohci, OHCI1394_LinkControlSet, |
| 502 | OHCI1394_LinkControl_CycleTimerEnable | |
| 503 | OHCI1394_LinkControl_CycleMaster); |
Ben Collins | 1934b8b | 2005-07-09 20:01:23 -0400 | [diff] [blame] | 504 | i = get_phy_reg(ohci, 4) | PHY_04_LCTRL; |
| 505 | if (hpsb_disable_irm) |
| 506 | i &= ~PHY_04_CONTENDER; |
| 507 | else |
| 508 | i |= PHY_04_CONTENDER; |
| 509 | set_phy_reg(ohci, 4, i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 510 | |
| 511 | /* Set up self-id dma buffer */ |
| 512 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus); |
| 513 | |
| 514 | /* enable self-id and phys */ |
| 515 | reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID | |
| 516 | OHCI1394_LinkControl_RcvPhyPkt); |
| 517 | |
| 518 | /* Set the Config ROM mapping register */ |
| 519 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus); |
| 520 | |
| 521 | /* Now get our max packet size */ |
| 522 | ohci->max_packet_size = |
| 523 | 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1); |
| 524 | |
| 525 | /* Don't accept phy packets into AR request context */ |
| 526 | reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400); |
| 527 | |
| 528 | /* Clear the interrupt mask */ |
| 529 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff); |
| 530 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff); |
| 531 | |
| 532 | /* Clear the interrupt mask */ |
| 533 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff); |
| 534 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff); |
| 535 | |
| 536 | /* Initialize AR dma */ |
| 537 | initialize_dma_rcv_ctx(&ohci->ar_req_context, 0); |
| 538 | initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0); |
| 539 | |
| 540 | /* Initialize AT dma */ |
| 541 | initialize_dma_trm_ctx(&ohci->at_req_context); |
| 542 | initialize_dma_trm_ctx(&ohci->at_resp_context); |
| 543 | |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 544 | /* Initialize IR Legacy DMA channel mask */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | ohci->ir_legacy_channels = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 546 | |
Stefan Richter | 180a430 | 2006-03-28 19:57:34 -0500 | [diff] [blame] | 547 | /* Accept AR requests from all nodes */ |
| 548 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); |
| 549 | |
| 550 | /* Set the address range of the physical response unit. |
| 551 | * Most controllers do not implement it as a writable register though. |
| 552 | * They will keep a hardwired offset of 0x00010000 and show 0x0 as |
| 553 | * register content. |
| 554 | * To actually enable physical responses is the job of our interrupt |
| 555 | * handler which programs the physical request filter. */ |
Ben Collins | 4611ed3 | 2006-06-12 18:13:32 -0400 | [diff] [blame] | 556 | reg_write(ohci, OHCI1394_PhyUpperBound, |
| 557 | OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED >> 16); |
Stefan Richter | 180a430 | 2006-03-28 19:57:34 -0500 | [diff] [blame] | 558 | |
| 559 | DBGMSG("physUpperBoundOffset=%08x", |
| 560 | reg_read(ohci, OHCI1394_PhyUpperBound)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 561 | |
| 562 | /* Specify AT retries */ |
| 563 | reg_write(ohci, OHCI1394_ATRetries, |
| 564 | OHCI1394_MAX_AT_REQ_RETRIES | |
| 565 | (OHCI1394_MAX_AT_RESP_RETRIES<<4) | |
| 566 | (OHCI1394_MAX_PHYS_RESP_RETRIES<<8)); |
| 567 | |
| 568 | /* We don't want hardware swapping */ |
| 569 | reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap); |
| 570 | |
| 571 | /* Enable interrupts */ |
| 572 | reg_write(ohci, OHCI1394_IntMaskSet, |
| 573 | OHCI1394_unrecoverableError | |
| 574 | OHCI1394_masterIntEnable | |
| 575 | OHCI1394_busReset | |
| 576 | OHCI1394_selfIDComplete | |
| 577 | OHCI1394_RSPkt | |
| 578 | OHCI1394_RQPkt | |
| 579 | OHCI1394_respTxComplete | |
| 580 | OHCI1394_reqTxComplete | |
| 581 | OHCI1394_isochRx | |
| 582 | OHCI1394_isochTx | |
Jody McIntyre | e2f8165 | 2006-03-28 19:55:11 -0500 | [diff] [blame] | 583 | OHCI1394_postedWriteErr | |
Ben Collins | 57fdb58 | 2006-06-12 18:12:21 -0400 | [diff] [blame] | 584 | OHCI1394_cycleTooLong | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 585 | OHCI1394_cycleInconsistent); |
| 586 | |
| 587 | /* Enable link */ |
| 588 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable); |
| 589 | |
| 590 | buf = reg_read(ohci, OHCI1394_Version); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | sprintf (irq_buf, "%d", ohci->dev->irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%s] " |
Greg Kroah-Hartman | e29419f | 2006-06-12 15:20:16 -0700 | [diff] [blame] | 593 | "MMIO=[%llx-%llx] Max Packet=[%d] IR/IT contexts=[%d/%d]", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10), |
| 595 | ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), irq_buf, |
Greg Kroah-Hartman | e29419f | 2006-06-12 15:20:16 -0700 | [diff] [blame] | 596 | (unsigned long long)pci_resource_start(ohci->dev, 0), |
| 597 | (unsigned long long)pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1, |
Stefan Richter | 209171a | 2005-12-13 11:05:00 -0500 | [diff] [blame] | 598 | ohci->max_packet_size, |
| 599 | ohci->nb_iso_rcv_ctx, ohci->nb_iso_xmit_ctx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 600 | |
| 601 | /* Check all of our ports to make sure that if anything is |
| 602 | * connected, we enable that port. */ |
| 603 | num_ports = get_phy_reg(ohci, 2) & 0xf; |
| 604 | for (i = 0; i < num_ports; i++) { |
| 605 | unsigned int status; |
| 606 | |
| 607 | set_phy_reg(ohci, 7, i); |
| 608 | status = get_phy_reg(ohci, 8); |
| 609 | |
| 610 | if (status & 0x20) |
| 611 | set_phy_reg(ohci, 8, status & ~1); |
| 612 | } |
| 613 | |
| 614 | /* Serial EEPROM Sanity check. */ |
| 615 | if ((ohci->max_packet_size < 512) || |
| 616 | (ohci->max_packet_size > 4096)) { |
| 617 | /* Serial EEPROM contents are suspect, set a sane max packet |
| 618 | * size and print the raw contents for bug reports if verbose |
| 619 | * debug is enabled. */ |
| 620 | #ifdef CONFIG_IEEE1394_VERBOSEDEBUG |
| 621 | int i; |
| 622 | #endif |
| 623 | |
| 624 | PRINT(KERN_DEBUG, "Serial EEPROM has suspicious values, " |
| 625 | "attempting to setting max_packet_size to 512 bytes"); |
| 626 | reg_write(ohci, OHCI1394_BusOptions, |
| 627 | (reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002); |
| 628 | ohci->max_packet_size = 512; |
| 629 | #ifdef CONFIG_IEEE1394_VERBOSEDEBUG |
| 630 | PRINT(KERN_DEBUG, " EEPROM Present: %d", |
| 631 | (reg_read(ohci, OHCI1394_Version) >> 24) & 0x1); |
| 632 | reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000); |
| 633 | |
| 634 | for (i = 0; |
| 635 | ((i < 1000) && |
| 636 | (reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++) |
| 637 | udelay(10); |
| 638 | |
| 639 | for (i = 0; i < 0x20; i++) { |
| 640 | reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000); |
| 641 | PRINT(KERN_DEBUG, " EEPROM %02x: %02x", i, |
| 642 | (reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff); |
| 643 | } |
| 644 | #endif |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | /* |
| 649 | * Insert a packet in the DMA fifo and generate the DMA prg |
| 650 | * FIXME: rewrite the program in order to accept packets crossing |
| 651 | * page boundaries. |
| 652 | * check also that a single dma descriptor doesn't cross a |
| 653 | * page boundary. |
| 654 | */ |
| 655 | static void insert_packet(struct ti_ohci *ohci, |
| 656 | struct dma_trm_ctx *d, struct hpsb_packet *packet) |
| 657 | { |
| 658 | u32 cycleTimer; |
| 659 | int idx = d->prg_ind; |
| 660 | |
| 661 | DBGMSG("Inserting packet for node " NODE_BUS_FMT |
| 662 | ", tlabel=%d, tcode=0x%x, speed=%d", |
| 663 | NODE_BUS_ARGS(ohci->host, packet->node_id), packet->tlabel, |
| 664 | packet->tcode, packet->speed_code); |
| 665 | |
| 666 | d->prg_cpu[idx]->begin.address = 0; |
| 667 | d->prg_cpu[idx]->begin.branchAddress = 0; |
| 668 | |
| 669 | if (d->type == DMA_CTX_ASYNC_RESP) { |
| 670 | /* |
| 671 | * For response packets, we need to put a timeout value in |
| 672 | * the 16 lower bits of the status... let's try 1 sec timeout |
| 673 | */ |
| 674 | cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer); |
| 675 | d->prg_cpu[idx]->begin.status = cpu_to_le32( |
| 676 | (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) | |
| 677 | ((cycleTimer&0x01fff000)>>12)); |
| 678 | |
| 679 | DBGMSG("cycleTimer: %08x timeStamp: %08x", |
| 680 | cycleTimer, d->prg_cpu[idx]->begin.status); |
| 681 | } else |
| 682 | d->prg_cpu[idx]->begin.status = 0; |
| 683 | |
| 684 | if ( (packet->type == hpsb_async) || (packet->type == hpsb_raw) ) { |
| 685 | |
| 686 | if (packet->type == hpsb_raw) { |
| 687 | d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4); |
| 688 | d->prg_cpu[idx]->data[1] = cpu_to_le32(packet->header[0]); |
| 689 | d->prg_cpu[idx]->data[2] = cpu_to_le32(packet->header[1]); |
| 690 | } else { |
| 691 | d->prg_cpu[idx]->data[0] = packet->speed_code<<16 | |
| 692 | (packet->header[0] & 0xFFFF); |
| 693 | |
| 694 | if (packet->tcode == TCODE_ISO_DATA) { |
| 695 | /* Sending an async stream packet */ |
| 696 | d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000; |
| 697 | } else { |
| 698 | /* Sending a normal async request or response */ |
| 699 | d->prg_cpu[idx]->data[1] = |
| 700 | (packet->header[1] & 0xFFFF) | |
| 701 | (packet->header[0] & 0xFFFF0000); |
| 702 | d->prg_cpu[idx]->data[2] = packet->header[2]; |
| 703 | d->prg_cpu[idx]->data[3] = packet->header[3]; |
| 704 | } |
| 705 | packet_swab(d->prg_cpu[idx]->data, packet->tcode); |
| 706 | } |
| 707 | |
| 708 | if (packet->data_size) { /* block transmit */ |
| 709 | if (packet->tcode == TCODE_STREAM_DATA){ |
| 710 | d->prg_cpu[idx]->begin.control = |
| 711 | cpu_to_le32(DMA_CTL_OUTPUT_MORE | |
| 712 | DMA_CTL_IMMEDIATE | 0x8); |
| 713 | } else { |
| 714 | d->prg_cpu[idx]->begin.control = |
| 715 | cpu_to_le32(DMA_CTL_OUTPUT_MORE | |
| 716 | DMA_CTL_IMMEDIATE | 0x10); |
| 717 | } |
| 718 | d->prg_cpu[idx]->end.control = |
| 719 | cpu_to_le32(DMA_CTL_OUTPUT_LAST | |
| 720 | DMA_CTL_IRQ | |
| 721 | DMA_CTL_BRANCH | |
| 722 | packet->data_size); |
| 723 | /* |
| 724 | * Check that the packet data buffer |
| 725 | * does not cross a page boundary. |
| 726 | * |
| 727 | * XXX Fix this some day. eth1394 seems to trigger |
| 728 | * it, but ignoring it doesn't seem to cause a |
| 729 | * problem. |
| 730 | */ |
| 731 | #if 0 |
| 732 | if (cross_bound((unsigned long)packet->data, |
| 733 | packet->data_size)>0) { |
| 734 | /* FIXME: do something about it */ |
| 735 | PRINT(KERN_ERR, |
| 736 | "%s: packet data addr: %p size %Zd bytes " |
| 737 | "cross page boundary", __FUNCTION__, |
| 738 | packet->data, packet->data_size); |
| 739 | } |
| 740 | #endif |
| 741 | d->prg_cpu[idx]->end.address = cpu_to_le32( |
| 742 | pci_map_single(ohci->dev, packet->data, |
| 743 | packet->data_size, |
| 744 | PCI_DMA_TODEVICE)); |
| 745 | OHCI_DMA_ALLOC("single, block transmit packet"); |
| 746 | |
| 747 | d->prg_cpu[idx]->end.branchAddress = 0; |
| 748 | d->prg_cpu[idx]->end.status = 0; |
| 749 | if (d->branchAddrPtr) |
| 750 | *(d->branchAddrPtr) = |
| 751 | cpu_to_le32(d->prg_bus[idx] | 0x3); |
| 752 | d->branchAddrPtr = |
| 753 | &(d->prg_cpu[idx]->end.branchAddress); |
| 754 | } else { /* quadlet transmit */ |
| 755 | if (packet->type == hpsb_raw) |
| 756 | d->prg_cpu[idx]->begin.control = |
| 757 | cpu_to_le32(DMA_CTL_OUTPUT_LAST | |
| 758 | DMA_CTL_IMMEDIATE | |
| 759 | DMA_CTL_IRQ | |
| 760 | DMA_CTL_BRANCH | |
| 761 | (packet->header_size + 4)); |
| 762 | else |
| 763 | d->prg_cpu[idx]->begin.control = |
| 764 | cpu_to_le32(DMA_CTL_OUTPUT_LAST | |
| 765 | DMA_CTL_IMMEDIATE | |
| 766 | DMA_CTL_IRQ | |
| 767 | DMA_CTL_BRANCH | |
| 768 | packet->header_size); |
| 769 | |
| 770 | if (d->branchAddrPtr) |
| 771 | *(d->branchAddrPtr) = |
| 772 | cpu_to_le32(d->prg_bus[idx] | 0x2); |
| 773 | d->branchAddrPtr = |
| 774 | &(d->prg_cpu[idx]->begin.branchAddress); |
| 775 | } |
| 776 | |
| 777 | } else { /* iso packet */ |
| 778 | d->prg_cpu[idx]->data[0] = packet->speed_code<<16 | |
| 779 | (packet->header[0] & 0xFFFF); |
| 780 | d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000; |
| 781 | packet_swab(d->prg_cpu[idx]->data, packet->tcode); |
| 782 | |
| 783 | d->prg_cpu[idx]->begin.control = |
| 784 | cpu_to_le32(DMA_CTL_OUTPUT_MORE | |
| 785 | DMA_CTL_IMMEDIATE | 0x8); |
| 786 | d->prg_cpu[idx]->end.control = |
| 787 | cpu_to_le32(DMA_CTL_OUTPUT_LAST | |
| 788 | DMA_CTL_UPDATE | |
| 789 | DMA_CTL_IRQ | |
| 790 | DMA_CTL_BRANCH | |
| 791 | packet->data_size); |
| 792 | d->prg_cpu[idx]->end.address = cpu_to_le32( |
| 793 | pci_map_single(ohci->dev, packet->data, |
| 794 | packet->data_size, PCI_DMA_TODEVICE)); |
| 795 | OHCI_DMA_ALLOC("single, iso transmit packet"); |
| 796 | |
| 797 | d->prg_cpu[idx]->end.branchAddress = 0; |
| 798 | d->prg_cpu[idx]->end.status = 0; |
| 799 | DBGMSG("Iso xmit context info: header[%08x %08x]\n" |
| 800 | " begin=%08x %08x %08x %08x\n" |
| 801 | " %08x %08x %08x %08x\n" |
| 802 | " end =%08x %08x %08x %08x", |
| 803 | d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1], |
| 804 | d->prg_cpu[idx]->begin.control, |
| 805 | d->prg_cpu[idx]->begin.address, |
| 806 | d->prg_cpu[idx]->begin.branchAddress, |
| 807 | d->prg_cpu[idx]->begin.status, |
| 808 | d->prg_cpu[idx]->data[0], |
| 809 | d->prg_cpu[idx]->data[1], |
| 810 | d->prg_cpu[idx]->data[2], |
| 811 | d->prg_cpu[idx]->data[3], |
| 812 | d->prg_cpu[idx]->end.control, |
| 813 | d->prg_cpu[idx]->end.address, |
| 814 | d->prg_cpu[idx]->end.branchAddress, |
| 815 | d->prg_cpu[idx]->end.status); |
| 816 | if (d->branchAddrPtr) |
| 817 | *(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3); |
| 818 | d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress); |
| 819 | } |
| 820 | d->free_prgs--; |
| 821 | |
| 822 | /* queue the packet in the appropriate context queue */ |
| 823 | list_add_tail(&packet->driver_list, &d->fifo_list); |
| 824 | d->prg_ind = (d->prg_ind + 1) % d->num_desc; |
| 825 | } |
| 826 | |
| 827 | /* |
| 828 | * This function fills the FIFO with the (eventual) pending packets |
| 829 | * and runs or wakes up the DMA prg if necessary. |
| 830 | * |
| 831 | * The function MUST be called with the d->lock held. |
| 832 | */ |
| 833 | static void dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d) |
| 834 | { |
| 835 | struct hpsb_packet *packet, *ptmp; |
| 836 | int idx = d->prg_ind; |
| 837 | int z = 0; |
| 838 | |
| 839 | /* insert the packets into the dma fifo */ |
| 840 | list_for_each_entry_safe(packet, ptmp, &d->pending_list, driver_list) { |
| 841 | if (!d->free_prgs) |
| 842 | break; |
| 843 | |
| 844 | /* For the first packet only */ |
| 845 | if (!z) |
| 846 | z = (packet->data_size) ? 3 : 2; |
| 847 | |
| 848 | /* Insert the packet */ |
| 849 | list_del_init(&packet->driver_list); |
| 850 | insert_packet(ohci, d, packet); |
| 851 | } |
| 852 | |
| 853 | /* Nothing must have been done, either no free_prgs or no packets */ |
| 854 | if (z == 0) |
| 855 | return; |
| 856 | |
| 857 | /* Is the context running ? (should be unless it is |
| 858 | the first packet to be sent in this context) */ |
| 859 | if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) { |
| 860 | u32 nodeId = reg_read(ohci, OHCI1394_NodeID); |
| 861 | |
| 862 | DBGMSG("Starting transmit DMA ctx=%d",d->ctx); |
| 863 | reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z); |
| 864 | |
| 865 | /* Check that the node id is valid, and not 63 */ |
| 866 | if (!(nodeId & 0x80000000) || (nodeId & 0x3f) == 63) |
| 867 | PRINT(KERN_ERR, "Running dma failed because Node ID is not valid"); |
| 868 | else |
| 869 | reg_write(ohci, d->ctrlSet, 0x8000); |
| 870 | } else { |
| 871 | /* Wake up the dma context if necessary */ |
| 872 | if (!(reg_read(ohci, d->ctrlSet) & 0x400)) |
| 873 | DBGMSG("Waking transmit DMA ctx=%d",d->ctx); |
| 874 | |
| 875 | /* do this always, to avoid race condition */ |
| 876 | reg_write(ohci, d->ctrlSet, 0x1000); |
| 877 | } |
| 878 | |
| 879 | return; |
| 880 | } |
| 881 | |
| 882 | /* Transmission of an async or iso packet */ |
| 883 | static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet) |
| 884 | { |
| 885 | struct ti_ohci *ohci = host->hostdata; |
| 886 | struct dma_trm_ctx *d; |
| 887 | unsigned long flags; |
| 888 | |
| 889 | if (packet->data_size > ohci->max_packet_size) { |
| 890 | PRINT(KERN_ERR, |
| 891 | "Transmit packet size %Zd is too big", |
| 892 | packet->data_size); |
| 893 | return -EOVERFLOW; |
| 894 | } |
| 895 | |
| 896 | /* Decide whether we have an iso, a request, or a response packet */ |
| 897 | if (packet->type == hpsb_raw) |
| 898 | d = &ohci->at_req_context; |
| 899 | else if ((packet->tcode == TCODE_ISO_DATA) && (packet->type == hpsb_iso)) { |
| 900 | /* The legacy IT DMA context is initialized on first |
| 901 | * use. However, the alloc cannot be run from |
| 902 | * interrupt context, so we bail out if that is the |
| 903 | * case. I don't see anyone sending ISO packets from |
| 904 | * interrupt context anyway... */ |
| 905 | |
| 906 | if (ohci->it_legacy_context.ohci == NULL) { |
| 907 | if (in_interrupt()) { |
| 908 | PRINT(KERN_ERR, |
| 909 | "legacy IT context cannot be initialized during interrupt"); |
| 910 | return -EINVAL; |
| 911 | } |
| 912 | |
| 913 | if (alloc_dma_trm_ctx(ohci, &ohci->it_legacy_context, |
| 914 | DMA_CTX_ISO, 0, IT_NUM_DESC, |
| 915 | OHCI1394_IsoXmitContextBase) < 0) { |
| 916 | PRINT(KERN_ERR, |
| 917 | "error initializing legacy IT context"); |
| 918 | return -ENOMEM; |
| 919 | } |
| 920 | |
| 921 | initialize_dma_trm_ctx(&ohci->it_legacy_context); |
| 922 | } |
| 923 | |
| 924 | d = &ohci->it_legacy_context; |
| 925 | } else if ((packet->tcode & 0x02) && (packet->tcode != TCODE_ISO_DATA)) |
| 926 | d = &ohci->at_resp_context; |
| 927 | else |
| 928 | d = &ohci->at_req_context; |
| 929 | |
| 930 | spin_lock_irqsave(&d->lock,flags); |
| 931 | |
| 932 | list_add_tail(&packet->driver_list, &d->pending_list); |
| 933 | |
| 934 | dma_trm_flush(ohci, d); |
| 935 | |
| 936 | spin_unlock_irqrestore(&d->lock,flags); |
| 937 | |
| 938 | return 0; |
| 939 | } |
| 940 | |
| 941 | static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg) |
| 942 | { |
| 943 | struct ti_ohci *ohci = host->hostdata; |
| 944 | int retval = 0; |
| 945 | unsigned long flags; |
| 946 | int phy_reg; |
| 947 | |
| 948 | switch (cmd) { |
| 949 | case RESET_BUS: |
| 950 | switch (arg) { |
| 951 | case SHORT_RESET: |
| 952 | phy_reg = get_phy_reg(ohci, 5); |
| 953 | phy_reg |= 0x40; |
| 954 | set_phy_reg(ohci, 5, phy_reg); /* set ISBR */ |
| 955 | break; |
| 956 | case LONG_RESET: |
| 957 | phy_reg = get_phy_reg(ohci, 1); |
| 958 | phy_reg |= 0x40; |
| 959 | set_phy_reg(ohci, 1, phy_reg); /* set IBR */ |
| 960 | break; |
| 961 | case SHORT_RESET_NO_FORCE_ROOT: |
| 962 | phy_reg = get_phy_reg(ohci, 1); |
| 963 | if (phy_reg & 0x80) { |
| 964 | phy_reg &= ~0x80; |
| 965 | set_phy_reg(ohci, 1, phy_reg); /* clear RHB */ |
| 966 | } |
| 967 | |
| 968 | phy_reg = get_phy_reg(ohci, 5); |
| 969 | phy_reg |= 0x40; |
| 970 | set_phy_reg(ohci, 5, phy_reg); /* set ISBR */ |
| 971 | break; |
| 972 | case LONG_RESET_NO_FORCE_ROOT: |
| 973 | phy_reg = get_phy_reg(ohci, 1); |
| 974 | phy_reg &= ~0x80; |
| 975 | phy_reg |= 0x40; |
| 976 | set_phy_reg(ohci, 1, phy_reg); /* clear RHB, set IBR */ |
| 977 | break; |
| 978 | case SHORT_RESET_FORCE_ROOT: |
| 979 | phy_reg = get_phy_reg(ohci, 1); |
| 980 | if (!(phy_reg & 0x80)) { |
| 981 | phy_reg |= 0x80; |
| 982 | set_phy_reg(ohci, 1, phy_reg); /* set RHB */ |
| 983 | } |
| 984 | |
| 985 | phy_reg = get_phy_reg(ohci, 5); |
| 986 | phy_reg |= 0x40; |
| 987 | set_phy_reg(ohci, 5, phy_reg); /* set ISBR */ |
| 988 | break; |
| 989 | case LONG_RESET_FORCE_ROOT: |
| 990 | phy_reg = get_phy_reg(ohci, 1); |
| 991 | phy_reg |= 0xc0; |
| 992 | set_phy_reg(ohci, 1, phy_reg); /* set RHB and IBR */ |
| 993 | break; |
| 994 | default: |
| 995 | retval = -1; |
| 996 | } |
| 997 | break; |
| 998 | |
| 999 | case GET_CYCLE_COUNTER: |
| 1000 | retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer); |
| 1001 | break; |
| 1002 | |
| 1003 | case SET_CYCLE_COUNTER: |
| 1004 | reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg); |
| 1005 | break; |
| 1006 | |
| 1007 | case SET_BUS_ID: |
| 1008 | PRINT(KERN_ERR, "devctl command SET_BUS_ID err"); |
| 1009 | break; |
| 1010 | |
| 1011 | case ACT_CYCLE_MASTER: |
| 1012 | if (arg) { |
| 1013 | /* check if we are root and other nodes are present */ |
| 1014 | u32 nodeId = reg_read(ohci, OHCI1394_NodeID); |
| 1015 | if ((nodeId & (1<<30)) && (nodeId & 0x3f)) { |
| 1016 | /* |
| 1017 | * enable cycleTimer, cycleMaster |
| 1018 | */ |
| 1019 | DBGMSG("Cycle master enabled"); |
| 1020 | reg_write(ohci, OHCI1394_LinkControlSet, |
| 1021 | OHCI1394_LinkControl_CycleTimerEnable | |
| 1022 | OHCI1394_LinkControl_CycleMaster); |
| 1023 | } |
| 1024 | } else { |
| 1025 | /* disable cycleTimer, cycleMaster, cycleSource */ |
| 1026 | reg_write(ohci, OHCI1394_LinkControlClear, |
| 1027 | OHCI1394_LinkControl_CycleTimerEnable | |
| 1028 | OHCI1394_LinkControl_CycleMaster | |
| 1029 | OHCI1394_LinkControl_CycleSource); |
| 1030 | } |
| 1031 | break; |
| 1032 | |
| 1033 | case CANCEL_REQUESTS: |
| 1034 | DBGMSG("Cancel request received"); |
| 1035 | dma_trm_reset(&ohci->at_req_context); |
| 1036 | dma_trm_reset(&ohci->at_resp_context); |
| 1037 | break; |
| 1038 | |
| 1039 | case ISO_LISTEN_CHANNEL: |
| 1040 | { |
| 1041 | u64 mask; |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1042 | struct dma_rcv_ctx *d = &ohci->ir_legacy_context; |
| 1043 | int ir_legacy_active; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1044 | |
| 1045 | if (arg<0 || arg>63) { |
| 1046 | PRINT(KERN_ERR, |
| 1047 | "%s: IS0 listen channel %d is out of range", |
| 1048 | __FUNCTION__, arg); |
| 1049 | return -EFAULT; |
| 1050 | } |
| 1051 | |
| 1052 | mask = (u64)0x1<<arg; |
| 1053 | |
| 1054 | spin_lock_irqsave(&ohci->IR_channel_lock, flags); |
| 1055 | |
| 1056 | if (ohci->ISO_channel_usage & mask) { |
| 1057 | PRINT(KERN_ERR, |
| 1058 | "%s: IS0 listen channel %d is already used", |
| 1059 | __FUNCTION__, arg); |
| 1060 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); |
| 1061 | return -EFAULT; |
| 1062 | } |
| 1063 | |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1064 | ir_legacy_active = ohci->ir_legacy_channels; |
| 1065 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1066 | ohci->ISO_channel_usage |= mask; |
| 1067 | ohci->ir_legacy_channels |= mask; |
| 1068 | |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1069 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); |
| 1070 | |
| 1071 | if (!ir_legacy_active) { |
| 1072 | if (ohci1394_register_iso_tasklet(ohci, |
| 1073 | &ohci->ir_legacy_tasklet) < 0) { |
| 1074 | PRINT(KERN_ERR, "No IR DMA context available"); |
| 1075 | return -EBUSY; |
| 1076 | } |
| 1077 | |
| 1078 | /* the IR context can be assigned to any DMA context |
| 1079 | * by ohci1394_register_iso_tasklet */ |
| 1080 | d->ctx = ohci->ir_legacy_tasklet.context; |
| 1081 | d->ctrlSet = OHCI1394_IsoRcvContextControlSet + |
| 1082 | 32*d->ctx; |
| 1083 | d->ctrlClear = OHCI1394_IsoRcvContextControlClear + |
| 1084 | 32*d->ctx; |
| 1085 | d->cmdPtr = OHCI1394_IsoRcvCommandPtr + 32*d->ctx; |
| 1086 | d->ctxtMatch = OHCI1394_IsoRcvContextMatch + 32*d->ctx; |
| 1087 | |
| 1088 | initialize_dma_rcv_ctx(&ohci->ir_legacy_context, 1); |
| 1089 | |
Olaf Hering | 98848fa | 2005-07-14 00:33:45 -0700 | [diff] [blame] | 1090 | if (printk_ratelimit()) |
Jody McIntyre | 32e7a04 | 2005-09-30 11:59:19 -0700 | [diff] [blame] | 1091 | DBGMSG("IR legacy activated"); |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1092 | } |
| 1093 | |
| 1094 | spin_lock_irqsave(&ohci->IR_channel_lock, flags); |
| 1095 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1096 | if (arg>31) |
| 1097 | reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, |
| 1098 | 1<<(arg-32)); |
| 1099 | else |
| 1100 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, |
| 1101 | 1<<arg); |
| 1102 | |
| 1103 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); |
| 1104 | DBGMSG("Listening enabled on channel %d", arg); |
| 1105 | break; |
| 1106 | } |
| 1107 | case ISO_UNLISTEN_CHANNEL: |
| 1108 | { |
| 1109 | u64 mask; |
| 1110 | |
| 1111 | if (arg<0 || arg>63) { |
| 1112 | PRINT(KERN_ERR, |
| 1113 | "%s: IS0 unlisten channel %d is out of range", |
| 1114 | __FUNCTION__, arg); |
| 1115 | return -EFAULT; |
| 1116 | } |
| 1117 | |
| 1118 | mask = (u64)0x1<<arg; |
| 1119 | |
| 1120 | spin_lock_irqsave(&ohci->IR_channel_lock, flags); |
| 1121 | |
| 1122 | if (!(ohci->ISO_channel_usage & mask)) { |
| 1123 | PRINT(KERN_ERR, |
| 1124 | "%s: IS0 unlisten channel %d is not used", |
| 1125 | __FUNCTION__, arg); |
| 1126 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); |
| 1127 | return -EFAULT; |
| 1128 | } |
| 1129 | |
| 1130 | ohci->ISO_channel_usage &= ~mask; |
| 1131 | ohci->ir_legacy_channels &= ~mask; |
| 1132 | |
| 1133 | if (arg>31) |
| 1134 | reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, |
| 1135 | 1<<(arg-32)); |
| 1136 | else |
| 1137 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, |
| 1138 | 1<<arg); |
| 1139 | |
| 1140 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); |
| 1141 | DBGMSG("Listening disabled on channel %d", arg); |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1142 | |
| 1143 | if (ohci->ir_legacy_channels == 0) { |
| 1144 | stop_dma_rcv_ctx(&ohci->ir_legacy_context); |
| 1145 | DBGMSG("ISO legacy receive context stopped"); |
| 1146 | } |
| 1147 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1148 | break; |
| 1149 | } |
| 1150 | default: |
| 1151 | PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet", |
| 1152 | cmd); |
| 1153 | break; |
| 1154 | } |
| 1155 | return retval; |
| 1156 | } |
| 1157 | |
| 1158 | /*********************************** |
| 1159 | * rawiso ISO reception * |
| 1160 | ***********************************/ |
| 1161 | |
| 1162 | /* |
| 1163 | We use either buffer-fill or packet-per-buffer DMA mode. The DMA |
| 1164 | buffer is split into "blocks" (regions described by one DMA |
| 1165 | descriptor). Each block must be one page or less in size, and |
| 1166 | must not cross a page boundary. |
| 1167 | |
| 1168 | There is one little wrinkle with buffer-fill mode: a packet that |
| 1169 | starts in the final block may wrap around into the first block. But |
| 1170 | the user API expects all packets to be contiguous. Our solution is |
| 1171 | to keep the very last page of the DMA buffer in reserve - if a |
| 1172 | packet spans the gap, we copy its tail into this page. |
| 1173 | */ |
| 1174 | |
| 1175 | struct ohci_iso_recv { |
| 1176 | struct ti_ohci *ohci; |
| 1177 | |
| 1178 | struct ohci1394_iso_tasklet task; |
| 1179 | int task_active; |
| 1180 | |
| 1181 | enum { BUFFER_FILL_MODE = 0, |
| 1182 | PACKET_PER_BUFFER_MODE = 1 } dma_mode; |
| 1183 | |
| 1184 | /* memory and PCI mapping for the DMA descriptors */ |
| 1185 | struct dma_prog_region prog; |
| 1186 | struct dma_cmd *block; /* = (struct dma_cmd*) prog.virt */ |
| 1187 | |
| 1188 | /* how many DMA blocks fit in the buffer */ |
| 1189 | unsigned int nblocks; |
| 1190 | |
| 1191 | /* stride of DMA blocks */ |
| 1192 | unsigned int buf_stride; |
| 1193 | |
| 1194 | /* number of blocks to batch between interrupts */ |
| 1195 | int block_irq_interval; |
| 1196 | |
| 1197 | /* block that DMA will finish next */ |
| 1198 | int block_dma; |
| 1199 | |
| 1200 | /* (buffer-fill only) block that the reader will release next */ |
| 1201 | int block_reader; |
| 1202 | |
| 1203 | /* (buffer-fill only) bytes of buffer the reader has released, |
| 1204 | less than one block */ |
| 1205 | int released_bytes; |
| 1206 | |
| 1207 | /* (buffer-fill only) buffer offset at which the next packet will appear */ |
| 1208 | int dma_offset; |
| 1209 | |
| 1210 | /* OHCI DMA context control registers */ |
| 1211 | u32 ContextControlSet; |
| 1212 | u32 ContextControlClear; |
| 1213 | u32 CommandPtr; |
| 1214 | u32 ContextMatch; |
| 1215 | }; |
| 1216 | |
| 1217 | static void ohci_iso_recv_task(unsigned long data); |
| 1218 | static void ohci_iso_recv_stop(struct hpsb_iso *iso); |
| 1219 | static void ohci_iso_recv_shutdown(struct hpsb_iso *iso); |
| 1220 | static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync); |
| 1221 | static void ohci_iso_recv_program(struct hpsb_iso *iso); |
| 1222 | |
| 1223 | static int ohci_iso_recv_init(struct hpsb_iso *iso) |
| 1224 | { |
| 1225 | struct ti_ohci *ohci = iso->host->hostdata; |
| 1226 | struct ohci_iso_recv *recv; |
| 1227 | int ctx; |
| 1228 | int ret = -ENOMEM; |
| 1229 | |
| 1230 | recv = kmalloc(sizeof(*recv), SLAB_KERNEL); |
| 1231 | if (!recv) |
| 1232 | return -ENOMEM; |
| 1233 | |
| 1234 | iso->hostdata = recv; |
| 1235 | recv->ohci = ohci; |
| 1236 | recv->task_active = 0; |
| 1237 | dma_prog_region_init(&recv->prog); |
| 1238 | recv->block = NULL; |
| 1239 | |
| 1240 | /* use buffer-fill mode, unless irq_interval is 1 |
| 1241 | (note: multichannel requires buffer-fill) */ |
| 1242 | |
| 1243 | if (((iso->irq_interval == 1 && iso->dma_mode == HPSB_ISO_DMA_OLD_ABI) || |
| 1244 | iso->dma_mode == HPSB_ISO_DMA_PACKET_PER_BUFFER) && iso->channel != -1) { |
| 1245 | recv->dma_mode = PACKET_PER_BUFFER_MODE; |
| 1246 | } else { |
| 1247 | recv->dma_mode = BUFFER_FILL_MODE; |
| 1248 | } |
| 1249 | |
| 1250 | /* set nblocks, buf_stride, block_irq_interval */ |
| 1251 | |
| 1252 | if (recv->dma_mode == BUFFER_FILL_MODE) { |
| 1253 | recv->buf_stride = PAGE_SIZE; |
| 1254 | |
| 1255 | /* one block per page of data in the DMA buffer, minus the final guard page */ |
| 1256 | recv->nblocks = iso->buf_size/PAGE_SIZE - 1; |
| 1257 | if (recv->nblocks < 3) { |
| 1258 | DBGMSG("ohci_iso_recv_init: DMA buffer too small"); |
| 1259 | goto err; |
| 1260 | } |
| 1261 | |
| 1262 | /* iso->irq_interval is in packets - translate that to blocks */ |
| 1263 | if (iso->irq_interval == 1) |
| 1264 | recv->block_irq_interval = 1; |
| 1265 | else |
| 1266 | recv->block_irq_interval = iso->irq_interval * |
| 1267 | ((recv->nblocks+1)/iso->buf_packets); |
| 1268 | if (recv->block_irq_interval*4 > recv->nblocks) |
| 1269 | recv->block_irq_interval = recv->nblocks/4; |
| 1270 | if (recv->block_irq_interval < 1) |
| 1271 | recv->block_irq_interval = 1; |
| 1272 | |
| 1273 | } else { |
| 1274 | int max_packet_size; |
| 1275 | |
| 1276 | recv->nblocks = iso->buf_packets; |
| 1277 | recv->block_irq_interval = iso->irq_interval; |
| 1278 | if (recv->block_irq_interval * 4 > iso->buf_packets) |
| 1279 | recv->block_irq_interval = iso->buf_packets / 4; |
| 1280 | if (recv->block_irq_interval < 1) |
| 1281 | recv->block_irq_interval = 1; |
| 1282 | |
| 1283 | /* choose a buffer stride */ |
| 1284 | /* must be a power of 2, and <= PAGE_SIZE */ |
| 1285 | |
| 1286 | max_packet_size = iso->buf_size / iso->buf_packets; |
| 1287 | |
| 1288 | for (recv->buf_stride = 8; recv->buf_stride < max_packet_size; |
| 1289 | recv->buf_stride *= 2); |
| 1290 | |
| 1291 | if (recv->buf_stride*iso->buf_packets > iso->buf_size || |
| 1292 | recv->buf_stride > PAGE_SIZE) { |
| 1293 | /* this shouldn't happen, but anyway... */ |
| 1294 | DBGMSG("ohci_iso_recv_init: problem choosing a buffer stride"); |
| 1295 | goto err; |
| 1296 | } |
| 1297 | } |
| 1298 | |
| 1299 | recv->block_reader = 0; |
| 1300 | recv->released_bytes = 0; |
| 1301 | recv->block_dma = 0; |
| 1302 | recv->dma_offset = 0; |
| 1303 | |
| 1304 | /* size of DMA program = one descriptor per block */ |
| 1305 | if (dma_prog_region_alloc(&recv->prog, |
| 1306 | sizeof(struct dma_cmd) * recv->nblocks, |
| 1307 | recv->ohci->dev)) |
| 1308 | goto err; |
| 1309 | |
| 1310 | recv->block = (struct dma_cmd*) recv->prog.kvirt; |
| 1311 | |
| 1312 | ohci1394_init_iso_tasklet(&recv->task, |
| 1313 | iso->channel == -1 ? OHCI_ISO_MULTICHANNEL_RECEIVE : |
| 1314 | OHCI_ISO_RECEIVE, |
| 1315 | ohci_iso_recv_task, (unsigned long) iso); |
| 1316 | |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1317 | if (ohci1394_register_iso_tasklet(recv->ohci, &recv->task) < 0) { |
| 1318 | ret = -EBUSY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1319 | goto err; |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1320 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1321 | |
| 1322 | recv->task_active = 1; |
| 1323 | |
| 1324 | /* recv context registers are spaced 32 bytes apart */ |
| 1325 | ctx = recv->task.context; |
| 1326 | recv->ContextControlSet = OHCI1394_IsoRcvContextControlSet + 32 * ctx; |
| 1327 | recv->ContextControlClear = OHCI1394_IsoRcvContextControlClear + 32 * ctx; |
| 1328 | recv->CommandPtr = OHCI1394_IsoRcvCommandPtr + 32 * ctx; |
| 1329 | recv->ContextMatch = OHCI1394_IsoRcvContextMatch + 32 * ctx; |
| 1330 | |
| 1331 | if (iso->channel == -1) { |
| 1332 | /* clear multi-channel selection mask */ |
| 1333 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, 0xFFFFFFFF); |
| 1334 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, 0xFFFFFFFF); |
| 1335 | } |
| 1336 | |
| 1337 | /* write the DMA program */ |
| 1338 | ohci_iso_recv_program(iso); |
| 1339 | |
| 1340 | DBGMSG("ohci_iso_recv_init: %s mode, DMA buffer is %lu pages" |
| 1341 | " (%u bytes), using %u blocks, buf_stride %u, block_irq_interval %d", |
| 1342 | recv->dma_mode == BUFFER_FILL_MODE ? |
| 1343 | "buffer-fill" : "packet-per-buffer", |
| 1344 | iso->buf_size/PAGE_SIZE, iso->buf_size, |
| 1345 | recv->nblocks, recv->buf_stride, recv->block_irq_interval); |
| 1346 | |
| 1347 | return 0; |
| 1348 | |
| 1349 | err: |
| 1350 | ohci_iso_recv_shutdown(iso); |
| 1351 | return ret; |
| 1352 | } |
| 1353 | |
| 1354 | static void ohci_iso_recv_stop(struct hpsb_iso *iso) |
| 1355 | { |
| 1356 | struct ohci_iso_recv *recv = iso->hostdata; |
| 1357 | |
| 1358 | /* disable interrupts */ |
| 1359 | reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << recv->task.context); |
| 1360 | |
| 1361 | /* halt DMA */ |
| 1362 | ohci1394_stop_context(recv->ohci, recv->ContextControlClear, NULL); |
| 1363 | } |
| 1364 | |
| 1365 | static void ohci_iso_recv_shutdown(struct hpsb_iso *iso) |
| 1366 | { |
| 1367 | struct ohci_iso_recv *recv = iso->hostdata; |
| 1368 | |
| 1369 | if (recv->task_active) { |
| 1370 | ohci_iso_recv_stop(iso); |
| 1371 | ohci1394_unregister_iso_tasklet(recv->ohci, &recv->task); |
| 1372 | recv->task_active = 0; |
| 1373 | } |
| 1374 | |
| 1375 | dma_prog_region_free(&recv->prog); |
| 1376 | kfree(recv); |
| 1377 | iso->hostdata = NULL; |
| 1378 | } |
| 1379 | |
| 1380 | /* set up a "gapped" ring buffer DMA program */ |
| 1381 | static void ohci_iso_recv_program(struct hpsb_iso *iso) |
| 1382 | { |
| 1383 | struct ohci_iso_recv *recv = iso->hostdata; |
| 1384 | int blk; |
| 1385 | |
| 1386 | /* address of 'branch' field in previous DMA descriptor */ |
| 1387 | u32 *prev_branch = NULL; |
| 1388 | |
| 1389 | for (blk = 0; blk < recv->nblocks; blk++) { |
| 1390 | u32 control; |
| 1391 | |
| 1392 | /* the DMA descriptor */ |
| 1393 | struct dma_cmd *cmd = &recv->block[blk]; |
| 1394 | |
| 1395 | /* offset of the DMA descriptor relative to the DMA prog buffer */ |
| 1396 | unsigned long prog_offset = blk * sizeof(struct dma_cmd); |
| 1397 | |
| 1398 | /* offset of this packet's data within the DMA buffer */ |
| 1399 | unsigned long buf_offset = blk * recv->buf_stride; |
| 1400 | |
| 1401 | if (recv->dma_mode == BUFFER_FILL_MODE) { |
| 1402 | control = 2 << 28; /* INPUT_MORE */ |
| 1403 | } else { |
| 1404 | control = 3 << 28; /* INPUT_LAST */ |
| 1405 | } |
| 1406 | |
| 1407 | control |= 8 << 24; /* s = 1, update xferStatus and resCount */ |
| 1408 | |
| 1409 | /* interrupt on last block, and at intervals */ |
| 1410 | if (blk == recv->nblocks-1 || (blk % recv->block_irq_interval) == 0) { |
| 1411 | control |= 3 << 20; /* want interrupt */ |
| 1412 | } |
| 1413 | |
| 1414 | control |= 3 << 18; /* enable branch to address */ |
| 1415 | control |= recv->buf_stride; |
| 1416 | |
| 1417 | cmd->control = cpu_to_le32(control); |
| 1418 | cmd->address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, buf_offset)); |
| 1419 | cmd->branchAddress = 0; /* filled in on next loop */ |
| 1420 | cmd->status = cpu_to_le32(recv->buf_stride); |
| 1421 | |
| 1422 | /* link the previous descriptor to this one */ |
| 1423 | if (prev_branch) { |
| 1424 | *prev_branch = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog, prog_offset) | 1); |
| 1425 | } |
| 1426 | |
| 1427 | prev_branch = &cmd->branchAddress; |
| 1428 | } |
| 1429 | |
| 1430 | /* the final descriptor's branch address and Z should be left at 0 */ |
| 1431 | } |
| 1432 | |
| 1433 | /* listen or unlisten to a specific channel (multi-channel mode only) */ |
| 1434 | static void ohci_iso_recv_change_channel(struct hpsb_iso *iso, unsigned char channel, int listen) |
| 1435 | { |
| 1436 | struct ohci_iso_recv *recv = iso->hostdata; |
| 1437 | int reg, i; |
| 1438 | |
| 1439 | if (channel < 32) { |
| 1440 | reg = listen ? OHCI1394_IRMultiChanMaskLoSet : OHCI1394_IRMultiChanMaskLoClear; |
| 1441 | i = channel; |
| 1442 | } else { |
| 1443 | reg = listen ? OHCI1394_IRMultiChanMaskHiSet : OHCI1394_IRMultiChanMaskHiClear; |
| 1444 | i = channel - 32; |
| 1445 | } |
| 1446 | |
| 1447 | reg_write(recv->ohci, reg, (1 << i)); |
| 1448 | |
| 1449 | /* issue a dummy read to force all PCI writes to be posted immediately */ |
| 1450 | mb(); |
| 1451 | reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer); |
| 1452 | } |
| 1453 | |
| 1454 | static void ohci_iso_recv_set_channel_mask(struct hpsb_iso *iso, u64 mask) |
| 1455 | { |
| 1456 | struct ohci_iso_recv *recv = iso->hostdata; |
| 1457 | int i; |
| 1458 | |
| 1459 | for (i = 0; i < 64; i++) { |
| 1460 | if (mask & (1ULL << i)) { |
| 1461 | if (i < 32) |
| 1462 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoSet, (1 << i)); |
| 1463 | else |
| 1464 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiSet, (1 << (i-32))); |
| 1465 | } else { |
| 1466 | if (i < 32) |
| 1467 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, (1 << i)); |
| 1468 | else |
| 1469 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, (1 << (i-32))); |
| 1470 | } |
| 1471 | } |
| 1472 | |
| 1473 | /* issue a dummy read to force all PCI writes to be posted immediately */ |
| 1474 | mb(); |
| 1475 | reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer); |
| 1476 | } |
| 1477 | |
| 1478 | static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync) |
| 1479 | { |
| 1480 | struct ohci_iso_recv *recv = iso->hostdata; |
| 1481 | struct ti_ohci *ohci = recv->ohci; |
| 1482 | u32 command, contextMatch; |
| 1483 | |
| 1484 | reg_write(recv->ohci, recv->ContextControlClear, 0xFFFFFFFF); |
| 1485 | wmb(); |
| 1486 | |
| 1487 | /* always keep ISO headers */ |
| 1488 | command = (1 << 30); |
| 1489 | |
| 1490 | if (recv->dma_mode == BUFFER_FILL_MODE) |
| 1491 | command |= (1 << 31); |
| 1492 | |
| 1493 | reg_write(recv->ohci, recv->ContextControlSet, command); |
| 1494 | |
| 1495 | /* match on specified tags */ |
| 1496 | contextMatch = tag_mask << 28; |
| 1497 | |
| 1498 | if (iso->channel == -1) { |
| 1499 | /* enable multichannel reception */ |
| 1500 | reg_write(recv->ohci, recv->ContextControlSet, (1 << 28)); |
| 1501 | } else { |
| 1502 | /* listen on channel */ |
| 1503 | contextMatch |= iso->channel; |
| 1504 | } |
| 1505 | |
| 1506 | if (cycle != -1) { |
| 1507 | u32 seconds; |
| 1508 | |
| 1509 | /* enable cycleMatch */ |
| 1510 | reg_write(recv->ohci, recv->ContextControlSet, (1 << 29)); |
| 1511 | |
| 1512 | /* set starting cycle */ |
| 1513 | cycle &= 0x1FFF; |
| 1514 | |
| 1515 | /* 'cycle' is only mod 8000, but we also need two 'seconds' bits - |
| 1516 | just snarf them from the current time */ |
| 1517 | seconds = reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer) >> 25; |
| 1518 | |
| 1519 | /* advance one second to give some extra time for DMA to start */ |
| 1520 | seconds += 1; |
| 1521 | |
| 1522 | cycle |= (seconds & 3) << 13; |
| 1523 | |
| 1524 | contextMatch |= cycle << 12; |
| 1525 | } |
| 1526 | |
| 1527 | if (sync != -1) { |
| 1528 | /* set sync flag on first DMA descriptor */ |
| 1529 | struct dma_cmd *cmd = &recv->block[recv->block_dma]; |
| 1530 | cmd->control |= cpu_to_le32(DMA_CTL_WAIT); |
| 1531 | |
| 1532 | /* match sync field */ |
| 1533 | contextMatch |= (sync&0xf)<<8; |
| 1534 | } |
| 1535 | |
| 1536 | reg_write(recv->ohci, recv->ContextMatch, contextMatch); |
| 1537 | |
| 1538 | /* address of first descriptor block */ |
| 1539 | command = dma_prog_region_offset_to_bus(&recv->prog, |
| 1540 | recv->block_dma * sizeof(struct dma_cmd)); |
| 1541 | command |= 1; /* Z=1 */ |
| 1542 | |
| 1543 | reg_write(recv->ohci, recv->CommandPtr, command); |
| 1544 | |
| 1545 | /* enable interrupts */ |
| 1546 | reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskSet, 1 << recv->task.context); |
| 1547 | |
| 1548 | wmb(); |
| 1549 | |
| 1550 | /* run */ |
| 1551 | reg_write(recv->ohci, recv->ContextControlSet, 0x8000); |
| 1552 | |
| 1553 | /* issue a dummy read of the cycle timer register to force |
| 1554 | all PCI writes to be posted immediately */ |
| 1555 | mb(); |
| 1556 | reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer); |
| 1557 | |
| 1558 | /* check RUN */ |
| 1559 | if (!(reg_read(recv->ohci, recv->ContextControlSet) & 0x8000)) { |
| 1560 | PRINT(KERN_ERR, |
| 1561 | "Error starting IR DMA (ContextControl 0x%08x)\n", |
| 1562 | reg_read(recv->ohci, recv->ContextControlSet)); |
| 1563 | return -1; |
| 1564 | } |
| 1565 | |
| 1566 | return 0; |
| 1567 | } |
| 1568 | |
| 1569 | static void ohci_iso_recv_release_block(struct ohci_iso_recv *recv, int block) |
| 1570 | { |
| 1571 | /* re-use the DMA descriptor for the block */ |
| 1572 | /* by linking the previous descriptor to it */ |
| 1573 | |
| 1574 | int next_i = block; |
| 1575 | int prev_i = (next_i == 0) ? (recv->nblocks - 1) : (next_i - 1); |
| 1576 | |
| 1577 | struct dma_cmd *next = &recv->block[next_i]; |
| 1578 | struct dma_cmd *prev = &recv->block[prev_i]; |
Ben Collins | 1934b8b | 2005-07-09 20:01:23 -0400 | [diff] [blame] | 1579 | |
| 1580 | /* ignore out-of-range requests */ |
| 1581 | if ((block < 0) || (block > recv->nblocks)) |
| 1582 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1583 | |
| 1584 | /* 'next' becomes the new end of the DMA chain, |
| 1585 | so disable branch and enable interrupt */ |
| 1586 | next->branchAddress = 0; |
| 1587 | next->control |= cpu_to_le32(3 << 20); |
| 1588 | next->status = cpu_to_le32(recv->buf_stride); |
| 1589 | |
| 1590 | /* link prev to next */ |
| 1591 | prev->branchAddress = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog, |
| 1592 | sizeof(struct dma_cmd) * next_i) |
| 1593 | | 1); /* Z=1 */ |
| 1594 | |
| 1595 | /* disable interrupt on previous DMA descriptor, except at intervals */ |
| 1596 | if ((prev_i % recv->block_irq_interval) == 0) { |
| 1597 | prev->control |= cpu_to_le32(3 << 20); /* enable interrupt */ |
| 1598 | } else { |
| 1599 | prev->control &= cpu_to_le32(~(3<<20)); /* disable interrupt */ |
| 1600 | } |
| 1601 | wmb(); |
| 1602 | |
| 1603 | /* wake up DMA in case it fell asleep */ |
| 1604 | reg_write(recv->ohci, recv->ContextControlSet, (1 << 12)); |
| 1605 | } |
| 1606 | |
| 1607 | static void ohci_iso_recv_bufferfill_release(struct ohci_iso_recv *recv, |
| 1608 | struct hpsb_iso_packet_info *info) |
| 1609 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1610 | /* release the memory where the packet was */ |
Ben Collins | 1934b8b | 2005-07-09 20:01:23 -0400 | [diff] [blame] | 1611 | recv->released_bytes += info->total_len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1612 | |
| 1613 | /* have we released enough memory for one block? */ |
| 1614 | while (recv->released_bytes > recv->buf_stride) { |
| 1615 | ohci_iso_recv_release_block(recv, recv->block_reader); |
| 1616 | recv->block_reader = (recv->block_reader + 1) % recv->nblocks; |
| 1617 | recv->released_bytes -= recv->buf_stride; |
| 1618 | } |
| 1619 | } |
| 1620 | |
| 1621 | static inline void ohci_iso_recv_release(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info) |
| 1622 | { |
| 1623 | struct ohci_iso_recv *recv = iso->hostdata; |
| 1624 | if (recv->dma_mode == BUFFER_FILL_MODE) { |
| 1625 | ohci_iso_recv_bufferfill_release(recv, info); |
| 1626 | } else { |
| 1627 | ohci_iso_recv_release_block(recv, info - iso->infos); |
| 1628 | } |
| 1629 | } |
| 1630 | |
| 1631 | /* parse all packets from blocks that have been fully received */ |
| 1632 | static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso_recv *recv) |
| 1633 | { |
| 1634 | int wake = 0; |
| 1635 | int runaway = 0; |
| 1636 | struct ti_ohci *ohci = recv->ohci; |
| 1637 | |
| 1638 | while (1) { |
| 1639 | /* we expect the next parsable packet to begin at recv->dma_offset */ |
| 1640 | /* note: packet layout is as shown in section 10.6.1.1 of the OHCI spec */ |
| 1641 | |
| 1642 | unsigned int offset; |
Ben Collins | 1934b8b | 2005-07-09 20:01:23 -0400 | [diff] [blame] | 1643 | unsigned short len, cycle, total_len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1644 | unsigned char channel, tag, sy; |
| 1645 | |
| 1646 | unsigned char *p = iso->data_buf.kvirt; |
| 1647 | |
| 1648 | unsigned int this_block = recv->dma_offset/recv->buf_stride; |
| 1649 | |
| 1650 | /* don't loop indefinitely */ |
| 1651 | if (runaway++ > 100000) { |
| 1652 | atomic_inc(&iso->overflows); |
| 1653 | PRINT(KERN_ERR, |
| 1654 | "IR DMA error - Runaway during buffer parsing!\n"); |
| 1655 | break; |
| 1656 | } |
| 1657 | |
| 1658 | /* stop parsing once we arrive at block_dma (i.e. don't get ahead of DMA) */ |
| 1659 | if (this_block == recv->block_dma) |
| 1660 | break; |
| 1661 | |
| 1662 | wake = 1; |
| 1663 | |
| 1664 | /* parse data length, tag, channel, and sy */ |
| 1665 | |
| 1666 | /* note: we keep our own local copies of 'len' and 'offset' |
| 1667 | so the user can't mess with them by poking in the mmap area */ |
| 1668 | |
| 1669 | len = p[recv->dma_offset+2] | (p[recv->dma_offset+3] << 8); |
| 1670 | |
| 1671 | if (len > 4096) { |
| 1672 | PRINT(KERN_ERR, |
| 1673 | "IR DMA error - bogus 'len' value %u\n", len); |
| 1674 | } |
| 1675 | |
| 1676 | channel = p[recv->dma_offset+1] & 0x3F; |
| 1677 | tag = p[recv->dma_offset+1] >> 6; |
| 1678 | sy = p[recv->dma_offset+0] & 0xF; |
| 1679 | |
| 1680 | /* advance to data payload */ |
| 1681 | recv->dma_offset += 4; |
| 1682 | |
| 1683 | /* check for wrap-around */ |
| 1684 | if (recv->dma_offset >= recv->buf_stride*recv->nblocks) { |
| 1685 | recv->dma_offset -= recv->buf_stride*recv->nblocks; |
| 1686 | } |
| 1687 | |
| 1688 | /* dma_offset now points to the first byte of the data payload */ |
| 1689 | offset = recv->dma_offset; |
| 1690 | |
| 1691 | /* advance to xferStatus/timeStamp */ |
| 1692 | recv->dma_offset += len; |
| 1693 | |
Ben Collins | 1934b8b | 2005-07-09 20:01:23 -0400 | [diff] [blame] | 1694 | total_len = len + 8; /* 8 bytes header+trailer in OHCI packet */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1695 | /* payload is padded to 4 bytes */ |
| 1696 | if (len % 4) { |
| 1697 | recv->dma_offset += 4 - (len%4); |
Ben Collins | 1934b8b | 2005-07-09 20:01:23 -0400 | [diff] [blame] | 1698 | total_len += 4 - (len%4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | } |
| 1700 | |
| 1701 | /* check for wrap-around */ |
| 1702 | if (recv->dma_offset >= recv->buf_stride*recv->nblocks) { |
| 1703 | /* uh oh, the packet data wraps from the last |
| 1704 | to the first DMA block - make the packet |
| 1705 | contiguous by copying its "tail" into the |
| 1706 | guard page */ |
| 1707 | |
| 1708 | int guard_off = recv->buf_stride*recv->nblocks; |
| 1709 | int tail_len = len - (guard_off - offset); |
| 1710 | |
| 1711 | if (tail_len > 0 && tail_len < recv->buf_stride) { |
| 1712 | memcpy(iso->data_buf.kvirt + guard_off, |
| 1713 | iso->data_buf.kvirt, |
| 1714 | tail_len); |
| 1715 | } |
| 1716 | |
| 1717 | recv->dma_offset -= recv->buf_stride*recv->nblocks; |
| 1718 | } |
| 1719 | |
| 1720 | /* parse timestamp */ |
| 1721 | cycle = p[recv->dma_offset+0] | (p[recv->dma_offset+1]<<8); |
| 1722 | cycle &= 0x1FFF; |
| 1723 | |
| 1724 | /* advance to next packet */ |
| 1725 | recv->dma_offset += 4; |
| 1726 | |
| 1727 | /* check for wrap-around */ |
| 1728 | if (recv->dma_offset >= recv->buf_stride*recv->nblocks) { |
| 1729 | recv->dma_offset -= recv->buf_stride*recv->nblocks; |
| 1730 | } |
| 1731 | |
Ben Collins | 1934b8b | 2005-07-09 20:01:23 -0400 | [diff] [blame] | 1732 | hpsb_iso_packet_received(iso, offset, len, total_len, cycle, channel, tag, sy); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1733 | } |
| 1734 | |
| 1735 | if (wake) |
| 1736 | hpsb_iso_wake(iso); |
| 1737 | } |
| 1738 | |
| 1739 | static void ohci_iso_recv_bufferfill_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv) |
| 1740 | { |
| 1741 | int loop; |
| 1742 | struct ti_ohci *ohci = recv->ohci; |
| 1743 | |
| 1744 | /* loop over all blocks */ |
| 1745 | for (loop = 0; loop < recv->nblocks; loop++) { |
| 1746 | |
| 1747 | /* check block_dma to see if it's done */ |
| 1748 | struct dma_cmd *im = &recv->block[recv->block_dma]; |
| 1749 | |
| 1750 | /* check the DMA descriptor for new writes to xferStatus */ |
| 1751 | u16 xferstatus = le32_to_cpu(im->status) >> 16; |
| 1752 | |
| 1753 | /* rescount is the number of bytes *remaining to be written* in the block */ |
| 1754 | u16 rescount = le32_to_cpu(im->status) & 0xFFFF; |
| 1755 | |
| 1756 | unsigned char event = xferstatus & 0x1F; |
| 1757 | |
| 1758 | if (!event) { |
| 1759 | /* nothing has happened to this block yet */ |
| 1760 | break; |
| 1761 | } |
| 1762 | |
| 1763 | if (event != 0x11) { |
| 1764 | atomic_inc(&iso->overflows); |
| 1765 | PRINT(KERN_ERR, |
| 1766 | "IR DMA error - OHCI error code 0x%02x\n", event); |
| 1767 | } |
| 1768 | |
| 1769 | if (rescount != 0) { |
| 1770 | /* the card is still writing to this block; |
| 1771 | we can't touch it until it's done */ |
| 1772 | break; |
| 1773 | } |
| 1774 | |
| 1775 | /* OK, the block is finished... */ |
| 1776 | |
| 1777 | /* sync our view of the block */ |
| 1778 | dma_region_sync_for_cpu(&iso->data_buf, recv->block_dma*recv->buf_stride, recv->buf_stride); |
| 1779 | |
| 1780 | /* reset the DMA descriptor */ |
| 1781 | im->status = recv->buf_stride; |
| 1782 | |
| 1783 | /* advance block_dma */ |
| 1784 | recv->block_dma = (recv->block_dma + 1) % recv->nblocks; |
| 1785 | |
| 1786 | if ((recv->block_dma+1) % recv->nblocks == recv->block_reader) { |
| 1787 | atomic_inc(&iso->overflows); |
| 1788 | DBGMSG("ISO reception overflow - " |
| 1789 | "ran out of DMA blocks"); |
| 1790 | } |
| 1791 | } |
| 1792 | |
| 1793 | /* parse any packets that have arrived */ |
| 1794 | ohci_iso_recv_bufferfill_parse(iso, recv); |
| 1795 | } |
| 1796 | |
| 1797 | static void ohci_iso_recv_packetperbuf_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv) |
| 1798 | { |
| 1799 | int count; |
| 1800 | int wake = 0; |
| 1801 | struct ti_ohci *ohci = recv->ohci; |
| 1802 | |
| 1803 | /* loop over the entire buffer */ |
| 1804 | for (count = 0; count < recv->nblocks; count++) { |
| 1805 | u32 packet_len = 0; |
| 1806 | |
| 1807 | /* pointer to the DMA descriptor */ |
| 1808 | struct dma_cmd *il = ((struct dma_cmd*) recv->prog.kvirt) + iso->pkt_dma; |
| 1809 | |
| 1810 | /* check the DMA descriptor for new writes to xferStatus */ |
| 1811 | u16 xferstatus = le32_to_cpu(il->status) >> 16; |
| 1812 | u16 rescount = le32_to_cpu(il->status) & 0xFFFF; |
| 1813 | |
| 1814 | unsigned char event = xferstatus & 0x1F; |
| 1815 | |
| 1816 | if (!event) { |
| 1817 | /* this packet hasn't come in yet; we are done for now */ |
| 1818 | goto out; |
| 1819 | } |
| 1820 | |
| 1821 | if (event == 0x11) { |
| 1822 | /* packet received successfully! */ |
| 1823 | |
| 1824 | /* rescount is the number of bytes *remaining* in the packet buffer, |
| 1825 | after the packet was written */ |
| 1826 | packet_len = recv->buf_stride - rescount; |
| 1827 | |
| 1828 | } else if (event == 0x02) { |
| 1829 | PRINT(KERN_ERR, "IR DMA error - packet too long for buffer\n"); |
| 1830 | } else if (event) { |
| 1831 | PRINT(KERN_ERR, "IR DMA error - OHCI error code 0x%02x\n", event); |
| 1832 | } |
| 1833 | |
| 1834 | /* sync our view of the buffer */ |
| 1835 | dma_region_sync_for_cpu(&iso->data_buf, iso->pkt_dma * recv->buf_stride, recv->buf_stride); |
| 1836 | |
| 1837 | /* record the per-packet info */ |
| 1838 | { |
| 1839 | /* iso header is 8 bytes ahead of the data payload */ |
| 1840 | unsigned char *hdr; |
| 1841 | |
| 1842 | unsigned int offset; |
| 1843 | unsigned short cycle; |
| 1844 | unsigned char channel, tag, sy; |
| 1845 | |
| 1846 | offset = iso->pkt_dma * recv->buf_stride; |
| 1847 | hdr = iso->data_buf.kvirt + offset; |
| 1848 | |
| 1849 | /* skip iso header */ |
| 1850 | offset += 8; |
| 1851 | packet_len -= 8; |
| 1852 | |
| 1853 | cycle = (hdr[0] | (hdr[1] << 8)) & 0x1FFF; |
| 1854 | channel = hdr[5] & 0x3F; |
| 1855 | tag = hdr[5] >> 6; |
| 1856 | sy = hdr[4] & 0xF; |
| 1857 | |
Ben Collins | 1934b8b | 2005-07-09 20:01:23 -0400 | [diff] [blame] | 1858 | hpsb_iso_packet_received(iso, offset, packet_len, |
| 1859 | recv->buf_stride, cycle, channel, tag, sy); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1860 | } |
| 1861 | |
| 1862 | /* reset the DMA descriptor */ |
| 1863 | il->status = recv->buf_stride; |
| 1864 | |
| 1865 | wake = 1; |
| 1866 | recv->block_dma = iso->pkt_dma; |
| 1867 | } |
| 1868 | |
| 1869 | out: |
| 1870 | if (wake) |
| 1871 | hpsb_iso_wake(iso); |
| 1872 | } |
| 1873 | |
| 1874 | static void ohci_iso_recv_task(unsigned long data) |
| 1875 | { |
| 1876 | struct hpsb_iso *iso = (struct hpsb_iso*) data; |
| 1877 | struct ohci_iso_recv *recv = iso->hostdata; |
| 1878 | |
| 1879 | if (recv->dma_mode == BUFFER_FILL_MODE) |
| 1880 | ohci_iso_recv_bufferfill_task(iso, recv); |
| 1881 | else |
| 1882 | ohci_iso_recv_packetperbuf_task(iso, recv); |
| 1883 | } |
| 1884 | |
| 1885 | /*********************************** |
| 1886 | * rawiso ISO transmission * |
| 1887 | ***********************************/ |
| 1888 | |
| 1889 | struct ohci_iso_xmit { |
| 1890 | struct ti_ohci *ohci; |
| 1891 | struct dma_prog_region prog; |
| 1892 | struct ohci1394_iso_tasklet task; |
| 1893 | int task_active; |
| 1894 | |
| 1895 | u32 ContextControlSet; |
| 1896 | u32 ContextControlClear; |
| 1897 | u32 CommandPtr; |
| 1898 | }; |
| 1899 | |
| 1900 | /* transmission DMA program: |
| 1901 | one OUTPUT_MORE_IMMEDIATE for the IT header |
| 1902 | one OUTPUT_LAST for the buffer data */ |
| 1903 | |
| 1904 | struct iso_xmit_cmd { |
| 1905 | struct dma_cmd output_more_immediate; |
| 1906 | u8 iso_hdr[8]; |
| 1907 | u32 unused[2]; |
| 1908 | struct dma_cmd output_last; |
| 1909 | }; |
| 1910 | |
| 1911 | static int ohci_iso_xmit_init(struct hpsb_iso *iso); |
| 1912 | static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle); |
| 1913 | static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso); |
| 1914 | static void ohci_iso_xmit_task(unsigned long data); |
| 1915 | |
| 1916 | static int ohci_iso_xmit_init(struct hpsb_iso *iso) |
| 1917 | { |
| 1918 | struct ohci_iso_xmit *xmit; |
| 1919 | unsigned int prog_size; |
| 1920 | int ctx; |
| 1921 | int ret = -ENOMEM; |
| 1922 | |
| 1923 | xmit = kmalloc(sizeof(*xmit), SLAB_KERNEL); |
| 1924 | if (!xmit) |
| 1925 | return -ENOMEM; |
| 1926 | |
| 1927 | iso->hostdata = xmit; |
| 1928 | xmit->ohci = iso->host->hostdata; |
| 1929 | xmit->task_active = 0; |
| 1930 | |
| 1931 | dma_prog_region_init(&xmit->prog); |
| 1932 | |
| 1933 | prog_size = sizeof(struct iso_xmit_cmd) * iso->buf_packets; |
| 1934 | |
| 1935 | if (dma_prog_region_alloc(&xmit->prog, prog_size, xmit->ohci->dev)) |
| 1936 | goto err; |
| 1937 | |
| 1938 | ohci1394_init_iso_tasklet(&xmit->task, OHCI_ISO_TRANSMIT, |
| 1939 | ohci_iso_xmit_task, (unsigned long) iso); |
| 1940 | |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1941 | if (ohci1394_register_iso_tasklet(xmit->ohci, &xmit->task) < 0) { |
| 1942 | ret = -EBUSY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1943 | goto err; |
Jody McIntyre | e4ec0f2 | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 1944 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1945 | |
| 1946 | xmit->task_active = 1; |
| 1947 | |
| 1948 | /* xmit context registers are spaced 16 bytes apart */ |
| 1949 | ctx = xmit->task.context; |
| 1950 | xmit->ContextControlSet = OHCI1394_IsoXmitContextControlSet + 16 * ctx; |
| 1951 | xmit->ContextControlClear = OHCI1394_IsoXmitContextControlClear + 16 * ctx; |
| 1952 | xmit->CommandPtr = OHCI1394_IsoXmitCommandPtr + 16 * ctx; |
| 1953 | |
| 1954 | return 0; |
| 1955 | |
| 1956 | err: |
| 1957 | ohci_iso_xmit_shutdown(iso); |
| 1958 | return ret; |
| 1959 | } |
| 1960 | |
| 1961 | static void ohci_iso_xmit_stop(struct hpsb_iso *iso) |
| 1962 | { |
| 1963 | struct ohci_iso_xmit *xmit = iso->hostdata; |
| 1964 | struct ti_ohci *ohci = xmit->ohci; |
| 1965 | |
| 1966 | /* disable interrupts */ |
| 1967 | reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskClear, 1 << xmit->task.context); |
| 1968 | |
| 1969 | /* halt DMA */ |
| 1970 | if (ohci1394_stop_context(xmit->ohci, xmit->ContextControlClear, NULL)) { |
| 1971 | /* XXX the DMA context will lock up if you try to send too much data! */ |
| 1972 | PRINT(KERN_ERR, |
| 1973 | "you probably exceeded the OHCI card's bandwidth limit - " |
| 1974 | "reload the module and reduce xmit bandwidth"); |
| 1975 | } |
| 1976 | } |
| 1977 | |
| 1978 | static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso) |
| 1979 | { |
| 1980 | struct ohci_iso_xmit *xmit = iso->hostdata; |
| 1981 | |
| 1982 | if (xmit->task_active) { |
| 1983 | ohci_iso_xmit_stop(iso); |
| 1984 | ohci1394_unregister_iso_tasklet(xmit->ohci, &xmit->task); |
| 1985 | xmit->task_active = 0; |
| 1986 | } |
| 1987 | |
| 1988 | dma_prog_region_free(&xmit->prog); |
| 1989 | kfree(xmit); |
| 1990 | iso->hostdata = NULL; |
| 1991 | } |
| 1992 | |
| 1993 | static void ohci_iso_xmit_task(unsigned long data) |
| 1994 | { |
| 1995 | struct hpsb_iso *iso = (struct hpsb_iso*) data; |
| 1996 | struct ohci_iso_xmit *xmit = iso->hostdata; |
| 1997 | struct ti_ohci *ohci = xmit->ohci; |
| 1998 | int wake = 0; |
| 1999 | int count; |
| 2000 | |
| 2001 | /* check the whole buffer if necessary, starting at pkt_dma */ |
| 2002 | for (count = 0; count < iso->buf_packets; count++) { |
| 2003 | int cycle; |
| 2004 | |
| 2005 | /* DMA descriptor */ |
| 2006 | struct iso_xmit_cmd *cmd = dma_region_i(&xmit->prog, struct iso_xmit_cmd, iso->pkt_dma); |
| 2007 | |
| 2008 | /* check for new writes to xferStatus */ |
| 2009 | u16 xferstatus = le32_to_cpu(cmd->output_last.status) >> 16; |
| 2010 | u8 event = xferstatus & 0x1F; |
| 2011 | |
| 2012 | if (!event) { |
| 2013 | /* packet hasn't been sent yet; we are done for now */ |
| 2014 | break; |
| 2015 | } |
| 2016 | |
| 2017 | if (event != 0x11) |
| 2018 | PRINT(KERN_ERR, |
| 2019 | "IT DMA error - OHCI error code 0x%02x\n", event); |
| 2020 | |
| 2021 | /* at least one packet went out, so wake up the writer */ |
| 2022 | wake = 1; |
| 2023 | |
| 2024 | /* parse cycle */ |
| 2025 | cycle = le32_to_cpu(cmd->output_last.status) & 0x1FFF; |
| 2026 | |
| 2027 | /* tell the subsystem the packet has gone out */ |
| 2028 | hpsb_iso_packet_sent(iso, cycle, event != 0x11); |
| 2029 | |
| 2030 | /* reset the DMA descriptor for next time */ |
| 2031 | cmd->output_last.status = 0; |
| 2032 | } |
| 2033 | |
| 2034 | if (wake) |
| 2035 | hpsb_iso_wake(iso); |
| 2036 | } |
| 2037 | |
| 2038 | static int ohci_iso_xmit_queue(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info) |
| 2039 | { |
| 2040 | struct ohci_iso_xmit *xmit = iso->hostdata; |
| 2041 | struct ti_ohci *ohci = xmit->ohci; |
| 2042 | |
| 2043 | int next_i, prev_i; |
| 2044 | struct iso_xmit_cmd *next, *prev; |
| 2045 | |
| 2046 | unsigned int offset; |
| 2047 | unsigned short len; |
| 2048 | unsigned char tag, sy; |
| 2049 | |
| 2050 | /* check that the packet doesn't cross a page boundary |
| 2051 | (we could allow this if we added OUTPUT_MORE descriptor support) */ |
| 2052 | if (cross_bound(info->offset, info->len)) { |
| 2053 | PRINT(KERN_ERR, |
| 2054 | "rawiso xmit: packet %u crosses a page boundary", |
| 2055 | iso->first_packet); |
| 2056 | return -EINVAL; |
| 2057 | } |
| 2058 | |
| 2059 | offset = info->offset; |
| 2060 | len = info->len; |
| 2061 | tag = info->tag; |
| 2062 | sy = info->sy; |
| 2063 | |
| 2064 | /* sync up the card's view of the buffer */ |
| 2065 | dma_region_sync_for_device(&iso->data_buf, offset, len); |
| 2066 | |
| 2067 | /* append first_packet to the DMA chain */ |
| 2068 | /* by linking the previous descriptor to it */ |
| 2069 | /* (next will become the new end of the DMA chain) */ |
| 2070 | |
| 2071 | next_i = iso->first_packet; |
| 2072 | prev_i = (next_i == 0) ? (iso->buf_packets - 1) : (next_i - 1); |
| 2073 | |
| 2074 | next = dma_region_i(&xmit->prog, struct iso_xmit_cmd, next_i); |
| 2075 | prev = dma_region_i(&xmit->prog, struct iso_xmit_cmd, prev_i); |
| 2076 | |
| 2077 | /* set up the OUTPUT_MORE_IMMEDIATE descriptor */ |
| 2078 | memset(next, 0, sizeof(struct iso_xmit_cmd)); |
| 2079 | next->output_more_immediate.control = cpu_to_le32(0x02000008); |
| 2080 | |
| 2081 | /* ISO packet header is embedded in the OUTPUT_MORE_IMMEDIATE */ |
| 2082 | |
| 2083 | /* tcode = 0xA, and sy */ |
| 2084 | next->iso_hdr[0] = 0xA0 | (sy & 0xF); |
| 2085 | |
| 2086 | /* tag and channel number */ |
| 2087 | next->iso_hdr[1] = (tag << 6) | (iso->channel & 0x3F); |
| 2088 | |
| 2089 | /* transmission speed */ |
| 2090 | next->iso_hdr[2] = iso->speed & 0x7; |
| 2091 | |
| 2092 | /* payload size */ |
| 2093 | next->iso_hdr[6] = len & 0xFF; |
| 2094 | next->iso_hdr[7] = len >> 8; |
| 2095 | |
| 2096 | /* set up the OUTPUT_LAST */ |
| 2097 | next->output_last.control = cpu_to_le32(1 << 28); |
| 2098 | next->output_last.control |= cpu_to_le32(1 << 27); /* update timeStamp */ |
| 2099 | next->output_last.control |= cpu_to_le32(3 << 20); /* want interrupt */ |
| 2100 | next->output_last.control |= cpu_to_le32(3 << 18); /* enable branch */ |
| 2101 | next->output_last.control |= cpu_to_le32(len); |
| 2102 | |
| 2103 | /* payload bus address */ |
| 2104 | next->output_last.address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, offset)); |
| 2105 | |
| 2106 | /* leave branchAddress at zero for now */ |
| 2107 | |
| 2108 | /* re-write the previous DMA descriptor to chain to this one */ |
| 2109 | |
| 2110 | /* set prev branch address to point to next (Z=3) */ |
| 2111 | prev->output_last.branchAddress = cpu_to_le32( |
| 2112 | dma_prog_region_offset_to_bus(&xmit->prog, sizeof(struct iso_xmit_cmd) * next_i) | 3); |
| 2113 | |
| 2114 | /* disable interrupt, unless required by the IRQ interval */ |
| 2115 | if (prev_i % iso->irq_interval) { |
| 2116 | prev->output_last.control &= cpu_to_le32(~(3 << 20)); /* no interrupt */ |
| 2117 | } else { |
| 2118 | prev->output_last.control |= cpu_to_le32(3 << 20); /* enable interrupt */ |
| 2119 | } |
| 2120 | |
| 2121 | wmb(); |
| 2122 | |
| 2123 | /* wake DMA in case it is sleeping */ |
| 2124 | reg_write(xmit->ohci, xmit->ContextControlSet, 1 << 12); |
| 2125 | |
| 2126 | /* issue a dummy read of the cycle timer to force all PCI |
| 2127 | writes to be posted immediately */ |
| 2128 | mb(); |
| 2129 | reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer); |
| 2130 | |
| 2131 | return 0; |
| 2132 | } |
| 2133 | |
| 2134 | static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle) |
| 2135 | { |
| 2136 | struct ohci_iso_xmit *xmit = iso->hostdata; |
| 2137 | struct ti_ohci *ohci = xmit->ohci; |
| 2138 | |
| 2139 | /* clear out the control register */ |
| 2140 | reg_write(xmit->ohci, xmit->ContextControlClear, 0xFFFFFFFF); |
| 2141 | wmb(); |
| 2142 | |
| 2143 | /* address and length of first descriptor block (Z=3) */ |
| 2144 | reg_write(xmit->ohci, xmit->CommandPtr, |
| 2145 | dma_prog_region_offset_to_bus(&xmit->prog, iso->pkt_dma * sizeof(struct iso_xmit_cmd)) | 3); |
| 2146 | |
| 2147 | /* cycle match */ |
| 2148 | if (cycle != -1) { |
| 2149 | u32 start = cycle & 0x1FFF; |
| 2150 | |
| 2151 | /* 'cycle' is only mod 8000, but we also need two 'seconds' bits - |
| 2152 | just snarf them from the current time */ |
| 2153 | u32 seconds = reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer) >> 25; |
| 2154 | |
| 2155 | /* advance one second to give some extra time for DMA to start */ |
| 2156 | seconds += 1; |
| 2157 | |
| 2158 | start |= (seconds & 3) << 13; |
| 2159 | |
| 2160 | reg_write(xmit->ohci, xmit->ContextControlSet, 0x80000000 | (start << 16)); |
| 2161 | } |
| 2162 | |
| 2163 | /* enable interrupts */ |
| 2164 | reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskSet, 1 << xmit->task.context); |
| 2165 | |
| 2166 | /* run */ |
| 2167 | reg_write(xmit->ohci, xmit->ContextControlSet, 0x8000); |
| 2168 | mb(); |
| 2169 | |
| 2170 | /* wait 100 usec to give the card time to go active */ |
| 2171 | udelay(100); |
| 2172 | |
| 2173 | /* check the RUN bit */ |
| 2174 | if (!(reg_read(xmit->ohci, xmit->ContextControlSet) & 0x8000)) { |
| 2175 | PRINT(KERN_ERR, "Error starting IT DMA (ContextControl 0x%08x)\n", |
| 2176 | reg_read(xmit->ohci, xmit->ContextControlSet)); |
| 2177 | return -1; |
| 2178 | } |
| 2179 | |
| 2180 | return 0; |
| 2181 | } |
| 2182 | |
| 2183 | static int ohci_isoctl(struct hpsb_iso *iso, enum isoctl_cmd cmd, unsigned long arg) |
| 2184 | { |
| 2185 | |
| 2186 | switch(cmd) { |
| 2187 | case XMIT_INIT: |
| 2188 | return ohci_iso_xmit_init(iso); |
| 2189 | case XMIT_START: |
| 2190 | return ohci_iso_xmit_start(iso, arg); |
| 2191 | case XMIT_STOP: |
| 2192 | ohci_iso_xmit_stop(iso); |
| 2193 | return 0; |
| 2194 | case XMIT_QUEUE: |
| 2195 | return ohci_iso_xmit_queue(iso, (struct hpsb_iso_packet_info*) arg); |
| 2196 | case XMIT_SHUTDOWN: |
| 2197 | ohci_iso_xmit_shutdown(iso); |
| 2198 | return 0; |
| 2199 | |
| 2200 | case RECV_INIT: |
| 2201 | return ohci_iso_recv_init(iso); |
| 2202 | case RECV_START: { |
| 2203 | int *args = (int*) arg; |
| 2204 | return ohci_iso_recv_start(iso, args[0], args[1], args[2]); |
| 2205 | } |
| 2206 | case RECV_STOP: |
| 2207 | ohci_iso_recv_stop(iso); |
| 2208 | return 0; |
| 2209 | case RECV_RELEASE: |
| 2210 | ohci_iso_recv_release(iso, (struct hpsb_iso_packet_info*) arg); |
| 2211 | return 0; |
| 2212 | case RECV_FLUSH: |
| 2213 | ohci_iso_recv_task((unsigned long) iso); |
| 2214 | return 0; |
| 2215 | case RECV_SHUTDOWN: |
| 2216 | ohci_iso_recv_shutdown(iso); |
| 2217 | return 0; |
| 2218 | case RECV_LISTEN_CHANNEL: |
| 2219 | ohci_iso_recv_change_channel(iso, arg, 1); |
| 2220 | return 0; |
| 2221 | case RECV_UNLISTEN_CHANNEL: |
| 2222 | ohci_iso_recv_change_channel(iso, arg, 0); |
| 2223 | return 0; |
| 2224 | case RECV_SET_CHANNEL_MASK: |
| 2225 | ohci_iso_recv_set_channel_mask(iso, *((u64*) arg)); |
| 2226 | return 0; |
| 2227 | |
| 2228 | default: |
| 2229 | PRINT_G(KERN_ERR, "ohci_isoctl cmd %d not implemented yet", |
| 2230 | cmd); |
| 2231 | break; |
| 2232 | } |
| 2233 | return -EINVAL; |
| 2234 | } |
| 2235 | |
| 2236 | /*************************************** |
| 2237 | * IEEE-1394 functionality section END * |
| 2238 | ***************************************/ |
| 2239 | |
| 2240 | |
| 2241 | /******************************************************** |
| 2242 | * Global stuff (interrupt handler, init/shutdown code) * |
| 2243 | ********************************************************/ |
| 2244 | |
| 2245 | static void dma_trm_reset(struct dma_trm_ctx *d) |
| 2246 | { |
| 2247 | unsigned long flags; |
| 2248 | LIST_HEAD(packet_list); |
| 2249 | struct ti_ohci *ohci = d->ohci; |
| 2250 | struct hpsb_packet *packet, *ptmp; |
| 2251 | |
| 2252 | ohci1394_stop_context(ohci, d->ctrlClear, NULL); |
| 2253 | |
| 2254 | /* Lock the context, reset it and release it. Move the packets |
| 2255 | * that were pending in the context to packet_list and free |
| 2256 | * them after releasing the lock. */ |
| 2257 | |
| 2258 | spin_lock_irqsave(&d->lock, flags); |
| 2259 | |
| 2260 | list_splice(&d->fifo_list, &packet_list); |
| 2261 | list_splice(&d->pending_list, &packet_list); |
| 2262 | INIT_LIST_HEAD(&d->fifo_list); |
| 2263 | INIT_LIST_HEAD(&d->pending_list); |
| 2264 | |
| 2265 | d->branchAddrPtr = NULL; |
| 2266 | d->sent_ind = d->prg_ind; |
| 2267 | d->free_prgs = d->num_desc; |
| 2268 | |
| 2269 | spin_unlock_irqrestore(&d->lock, flags); |
| 2270 | |
| 2271 | if (list_empty(&packet_list)) |
| 2272 | return; |
| 2273 | |
| 2274 | PRINT(KERN_INFO, "AT dma reset ctx=%d, aborting transmission", d->ctx); |
| 2275 | |
| 2276 | /* Now process subsystem callbacks for the packets from this |
| 2277 | * context. */ |
| 2278 | list_for_each_entry_safe(packet, ptmp, &packet_list, driver_list) { |
| 2279 | list_del_init(&packet->driver_list); |
| 2280 | hpsb_packet_sent(ohci->host, packet, ACKX_ABORTED); |
| 2281 | } |
| 2282 | } |
| 2283 | |
| 2284 | static void ohci_schedule_iso_tasklets(struct ti_ohci *ohci, |
| 2285 | quadlet_t rx_event, |
| 2286 | quadlet_t tx_event) |
| 2287 | { |
| 2288 | struct ohci1394_iso_tasklet *t; |
| 2289 | unsigned long mask; |
Andy Wingo | 4a9949d | 2005-10-19 21:23:46 -0700 | [diff] [blame] | 2290 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2291 | |
Andy Wingo | 4a9949d | 2005-10-19 21:23:46 -0700 | [diff] [blame] | 2292 | spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2293 | |
| 2294 | list_for_each_entry(t, &ohci->iso_tasklet_list, link) { |
| 2295 | mask = 1 << t->context; |
| 2296 | |
| 2297 | if (t->type == OHCI_ISO_TRANSMIT && tx_event & mask) |
| 2298 | tasklet_schedule(&t->tasklet); |
| 2299 | else if (rx_event & mask) |
| 2300 | tasklet_schedule(&t->tasklet); |
| 2301 | } |
| 2302 | |
Andy Wingo | 4a9949d | 2005-10-19 21:23:46 -0700 | [diff] [blame] | 2303 | spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2304 | } |
| 2305 | |
| 2306 | static irqreturn_t ohci_irq_handler(int irq, void *dev_id, |
| 2307 | struct pt_regs *regs_are_unused) |
| 2308 | { |
| 2309 | quadlet_t event, node_id; |
| 2310 | struct ti_ohci *ohci = (struct ti_ohci *)dev_id; |
| 2311 | struct hpsb_host *host = ohci->host; |
| 2312 | int phyid = -1, isroot = 0; |
| 2313 | unsigned long flags; |
| 2314 | |
| 2315 | /* Read and clear the interrupt event register. Don't clear |
| 2316 | * the busReset event, though. This is done when we get the |
| 2317 | * selfIDComplete interrupt. */ |
| 2318 | spin_lock_irqsave(&ohci->event_lock, flags); |
| 2319 | event = reg_read(ohci, OHCI1394_IntEventClear); |
| 2320 | reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset); |
| 2321 | spin_unlock_irqrestore(&ohci->event_lock, flags); |
| 2322 | |
| 2323 | if (!event) |
| 2324 | return IRQ_NONE; |
| 2325 | |
| 2326 | /* If event is ~(u32)0 cardbus card was ejected. In this case |
| 2327 | * we just return, and clean up in the ohci1394_pci_remove |
| 2328 | * function. */ |
| 2329 | if (event == ~(u32) 0) { |
| 2330 | DBGMSG("Device removed."); |
| 2331 | return IRQ_NONE; |
| 2332 | } |
| 2333 | |
| 2334 | DBGMSG("IntEvent: %08x", event); |
| 2335 | |
| 2336 | if (event & OHCI1394_unrecoverableError) { |
| 2337 | int ctx; |
| 2338 | PRINT(KERN_ERR, "Unrecoverable error!"); |
| 2339 | |
| 2340 | if (reg_read(ohci, OHCI1394_AsReqTrContextControlSet) & 0x800) |
| 2341 | PRINT(KERN_ERR, "Async Req Tx Context died: " |
| 2342 | "ctrl[%08x] cmdptr[%08x]", |
| 2343 | reg_read(ohci, OHCI1394_AsReqTrContextControlSet), |
| 2344 | reg_read(ohci, OHCI1394_AsReqTrCommandPtr)); |
| 2345 | |
| 2346 | if (reg_read(ohci, OHCI1394_AsRspTrContextControlSet) & 0x800) |
| 2347 | PRINT(KERN_ERR, "Async Rsp Tx Context died: " |
| 2348 | "ctrl[%08x] cmdptr[%08x]", |
| 2349 | reg_read(ohci, OHCI1394_AsRspTrContextControlSet), |
| 2350 | reg_read(ohci, OHCI1394_AsRspTrCommandPtr)); |
| 2351 | |
| 2352 | if (reg_read(ohci, OHCI1394_AsReqRcvContextControlSet) & 0x800) |
| 2353 | PRINT(KERN_ERR, "Async Req Rcv Context died: " |
| 2354 | "ctrl[%08x] cmdptr[%08x]", |
| 2355 | reg_read(ohci, OHCI1394_AsReqRcvContextControlSet), |
| 2356 | reg_read(ohci, OHCI1394_AsReqRcvCommandPtr)); |
| 2357 | |
| 2358 | if (reg_read(ohci, OHCI1394_AsRspRcvContextControlSet) & 0x800) |
| 2359 | PRINT(KERN_ERR, "Async Rsp Rcv Context died: " |
| 2360 | "ctrl[%08x] cmdptr[%08x]", |
| 2361 | reg_read(ohci, OHCI1394_AsRspRcvContextControlSet), |
| 2362 | reg_read(ohci, OHCI1394_AsRspRcvCommandPtr)); |
| 2363 | |
| 2364 | for (ctx = 0; ctx < ohci->nb_iso_xmit_ctx; ctx++) { |
| 2365 | if (reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)) & 0x800) |
| 2366 | PRINT(KERN_ERR, "Iso Xmit %d Context died: " |
| 2367 | "ctrl[%08x] cmdptr[%08x]", ctx, |
| 2368 | reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)), |
| 2369 | reg_read(ohci, OHCI1394_IsoXmitCommandPtr + (16 * ctx))); |
| 2370 | } |
| 2371 | |
| 2372 | for (ctx = 0; ctx < ohci->nb_iso_rcv_ctx; ctx++) { |
| 2373 | if (reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)) & 0x800) |
| 2374 | PRINT(KERN_ERR, "Iso Recv %d Context died: " |
| 2375 | "ctrl[%08x] cmdptr[%08x] match[%08x]", ctx, |
| 2376 | reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)), |
| 2377 | reg_read(ohci, OHCI1394_IsoRcvCommandPtr + (32 * ctx)), |
| 2378 | reg_read(ohci, OHCI1394_IsoRcvContextMatch + (32 * ctx))); |
| 2379 | } |
| 2380 | |
| 2381 | event &= ~OHCI1394_unrecoverableError; |
| 2382 | } |
Jody McIntyre | e2f8165 | 2006-03-28 19:55:11 -0500 | [diff] [blame] | 2383 | if (event & OHCI1394_postedWriteErr) { |
| 2384 | PRINT(KERN_ERR, "physical posted write error"); |
| 2385 | /* no recovery strategy yet, had to involve protocol drivers */ |
| 2386 | } |
Ben Collins | 57fdb58 | 2006-06-12 18:12:21 -0400 | [diff] [blame] | 2387 | if (event & OHCI1394_cycleTooLong) { |
| 2388 | if(printk_ratelimit()) |
| 2389 | PRINT(KERN_WARNING, "isochronous cycle too long"); |
| 2390 | else |
| 2391 | DBGMSG("OHCI1394_cycleTooLong"); |
| 2392 | reg_write(ohci, OHCI1394_LinkControlSet, |
| 2393 | OHCI1394_LinkControl_CycleMaster); |
| 2394 | event &= ~OHCI1394_cycleTooLong; |
| 2395 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2396 | if (event & OHCI1394_cycleInconsistent) { |
| 2397 | /* We subscribe to the cycleInconsistent event only to |
| 2398 | * clear the corresponding event bit... otherwise, |
| 2399 | * isochronous cycleMatch DMA won't work. */ |
| 2400 | DBGMSG("OHCI1394_cycleInconsistent"); |
| 2401 | event &= ~OHCI1394_cycleInconsistent; |
| 2402 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2403 | if (event & OHCI1394_busReset) { |
| 2404 | /* The busReset event bit can't be cleared during the |
| 2405 | * selfID phase, so we disable busReset interrupts, to |
| 2406 | * avoid burying the cpu in interrupt requests. */ |
| 2407 | spin_lock_irqsave(&ohci->event_lock, flags); |
| 2408 | reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); |
| 2409 | |
| 2410 | if (ohci->check_busreset) { |
| 2411 | int loop_count = 0; |
| 2412 | |
| 2413 | udelay(10); |
| 2414 | |
| 2415 | while (reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { |
| 2416 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
| 2417 | |
| 2418 | spin_unlock_irqrestore(&ohci->event_lock, flags); |
| 2419 | udelay(10); |
| 2420 | spin_lock_irqsave(&ohci->event_lock, flags); |
| 2421 | |
| 2422 | /* The loop counter check is to prevent the driver |
| 2423 | * from remaining in this state forever. For the |
| 2424 | * initial bus reset, the loop continues for ever |
| 2425 | * and the system hangs, until some device is plugged-in |
| 2426 | * or out manually into a port! The forced reset seems |
| 2427 | * to solve this problem. This mainly effects nForce2. */ |
| 2428 | if (loop_count > 10000) { |
| 2429 | ohci_devctl(host, RESET_BUS, LONG_RESET); |
| 2430 | DBGMSG("Detected bus-reset loop. Forced a bus reset!"); |
| 2431 | loop_count = 0; |
| 2432 | } |
| 2433 | |
| 2434 | loop_count++; |
| 2435 | } |
| 2436 | } |
| 2437 | spin_unlock_irqrestore(&ohci->event_lock, flags); |
| 2438 | if (!host->in_bus_reset) { |
| 2439 | DBGMSG("irq_handler: Bus reset requested"); |
| 2440 | |
| 2441 | /* Subsystem call */ |
| 2442 | hpsb_bus_reset(ohci->host); |
| 2443 | } |
| 2444 | event &= ~OHCI1394_busReset; |
| 2445 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2446 | if (event & OHCI1394_reqTxComplete) { |
| 2447 | struct dma_trm_ctx *d = &ohci->at_req_context; |
| 2448 | DBGMSG("Got reqTxComplete interrupt " |
| 2449 | "status=0x%08X", reg_read(ohci, d->ctrlSet)); |
| 2450 | if (reg_read(ohci, d->ctrlSet) & 0x800) |
| 2451 | ohci1394_stop_context(ohci, d->ctrlClear, |
| 2452 | "reqTxComplete"); |
| 2453 | else |
| 2454 | dma_trm_tasklet((unsigned long)d); |
| 2455 | //tasklet_schedule(&d->task); |
| 2456 | event &= ~OHCI1394_reqTxComplete; |
| 2457 | } |
| 2458 | if (event & OHCI1394_respTxComplete) { |
| 2459 | struct dma_trm_ctx *d = &ohci->at_resp_context; |
| 2460 | DBGMSG("Got respTxComplete interrupt " |
| 2461 | "status=0x%08X", reg_read(ohci, d->ctrlSet)); |
| 2462 | if (reg_read(ohci, d->ctrlSet) & 0x800) |
| 2463 | ohci1394_stop_context(ohci, d->ctrlClear, |
| 2464 | "respTxComplete"); |
| 2465 | else |
| 2466 | tasklet_schedule(&d->task); |
| 2467 | event &= ~OHCI1394_respTxComplete; |
| 2468 | } |
| 2469 | if (event & OHCI1394_RQPkt) { |
| 2470 | struct dma_rcv_ctx *d = &ohci->ar_req_context; |
| 2471 | DBGMSG("Got RQPkt interrupt status=0x%08X", |
| 2472 | reg_read(ohci, d->ctrlSet)); |
| 2473 | if (reg_read(ohci, d->ctrlSet) & 0x800) |
| 2474 | ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt"); |
| 2475 | else |
| 2476 | tasklet_schedule(&d->task); |
| 2477 | event &= ~OHCI1394_RQPkt; |
| 2478 | } |
| 2479 | if (event & OHCI1394_RSPkt) { |
| 2480 | struct dma_rcv_ctx *d = &ohci->ar_resp_context; |
| 2481 | DBGMSG("Got RSPkt interrupt status=0x%08X", |
| 2482 | reg_read(ohci, d->ctrlSet)); |
| 2483 | if (reg_read(ohci, d->ctrlSet) & 0x800) |
| 2484 | ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt"); |
| 2485 | else |
| 2486 | tasklet_schedule(&d->task); |
| 2487 | event &= ~OHCI1394_RSPkt; |
| 2488 | } |
| 2489 | if (event & OHCI1394_isochRx) { |
| 2490 | quadlet_t rx_event; |
| 2491 | |
| 2492 | rx_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet); |
| 2493 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, rx_event); |
| 2494 | ohci_schedule_iso_tasklets(ohci, rx_event, 0); |
| 2495 | event &= ~OHCI1394_isochRx; |
| 2496 | } |
| 2497 | if (event & OHCI1394_isochTx) { |
| 2498 | quadlet_t tx_event; |
| 2499 | |
| 2500 | tx_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet); |
| 2501 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, tx_event); |
| 2502 | ohci_schedule_iso_tasklets(ohci, 0, tx_event); |
| 2503 | event &= ~OHCI1394_isochTx; |
| 2504 | } |
| 2505 | if (event & OHCI1394_selfIDComplete) { |
| 2506 | if (host->in_bus_reset) { |
| 2507 | node_id = reg_read(ohci, OHCI1394_NodeID); |
| 2508 | |
| 2509 | if (!(node_id & 0x80000000)) { |
| 2510 | PRINT(KERN_ERR, |
| 2511 | "SelfID received, but NodeID invalid " |
| 2512 | "(probably new bus reset occurred): %08X", |
| 2513 | node_id); |
| 2514 | goto selfid_not_valid; |
| 2515 | } |
| 2516 | |
| 2517 | phyid = node_id & 0x0000003f; |
| 2518 | isroot = (node_id & 0x40000000) != 0; |
| 2519 | |
| 2520 | DBGMSG("SelfID interrupt received " |
| 2521 | "(phyid %d, %s)", phyid, |
| 2522 | (isroot ? "root" : "not root")); |
| 2523 | |
| 2524 | handle_selfid(ohci, host, phyid, isroot); |
| 2525 | |
| 2526 | /* Clear the bus reset event and re-enable the |
| 2527 | * busReset interrupt. */ |
| 2528 | spin_lock_irqsave(&ohci->event_lock, flags); |
| 2529 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
| 2530 | reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); |
| 2531 | spin_unlock_irqrestore(&ohci->event_lock, flags); |
| 2532 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2533 | /* Turn on phys dma reception. |
| 2534 | * |
| 2535 | * TODO: Enable some sort of filtering management. |
| 2536 | */ |
| 2537 | if (phys_dma) { |
Stefan Richter | 180a430 | 2006-03-28 19:57:34 -0500 | [diff] [blame] | 2538 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, |
| 2539 | 0xffffffff); |
| 2540 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, |
| 2541 | 0xffffffff); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2542 | } |
| 2543 | |
| 2544 | DBGMSG("PhyReqFilter=%08x%08x", |
Stefan Richter | 180a430 | 2006-03-28 19:57:34 -0500 | [diff] [blame] | 2545 | reg_read(ohci, OHCI1394_PhyReqFilterHiSet), |
| 2546 | reg_read(ohci, OHCI1394_PhyReqFilterLoSet)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2547 | |
| 2548 | hpsb_selfid_complete(host, phyid, isroot); |
| 2549 | } else |
| 2550 | PRINT(KERN_ERR, |
| 2551 | "SelfID received outside of bus reset sequence"); |
| 2552 | |
| 2553 | selfid_not_valid: |
| 2554 | event &= ~OHCI1394_selfIDComplete; |
| 2555 | } |
| 2556 | |
| 2557 | /* Make sure we handle everything, just in case we accidentally |
| 2558 | * enabled an interrupt that we didn't write a handler for. */ |
| 2559 | if (event) |
| 2560 | PRINT(KERN_ERR, "Unhandled interrupt(s) 0x%08x", |
| 2561 | event); |
| 2562 | |
| 2563 | return IRQ_HANDLED; |
| 2564 | } |
| 2565 | |
| 2566 | /* Put the buffer back into the dma context */ |
| 2567 | static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx) |
| 2568 | { |
| 2569 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); |
| 2570 | DBGMSG("Inserting dma buf ctx=%d idx=%d", d->ctx, idx); |
| 2571 | |
| 2572 | d->prg_cpu[idx]->status = cpu_to_le32(d->buf_size); |
| 2573 | d->prg_cpu[idx]->branchAddress &= le32_to_cpu(0xfffffff0); |
| 2574 | idx = (idx + d->num_desc - 1 ) % d->num_desc; |
| 2575 | d->prg_cpu[idx]->branchAddress |= le32_to_cpu(0x00000001); |
| 2576 | |
| 2577 | /* To avoid a race, ensure 1394 interface hardware sees the inserted |
| 2578 | * context program descriptors before it sees the wakeup bit set. */ |
| 2579 | wmb(); |
| 2580 | |
| 2581 | /* wake up the dma context if necessary */ |
| 2582 | if (!(reg_read(ohci, d->ctrlSet) & 0x400)) { |
| 2583 | PRINT(KERN_INFO, |
| 2584 | "Waking dma ctx=%d ... processing is probably too slow", |
| 2585 | d->ctx); |
| 2586 | } |
| 2587 | |
| 2588 | /* do this always, to avoid race condition */ |
| 2589 | reg_write(ohci, d->ctrlSet, 0x1000); |
| 2590 | } |
| 2591 | |
| 2592 | #define cond_le32_to_cpu(data, noswap) \ |
| 2593 | (noswap ? data : le32_to_cpu(data)) |
| 2594 | |
| 2595 | static const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0, |
| 2596 | -1, 0, -1, 0, -1, -1, 16, -1}; |
| 2597 | |
| 2598 | /* |
| 2599 | * Determine the length of a packet in the buffer |
| 2600 | * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca> |
| 2601 | */ |
| 2602 | static __inline__ int packet_length(struct dma_rcv_ctx *d, int idx, quadlet_t *buf_ptr, |
| 2603 | int offset, unsigned char tcode, int noswap) |
| 2604 | { |
| 2605 | int length = -1; |
| 2606 | |
| 2607 | if (d->type == DMA_CTX_ASYNC_REQ || d->type == DMA_CTX_ASYNC_RESP) { |
| 2608 | length = TCODE_SIZE[tcode]; |
| 2609 | if (length == 0) { |
| 2610 | if (offset + 12 >= d->buf_size) { |
| 2611 | length = (cond_le32_to_cpu(d->buf_cpu[(idx + 1) % d->num_desc] |
| 2612 | [3 - ((d->buf_size - offset) >> 2)], noswap) >> 16); |
| 2613 | } else { |
| 2614 | length = (cond_le32_to_cpu(buf_ptr[3], noswap) >> 16); |
| 2615 | } |
| 2616 | length += 20; |
| 2617 | } |
| 2618 | } else if (d->type == DMA_CTX_ISO) { |
| 2619 | /* Assumption: buffer fill mode with header/trailer */ |
| 2620 | length = (cond_le32_to_cpu(buf_ptr[0], noswap) >> 16) + 8; |
| 2621 | } |
| 2622 | |
| 2623 | if (length > 0 && length % 4) |
| 2624 | length += 4 - (length % 4); |
| 2625 | |
| 2626 | return length; |
| 2627 | } |
| 2628 | |
| 2629 | /* Tasklet that processes dma receive buffers */ |
| 2630 | static void dma_rcv_tasklet (unsigned long data) |
| 2631 | { |
| 2632 | struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data; |
| 2633 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); |
| 2634 | unsigned int split_left, idx, offset, rescount; |
| 2635 | unsigned char tcode; |
| 2636 | int length, bytes_left, ack; |
| 2637 | unsigned long flags; |
| 2638 | quadlet_t *buf_ptr; |
| 2639 | char *split_ptr; |
| 2640 | char msg[256]; |
| 2641 | |
| 2642 | spin_lock_irqsave(&d->lock, flags); |
| 2643 | |
| 2644 | idx = d->buf_ind; |
| 2645 | offset = d->buf_offset; |
| 2646 | buf_ptr = d->buf_cpu[idx] + offset/4; |
| 2647 | |
| 2648 | rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff; |
| 2649 | bytes_left = d->buf_size - rescount - offset; |
| 2650 | |
| 2651 | while (bytes_left > 0) { |
| 2652 | tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming) >> 4) & 0xf; |
| 2653 | |
| 2654 | /* packet_length() will return < 4 for an error */ |
| 2655 | length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->no_swap_incoming); |
| 2656 | |
| 2657 | if (length < 4) { /* something is wrong */ |
| 2658 | sprintf(msg,"Unexpected tcode 0x%x(0x%08x) in AR ctx=%d, length=%d", |
| 2659 | tcode, cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming), |
| 2660 | d->ctx, length); |
| 2661 | ohci1394_stop_context(ohci, d->ctrlClear, msg); |
| 2662 | spin_unlock_irqrestore(&d->lock, flags); |
| 2663 | return; |
| 2664 | } |
| 2665 | |
| 2666 | /* The first case is where we have a packet that crosses |
| 2667 | * over more than one descriptor. The next case is where |
| 2668 | * it's all in the first descriptor. */ |
| 2669 | if ((offset + length) > d->buf_size) { |
| 2670 | DBGMSG("Split packet rcv'd"); |
| 2671 | if (length > d->split_buf_size) { |
| 2672 | ohci1394_stop_context(ohci, d->ctrlClear, |
| 2673 | "Split packet size exceeded"); |
| 2674 | d->buf_ind = idx; |
| 2675 | d->buf_offset = offset; |
| 2676 | spin_unlock_irqrestore(&d->lock, flags); |
| 2677 | return; |
| 2678 | } |
| 2679 | |
| 2680 | if (le32_to_cpu(d->prg_cpu[(idx+1)%d->num_desc]->status) |
| 2681 | == d->buf_size) { |
| 2682 | /* Other part of packet not written yet. |
| 2683 | * this should never happen I think |
| 2684 | * anyway we'll get it on the next call. */ |
| 2685 | PRINT(KERN_INFO, |
| 2686 | "Got only half a packet!"); |
| 2687 | d->buf_ind = idx; |
| 2688 | d->buf_offset = offset; |
| 2689 | spin_unlock_irqrestore(&d->lock, flags); |
| 2690 | return; |
| 2691 | } |
| 2692 | |
| 2693 | split_left = length; |
| 2694 | split_ptr = (char *)d->spb; |
| 2695 | memcpy(split_ptr,buf_ptr,d->buf_size-offset); |
| 2696 | split_left -= d->buf_size-offset; |
| 2697 | split_ptr += d->buf_size-offset; |
| 2698 | insert_dma_buffer(d, idx); |
| 2699 | idx = (idx+1) % d->num_desc; |
| 2700 | buf_ptr = d->buf_cpu[idx]; |
| 2701 | offset=0; |
| 2702 | |
| 2703 | while (split_left >= d->buf_size) { |
| 2704 | memcpy(split_ptr,buf_ptr,d->buf_size); |
| 2705 | split_ptr += d->buf_size; |
| 2706 | split_left -= d->buf_size; |
| 2707 | insert_dma_buffer(d, idx); |
| 2708 | idx = (idx+1) % d->num_desc; |
| 2709 | buf_ptr = d->buf_cpu[idx]; |
| 2710 | } |
| 2711 | |
| 2712 | if (split_left > 0) { |
| 2713 | memcpy(split_ptr, buf_ptr, split_left); |
| 2714 | offset = split_left; |
| 2715 | buf_ptr += offset/4; |
| 2716 | } |
| 2717 | } else { |
| 2718 | DBGMSG("Single packet rcv'd"); |
| 2719 | memcpy(d->spb, buf_ptr, length); |
| 2720 | offset += length; |
| 2721 | buf_ptr += length/4; |
| 2722 | if (offset==d->buf_size) { |
| 2723 | insert_dma_buffer(d, idx); |
| 2724 | idx = (idx+1) % d->num_desc; |
| 2725 | buf_ptr = d->buf_cpu[idx]; |
| 2726 | offset=0; |
| 2727 | } |
| 2728 | } |
| 2729 | |
| 2730 | /* We get one phy packet to the async descriptor for each |
| 2731 | * bus reset. We always ignore it. */ |
| 2732 | if (tcode != OHCI1394_TCODE_PHY) { |
| 2733 | if (!ohci->no_swap_incoming) |
| 2734 | packet_swab(d->spb, tcode); |
| 2735 | DBGMSG("Packet received from node" |
| 2736 | " %d ack=0x%02X spd=%d tcode=0x%X" |
| 2737 | " length=%d ctx=%d tlabel=%d", |
| 2738 | (d->spb[1]>>16)&0x3f, |
| 2739 | (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f, |
| 2740 | (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>21)&0x3, |
| 2741 | tcode, length, d->ctx, |
Jody McIntyre | dfe547a | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 2742 | (cond_le32_to_cpu(d->spb[0], ohci->no_swap_incoming)>>10)&0x3f); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2743 | |
| 2744 | ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f) |
| 2745 | == 0x11) ? 1 : 0; |
| 2746 | |
| 2747 | hpsb_packet_received(ohci->host, d->spb, |
| 2748 | length-4, ack); |
| 2749 | } |
| 2750 | #ifdef OHCI1394_DEBUG |
| 2751 | else |
| 2752 | PRINT (KERN_DEBUG, "Got phy packet ctx=%d ... discarded", |
| 2753 | d->ctx); |
| 2754 | #endif |
| 2755 | |
| 2756 | rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff; |
| 2757 | |
| 2758 | bytes_left = d->buf_size - rescount - offset; |
| 2759 | |
| 2760 | } |
| 2761 | |
| 2762 | d->buf_ind = idx; |
| 2763 | d->buf_offset = offset; |
| 2764 | |
| 2765 | spin_unlock_irqrestore(&d->lock, flags); |
| 2766 | } |
| 2767 | |
| 2768 | /* Bottom half that processes sent packets */ |
| 2769 | static void dma_trm_tasklet (unsigned long data) |
| 2770 | { |
| 2771 | struct dma_trm_ctx *d = (struct dma_trm_ctx*)data; |
| 2772 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); |
| 2773 | struct hpsb_packet *packet, *ptmp; |
| 2774 | unsigned long flags; |
| 2775 | u32 status, ack; |
| 2776 | size_t datasize; |
| 2777 | |
| 2778 | spin_lock_irqsave(&d->lock, flags); |
| 2779 | |
| 2780 | list_for_each_entry_safe(packet, ptmp, &d->fifo_list, driver_list) { |
| 2781 | datasize = packet->data_size; |
| 2782 | if (datasize && packet->type != hpsb_raw) |
| 2783 | status = le32_to_cpu( |
| 2784 | d->prg_cpu[d->sent_ind]->end.status) >> 16; |
| 2785 | else |
| 2786 | status = le32_to_cpu( |
| 2787 | d->prg_cpu[d->sent_ind]->begin.status) >> 16; |
| 2788 | |
| 2789 | if (status == 0) |
| 2790 | /* this packet hasn't been sent yet*/ |
| 2791 | break; |
| 2792 | |
| 2793 | #ifdef OHCI1394_DEBUG |
| 2794 | if (datasize) |
| 2795 | if (((le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf) == 0xa) |
| 2796 | DBGMSG("Stream packet sent to channel %d tcode=0x%X " |
| 2797 | "ack=0x%X spd=%d dataLength=%d ctx=%d", |
| 2798 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>8)&0x3f, |
| 2799 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf, |
| 2800 | status&0x1f, (status>>5)&0x3, |
| 2801 | le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16, |
| 2802 | d->ctx); |
| 2803 | else |
| 2804 | DBGMSG("Packet sent to node %d tcode=0x%X tLabel=" |
Jody McIntyre | dfe547a | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 2805 | "%d ack=0x%X spd=%d dataLength=%d ctx=%d", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2806 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16)&0x3f, |
| 2807 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf, |
| 2808 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>10)&0x3f, |
| 2809 | status&0x1f, (status>>5)&0x3, |
| 2810 | le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3])>>16, |
| 2811 | d->ctx); |
| 2812 | else |
| 2813 | DBGMSG("Packet sent to node %d tcode=0x%X tLabel=" |
Jody McIntyre | dfe547a | 2005-04-21 14:09:42 -0700 | [diff] [blame] | 2814 | "%d ack=0x%X spd=%d data=0x%08X ctx=%d", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2815 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1]) |
| 2816 | >>16)&0x3f, |
| 2817 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0]) |
| 2818 | >>4)&0xf, |
| 2819 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0]) |
| 2820 | >>10)&0x3f, |
| 2821 | status&0x1f, (status>>5)&0x3, |
| 2822 | le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3]), |
| 2823 | d->ctx); |
| 2824 | #endif |
| 2825 | |
| 2826 | if (status & 0x10) { |
| 2827 | ack = status & 0xf; |
| 2828 | } else { |
| 2829 | switch (status & 0x1f) { |
| 2830 | case EVT_NO_STATUS: /* that should never happen */ |
| 2831 | case EVT_RESERVED_A: /* that should never happen */ |
| 2832 | case EVT_LONG_PACKET: /* that should never happen */ |
| 2833 | PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f); |
| 2834 | ack = ACKX_SEND_ERROR; |
| 2835 | break; |
| 2836 | case EVT_MISSING_ACK: |
| 2837 | ack = ACKX_TIMEOUT; |
| 2838 | break; |
| 2839 | case EVT_UNDERRUN: |
| 2840 | ack = ACKX_SEND_ERROR; |
| 2841 | break; |
| 2842 | case EVT_OVERRUN: /* that should never happen */ |
| 2843 | PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f); |
| 2844 | ack = ACKX_SEND_ERROR; |
| 2845 | break; |
| 2846 | case EVT_DESCRIPTOR_READ: |
| 2847 | case EVT_DATA_READ: |
| 2848 | case EVT_DATA_WRITE: |
| 2849 | ack = ACKX_SEND_ERROR; |
| 2850 | break; |
| 2851 | case EVT_BUS_RESET: /* that should never happen */ |
| 2852 | PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f); |
| 2853 | ack = ACKX_SEND_ERROR; |
| 2854 | break; |
| 2855 | case EVT_TIMEOUT: |
| 2856 | ack = ACKX_TIMEOUT; |
| 2857 | break; |
| 2858 | case EVT_TCODE_ERR: |
| 2859 | ack = ACKX_SEND_ERROR; |
| 2860 | break; |
| 2861 | case EVT_RESERVED_B: /* that should never happen */ |
| 2862 | case EVT_RESERVED_C: /* that should never happen */ |
| 2863 | PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f); |
| 2864 | ack = ACKX_SEND_ERROR; |
| 2865 | break; |
| 2866 | case EVT_UNKNOWN: |
| 2867 | case EVT_FLUSHED: |
| 2868 | ack = ACKX_SEND_ERROR; |
| 2869 | break; |
| 2870 | default: |
| 2871 | PRINT(KERN_ERR, "Unhandled OHCI evt_* error 0x%x", status & 0x1f); |
| 2872 | ack = ACKX_SEND_ERROR; |
| 2873 | BUG(); |
| 2874 | } |
| 2875 | } |
| 2876 | |
| 2877 | list_del_init(&packet->driver_list); |
| 2878 | hpsb_packet_sent(ohci->host, packet, ack); |
| 2879 | |
| 2880 | if (datasize) { |
| 2881 | pci_unmap_single(ohci->dev, |
| 2882 | cpu_to_le32(d->prg_cpu[d->sent_ind]->end.address), |
| 2883 | datasize, PCI_DMA_TODEVICE); |
| 2884 | OHCI_DMA_FREE("single Xmit data packet"); |
| 2885 | } |
| 2886 | |
| 2887 | d->sent_ind = (d->sent_ind+1)%d->num_desc; |
| 2888 | d->free_prgs++; |
| 2889 | } |
| 2890 | |
| 2891 | dma_trm_flush(ohci, d); |
| 2892 | |
| 2893 | spin_unlock_irqrestore(&d->lock, flags); |
| 2894 | } |
| 2895 | |
| 2896 | static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d) |
| 2897 | { |
| 2898 | if (d->ctrlClear) { |
| 2899 | ohci1394_stop_context(d->ohci, d->ctrlClear, NULL); |
| 2900 | |
| 2901 | if (d->type == DMA_CTX_ISO) { |
| 2902 | /* disable interrupts */ |
| 2903 | reg_write(d->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << d->ctx); |
| 2904 | ohci1394_unregister_iso_tasklet(d->ohci, &d->ohci->ir_legacy_tasklet); |
| 2905 | } else { |
| 2906 | tasklet_kill(&d->task); |
| 2907 | } |
| 2908 | } |
| 2909 | } |
| 2910 | |
| 2911 | |
| 2912 | static void free_dma_rcv_ctx(struct dma_rcv_ctx *d) |
| 2913 | { |
| 2914 | int i; |
| 2915 | struct ti_ohci *ohci = d->ohci; |
| 2916 | |
| 2917 | if (ohci == NULL) |
| 2918 | return; |
| 2919 | |
| 2920 | DBGMSG("Freeing dma_rcv_ctx %d", d->ctx); |
| 2921 | |
| 2922 | if (d->buf_cpu) { |
| 2923 | for (i=0; i<d->num_desc; i++) |
| 2924 | if (d->buf_cpu[i] && d->buf_bus[i]) { |
| 2925 | pci_free_consistent( |
| 2926 | ohci->dev, d->buf_size, |
| 2927 | d->buf_cpu[i], d->buf_bus[i]); |
| 2928 | OHCI_DMA_FREE("consistent dma_rcv buf[%d]", i); |
| 2929 | } |
| 2930 | kfree(d->buf_cpu); |
| 2931 | kfree(d->buf_bus); |
| 2932 | } |
| 2933 | if (d->prg_cpu) { |
| 2934 | for (i=0; i<d->num_desc; i++) |
| 2935 | if (d->prg_cpu[i] && d->prg_bus[i]) { |
| 2936 | pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]); |
| 2937 | OHCI_DMA_FREE("consistent dma_rcv prg[%d]", i); |
| 2938 | } |
| 2939 | pci_pool_destroy(d->prg_pool); |
| 2940 | OHCI_DMA_FREE("dma_rcv prg pool"); |
| 2941 | kfree(d->prg_cpu); |
| 2942 | kfree(d->prg_bus); |
| 2943 | } |
Jody McIntyre | 616b859 | 2005-05-16 21:54:01 -0700 | [diff] [blame] | 2944 | kfree(d->spb); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2945 | |
| 2946 | /* Mark this context as freed. */ |
| 2947 | d->ohci = NULL; |
| 2948 | } |
| 2949 | |
| 2950 | static int |
| 2951 | alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d, |
| 2952 | enum context_type type, int ctx, int num_desc, |
| 2953 | int buf_size, int split_buf_size, int context_base) |
| 2954 | { |
| 2955 | int i, len; |
| 2956 | static int num_allocs; |
| 2957 | static char pool_name[20]; |
| 2958 | |
| 2959 | d->ohci = ohci; |
| 2960 | d->type = type; |
| 2961 | d->ctx = ctx; |
| 2962 | |
| 2963 | d->num_desc = num_desc; |
| 2964 | d->buf_size = buf_size; |
| 2965 | d->split_buf_size = split_buf_size; |
| 2966 | |
| 2967 | d->ctrlSet = 0; |
| 2968 | d->ctrlClear = 0; |
| 2969 | d->cmdPtr = 0; |
| 2970 | |
Stefan Richter | 8551158 | 2005-11-07 06:31:45 -0500 | [diff] [blame] | 2971 | d->buf_cpu = kzalloc(d->num_desc * sizeof(*d->buf_cpu), GFP_ATOMIC); |
| 2972 | d->buf_bus = kzalloc(d->num_desc * sizeof(*d->buf_bus), GFP_ATOMIC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2973 | |
| 2974 | if (d->buf_cpu == NULL || d->buf_bus == NULL) { |
| 2975 | PRINT(KERN_ERR, "Failed to allocate dma buffer"); |
| 2976 | free_dma_rcv_ctx(d); |
| 2977 | return -ENOMEM; |
| 2978 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2979 | |
Stefan Richter | 8551158 | 2005-11-07 06:31:45 -0500 | [diff] [blame] | 2980 | d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_ATOMIC); |
| 2981 | d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_ATOMIC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2982 | |
| 2983 | if (d->prg_cpu == NULL || d->prg_bus == NULL) { |
| 2984 | PRINT(KERN_ERR, "Failed to allocate dma prg"); |
| 2985 | free_dma_rcv_ctx(d); |
| 2986 | return -ENOMEM; |
| 2987 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2988 | |
| 2989 | d->spb = kmalloc(d->split_buf_size, GFP_ATOMIC); |
| 2990 | |
| 2991 | if (d->spb == NULL) { |
| 2992 | PRINT(KERN_ERR, "Failed to allocate split buffer"); |
| 2993 | free_dma_rcv_ctx(d); |
| 2994 | return -ENOMEM; |
| 2995 | } |
| 2996 | |
| 2997 | len = sprintf(pool_name, "ohci1394_rcv_prg"); |
| 2998 | sprintf(pool_name+len, "%d", num_allocs); |
| 2999 | d->prg_pool = pci_pool_create(pool_name, ohci->dev, |
| 3000 | sizeof(struct dma_cmd), 4, 0); |
| 3001 | if(d->prg_pool == NULL) |
| 3002 | { |
| 3003 | PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name); |
| 3004 | free_dma_rcv_ctx(d); |
| 3005 | return -ENOMEM; |
| 3006 | } |
| 3007 | num_allocs++; |
| 3008 | |
| 3009 | OHCI_DMA_ALLOC("dma_rcv prg pool"); |
| 3010 | |
| 3011 | for (i=0; i<d->num_desc; i++) { |
| 3012 | d->buf_cpu[i] = pci_alloc_consistent(ohci->dev, |
| 3013 | d->buf_size, |
| 3014 | d->buf_bus+i); |
| 3015 | OHCI_DMA_ALLOC("consistent dma_rcv buf[%d]", i); |
| 3016 | |
| 3017 | if (d->buf_cpu[i] != NULL) { |
| 3018 | memset(d->buf_cpu[i], 0, d->buf_size); |
| 3019 | } else { |
| 3020 | PRINT(KERN_ERR, |
| 3021 | "Failed to allocate dma buffer"); |
| 3022 | free_dma_rcv_ctx(d); |
| 3023 | return -ENOMEM; |
| 3024 | } |
| 3025 | |
| 3026 | d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i); |
| 3027 | OHCI_DMA_ALLOC("pool dma_rcv prg[%d]", i); |
| 3028 | |
| 3029 | if (d->prg_cpu[i] != NULL) { |
| 3030 | memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd)); |
| 3031 | } else { |
| 3032 | PRINT(KERN_ERR, |
| 3033 | "Failed to allocate dma prg"); |
| 3034 | free_dma_rcv_ctx(d); |
| 3035 | return -ENOMEM; |
| 3036 | } |
| 3037 | } |
| 3038 | |
| 3039 | spin_lock_init(&d->lock); |
| 3040 | |
| 3041 | if (type == DMA_CTX_ISO) { |
| 3042 | ohci1394_init_iso_tasklet(&ohci->ir_legacy_tasklet, |
| 3043 | OHCI_ISO_MULTICHANNEL_RECEIVE, |
| 3044 | dma_rcv_tasklet, (unsigned long) d); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3045 | } else { |
| 3046 | d->ctrlSet = context_base + OHCI1394_ContextControlSet; |
| 3047 | d->ctrlClear = context_base + OHCI1394_ContextControlClear; |
| 3048 | d->cmdPtr = context_base + OHCI1394_ContextCommandPtr; |
| 3049 | |
| 3050 | tasklet_init (&d->task, dma_rcv_tasklet, (unsigned long) d); |
| 3051 | } |
| 3052 | |
| 3053 | return 0; |
| 3054 | } |
| 3055 | |
| 3056 | static void free_dma_trm_ctx(struct dma_trm_ctx *d) |
| 3057 | { |
| 3058 | int i; |
| 3059 | struct ti_ohci *ohci = d->ohci; |
| 3060 | |
| 3061 | if (ohci == NULL) |
| 3062 | return; |
| 3063 | |
| 3064 | DBGMSG("Freeing dma_trm_ctx %d", d->ctx); |
| 3065 | |
| 3066 | if (d->prg_cpu) { |
| 3067 | for (i=0; i<d->num_desc; i++) |
| 3068 | if (d->prg_cpu[i] && d->prg_bus[i]) { |
| 3069 | pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]); |
| 3070 | OHCI_DMA_FREE("pool dma_trm prg[%d]", i); |
| 3071 | } |
| 3072 | pci_pool_destroy(d->prg_pool); |
| 3073 | OHCI_DMA_FREE("dma_trm prg pool"); |
| 3074 | kfree(d->prg_cpu); |
| 3075 | kfree(d->prg_bus); |
| 3076 | } |
| 3077 | |
| 3078 | /* Mark this context as freed. */ |
| 3079 | d->ohci = NULL; |
| 3080 | } |
| 3081 | |
| 3082 | static int |
| 3083 | alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d, |
| 3084 | enum context_type type, int ctx, int num_desc, |
| 3085 | int context_base) |
| 3086 | { |
| 3087 | int i, len; |
| 3088 | static char pool_name[20]; |
| 3089 | static int num_allocs=0; |
| 3090 | |
| 3091 | d->ohci = ohci; |
| 3092 | d->type = type; |
| 3093 | d->ctx = ctx; |
| 3094 | d->num_desc = num_desc; |
| 3095 | d->ctrlSet = 0; |
| 3096 | d->ctrlClear = 0; |
| 3097 | d->cmdPtr = 0; |
| 3098 | |
Stefan Richter | 8551158 | 2005-11-07 06:31:45 -0500 | [diff] [blame] | 3099 | d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_KERNEL); |
| 3100 | d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3101 | |
| 3102 | if (d->prg_cpu == NULL || d->prg_bus == NULL) { |
| 3103 | PRINT(KERN_ERR, "Failed to allocate at dma prg"); |
| 3104 | free_dma_trm_ctx(d); |
| 3105 | return -ENOMEM; |
| 3106 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3107 | |
| 3108 | len = sprintf(pool_name, "ohci1394_trm_prg"); |
| 3109 | sprintf(pool_name+len, "%d", num_allocs); |
| 3110 | d->prg_pool = pci_pool_create(pool_name, ohci->dev, |
| 3111 | sizeof(struct at_dma_prg), 4, 0); |
| 3112 | if (d->prg_pool == NULL) { |
| 3113 | PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name); |
| 3114 | free_dma_trm_ctx(d); |
| 3115 | return -ENOMEM; |
| 3116 | } |
| 3117 | num_allocs++; |
| 3118 | |
| 3119 | OHCI_DMA_ALLOC("dma_rcv prg pool"); |
| 3120 | |
| 3121 | for (i = 0; i < d->num_desc; i++) { |
| 3122 | d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i); |
| 3123 | OHCI_DMA_ALLOC("pool dma_trm prg[%d]", i); |
| 3124 | |
| 3125 | if (d->prg_cpu[i] != NULL) { |
| 3126 | memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg)); |
| 3127 | } else { |
| 3128 | PRINT(KERN_ERR, |
| 3129 | "Failed to allocate at dma prg"); |
| 3130 | free_dma_trm_ctx(d); |
| 3131 | return -ENOMEM; |
| 3132 | } |
| 3133 | } |
| 3134 | |
| 3135 | spin_lock_init(&d->lock); |
| 3136 | |
| 3137 | /* initialize tasklet */ |
| 3138 | if (type == DMA_CTX_ISO) { |
| 3139 | ohci1394_init_iso_tasklet(&ohci->it_legacy_tasklet, OHCI_ISO_TRANSMIT, |
| 3140 | dma_trm_tasklet, (unsigned long) d); |
| 3141 | if (ohci1394_register_iso_tasklet(ohci, |
| 3142 | &ohci->it_legacy_tasklet) < 0) { |
| 3143 | PRINT(KERN_ERR, "No IT DMA context available"); |
| 3144 | free_dma_trm_ctx(d); |
| 3145 | return -EBUSY; |
| 3146 | } |
| 3147 | |
| 3148 | /* IT can be assigned to any context by register_iso_tasklet */ |
| 3149 | d->ctx = ohci->it_legacy_tasklet.context; |
| 3150 | d->ctrlSet = OHCI1394_IsoXmitContextControlSet + 16 * d->ctx; |
| 3151 | d->ctrlClear = OHCI1394_IsoXmitContextControlClear + 16 * d->ctx; |
| 3152 | d->cmdPtr = OHCI1394_IsoXmitCommandPtr + 16 * d->ctx; |
| 3153 | } else { |
| 3154 | d->ctrlSet = context_base + OHCI1394_ContextControlSet; |
| 3155 | d->ctrlClear = context_base + OHCI1394_ContextControlClear; |
| 3156 | d->cmdPtr = context_base + OHCI1394_ContextCommandPtr; |
| 3157 | tasklet_init (&d->task, dma_trm_tasklet, (unsigned long)d); |
| 3158 | } |
| 3159 | |
| 3160 | return 0; |
| 3161 | } |
| 3162 | |
| 3163 | static void ohci_set_hw_config_rom(struct hpsb_host *host, quadlet_t *config_rom) |
| 3164 | { |
| 3165 | struct ti_ohci *ohci = host->hostdata; |
| 3166 | |
| 3167 | reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(config_rom[0])); |
| 3168 | reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(config_rom[2])); |
| 3169 | |
| 3170 | memcpy(ohci->csr_config_rom_cpu, config_rom, OHCI_CONFIG_ROM_LEN); |
| 3171 | } |
| 3172 | |
| 3173 | |
| 3174 | static quadlet_t ohci_hw_csr_reg(struct hpsb_host *host, int reg, |
| 3175 | quadlet_t data, quadlet_t compare) |
| 3176 | { |
| 3177 | struct ti_ohci *ohci = host->hostdata; |
| 3178 | int i; |
| 3179 | |
| 3180 | reg_write(ohci, OHCI1394_CSRData, data); |
| 3181 | reg_write(ohci, OHCI1394_CSRCompareData, compare); |
| 3182 | reg_write(ohci, OHCI1394_CSRControl, reg & 0x3); |
| 3183 | |
| 3184 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { |
| 3185 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) |
| 3186 | break; |
| 3187 | |
| 3188 | mdelay(1); |
| 3189 | } |
| 3190 | |
| 3191 | return reg_read(ohci, OHCI1394_CSRData); |
| 3192 | } |
| 3193 | |
| 3194 | static struct hpsb_host_driver ohci1394_driver = { |
| 3195 | .owner = THIS_MODULE, |
| 3196 | .name = OHCI1394_DRIVER_NAME, |
| 3197 | .set_hw_config_rom = ohci_set_hw_config_rom, |
| 3198 | .transmit_packet = ohci_transmit, |
| 3199 | .devctl = ohci_devctl, |
| 3200 | .isoctl = ohci_isoctl, |
| 3201 | .hw_csr_reg = ohci_hw_csr_reg, |
| 3202 | }; |
| 3203 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3204 | /*********************************** |
| 3205 | * PCI Driver Interface functions * |
| 3206 | ***********************************/ |
| 3207 | |
| 3208 | #define FAIL(err, fmt, args...) \ |
| 3209 | do { \ |
| 3210 | PRINT_G(KERN_ERR, fmt , ## args); \ |
| 3211 | ohci1394_pci_remove(dev); \ |
| 3212 | return err; \ |
| 3213 | } while (0) |
| 3214 | |
| 3215 | static int __devinit ohci1394_pci_probe(struct pci_dev *dev, |
| 3216 | const struct pci_device_id *ent) |
| 3217 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3218 | struct hpsb_host *host; |
| 3219 | struct ti_ohci *ohci; /* shortcut to currently handled device */ |
Greg Kroah-Hartman | 2427ddd | 2006-06-12 17:07:52 -0700 | [diff] [blame] | 3220 | resource_size_t ohci_base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3221 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3222 | if (pci_enable_device(dev)) |
| 3223 | FAIL(-ENXIO, "Failed to enable OHCI hardware"); |
| 3224 | pci_set_master(dev); |
| 3225 | |
| 3226 | host = hpsb_alloc_host(&ohci1394_driver, sizeof(struct ti_ohci), &dev->dev); |
| 3227 | if (!host) FAIL(-ENOMEM, "Failed to allocate host structure"); |
| 3228 | |
| 3229 | ohci = host->hostdata; |
| 3230 | ohci->dev = dev; |
| 3231 | ohci->host = host; |
| 3232 | ohci->init_state = OHCI_INIT_ALLOC_HOST; |
| 3233 | host->pdev = dev; |
| 3234 | pci_set_drvdata(dev, ohci); |
| 3235 | |
| 3236 | /* We don't want hardware swapping */ |
| 3237 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); |
| 3238 | |
| 3239 | /* Some oddball Apple controllers do not order the selfid |
| 3240 | * properly, so we make up for it here. */ |
| 3241 | #ifndef __LITTLE_ENDIAN |
| 3242 | /* XXX: Need a better way to check this. I'm wondering if we can |
| 3243 | * read the values of the OHCI1394_PCI_HCI_Control and the |
| 3244 | * noByteSwapData registers to see if they were not cleared to |
| 3245 | * zero. Should this work? Obviously it's not defined what these |
| 3246 | * registers will read when they aren't supported. Bleh! */ |
| 3247 | if (dev->vendor == PCI_VENDOR_ID_APPLE && |
| 3248 | dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) { |
| 3249 | ohci->no_swap_incoming = 1; |
| 3250 | ohci->selfid_swap = 0; |
| 3251 | } else |
| 3252 | ohci->selfid_swap = 1; |
| 3253 | #endif |
| 3254 | |
| 3255 | |
| 3256 | #ifndef PCI_DEVICE_ID_NVIDIA_NFORCE2_FW |
| 3257 | #define PCI_DEVICE_ID_NVIDIA_NFORCE2_FW 0x006e |
| 3258 | #endif |
| 3259 | |
| 3260 | /* These chipsets require a bit of extra care when checking after |
| 3261 | * a busreset. */ |
| 3262 | if ((dev->vendor == PCI_VENDOR_ID_APPLE && |
| 3263 | dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) || |
| 3264 | (dev->vendor == PCI_VENDOR_ID_NVIDIA && |
| 3265 | dev->device == PCI_DEVICE_ID_NVIDIA_NFORCE2_FW)) |
| 3266 | ohci->check_busreset = 1; |
| 3267 | |
| 3268 | /* We hardwire the MMIO length, since some CardBus adaptors |
| 3269 | * fail to report the right length. Anyway, the ohci spec |
| 3270 | * clearly says it's 2kb, so this shouldn't be a problem. */ |
| 3271 | ohci_base = pci_resource_start(dev, 0); |
Jody McIntyre | 94c2d01 | 2006-03-28 20:04:04 -0500 | [diff] [blame] | 3272 | if (pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) |
Greg Kroah-Hartman | e29419f | 2006-06-12 15:20:16 -0700 | [diff] [blame] | 3273 | PRINT(KERN_WARNING, "PCI resource length of 0x%llx too small!", |
| 3274 | (unsigned long long)pci_resource_len(dev, 0)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3275 | |
| 3276 | /* Seems PCMCIA handles this internally. Not sure why. Seems |
| 3277 | * pretty bogus to force a driver to special case this. */ |
| 3278 | #ifndef PCMCIA |
| 3279 | if (!request_mem_region (ohci_base, OHCI1394_REGISTER_SIZE, OHCI1394_DRIVER_NAME)) |
Greg Kroah-Hartman | e29419f | 2006-06-12 15:20:16 -0700 | [diff] [blame] | 3280 | FAIL(-ENOMEM, "MMIO resource (0x%llx - 0x%llx) unavailable", |
| 3281 | (unsigned long long)ohci_base, |
| 3282 | (unsigned long long)ohci_base + OHCI1394_REGISTER_SIZE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3283 | #endif |
| 3284 | ohci->init_state = OHCI_INIT_HAVE_MEM_REGION; |
| 3285 | |
| 3286 | ohci->registers = ioremap(ohci_base, OHCI1394_REGISTER_SIZE); |
| 3287 | if (ohci->registers == NULL) |
| 3288 | FAIL(-ENXIO, "Failed to remap registers - card not accessible"); |
| 3289 | ohci->init_state = OHCI_INIT_HAVE_IOMAPPING; |
| 3290 | DBGMSG("Remapped memory spaces reg 0x%p", ohci->registers); |
| 3291 | |
| 3292 | /* csr_config rom allocation */ |
| 3293 | ohci->csr_config_rom_cpu = |
| 3294 | pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN, |
| 3295 | &ohci->csr_config_rom_bus); |
| 3296 | OHCI_DMA_ALLOC("consistent csr_config_rom"); |
| 3297 | if (ohci->csr_config_rom_cpu == NULL) |
| 3298 | FAIL(-ENOMEM, "Failed to allocate buffer config rom"); |
| 3299 | ohci->init_state = OHCI_INIT_HAVE_CONFIG_ROM_BUFFER; |
| 3300 | |
| 3301 | /* self-id dma buffer allocation */ |
| 3302 | ohci->selfid_buf_cpu = |
| 3303 | pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE, |
| 3304 | &ohci->selfid_buf_bus); |
| 3305 | OHCI_DMA_ALLOC("consistent selfid_buf"); |
| 3306 | |
| 3307 | if (ohci->selfid_buf_cpu == NULL) |
| 3308 | FAIL(-ENOMEM, "Failed to allocate DMA buffer for self-id packets"); |
| 3309 | ohci->init_state = OHCI_INIT_HAVE_SELFID_BUFFER; |
| 3310 | |
| 3311 | if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff) |
| 3312 | PRINT(KERN_INFO, "SelfID buffer %p is not aligned on " |
| 3313 | "8Kb boundary... may cause problems on some CXD3222 chip", |
| 3314 | ohci->selfid_buf_cpu); |
| 3315 | |
| 3316 | /* No self-id errors at startup */ |
| 3317 | ohci->self_id_errors = 0; |
| 3318 | |
| 3319 | ohci->init_state = OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE; |
| 3320 | /* AR DMA request context allocation */ |
| 3321 | if (alloc_dma_rcv_ctx(ohci, &ohci->ar_req_context, |
| 3322 | DMA_CTX_ASYNC_REQ, 0, AR_REQ_NUM_DESC, |
| 3323 | AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE, |
| 3324 | OHCI1394_AsReqRcvContextBase) < 0) |
| 3325 | FAIL(-ENOMEM, "Failed to allocate AR Req context"); |
| 3326 | |
| 3327 | /* AR DMA response context allocation */ |
| 3328 | if (alloc_dma_rcv_ctx(ohci, &ohci->ar_resp_context, |
| 3329 | DMA_CTX_ASYNC_RESP, 0, AR_RESP_NUM_DESC, |
| 3330 | AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE, |
| 3331 | OHCI1394_AsRspRcvContextBase) < 0) |
| 3332 | FAIL(-ENOMEM, "Failed to allocate AR Resp context"); |
| 3333 | |
| 3334 | /* AT DMA request context */ |
| 3335 | if (alloc_dma_trm_ctx(ohci, &ohci->at_req_context, |
| 3336 | DMA_CTX_ASYNC_REQ, 0, AT_REQ_NUM_DESC, |
| 3337 | OHCI1394_AsReqTrContextBase) < 0) |
| 3338 | FAIL(-ENOMEM, "Failed to allocate AT Req context"); |
| 3339 | |
| 3340 | /* AT DMA response context */ |
| 3341 | if (alloc_dma_trm_ctx(ohci, &ohci->at_resp_context, |
| 3342 | DMA_CTX_ASYNC_RESP, 1, AT_RESP_NUM_DESC, |
| 3343 | OHCI1394_AsRspTrContextBase) < 0) |
| 3344 | FAIL(-ENOMEM, "Failed to allocate AT Resp context"); |
| 3345 | |
| 3346 | /* Start off with a soft reset, to clear everything to a sane |
| 3347 | * state. */ |
| 3348 | ohci_soft_reset(ohci); |
| 3349 | |
| 3350 | /* Now enable LPS, which we need in order to start accessing |
| 3351 | * most of the registers. In fact, on some cards (ALI M5251), |
| 3352 | * accessing registers in the SClk domain without LPS enabled |
| 3353 | * will lock up the machine. Wait 50msec to make sure we have |
| 3354 | * full link enabled. */ |
| 3355 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); |
| 3356 | |
| 3357 | /* Disable and clear interrupts */ |
| 3358 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); |
| 3359 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); |
| 3360 | |
| 3361 | mdelay(50); |
| 3362 | |
| 3363 | /* Determine the number of available IR and IT contexts. */ |
| 3364 | ohci->nb_iso_rcv_ctx = |
| 3365 | get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3366 | ohci->nb_iso_xmit_ctx = |
| 3367 | get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3368 | |
| 3369 | /* Set the usage bits for non-existent contexts so they can't |
| 3370 | * be allocated */ |
| 3371 | ohci->ir_ctx_usage = ~0 << ohci->nb_iso_rcv_ctx; |
| 3372 | ohci->it_ctx_usage = ~0 << ohci->nb_iso_xmit_ctx; |
| 3373 | |
| 3374 | INIT_LIST_HEAD(&ohci->iso_tasklet_list); |
| 3375 | spin_lock_init(&ohci->iso_tasklet_list_lock); |
| 3376 | ohci->ISO_channel_usage = 0; |
| 3377 | spin_lock_init(&ohci->IR_channel_lock); |
| 3378 | |
| 3379 | /* Allocate the IR DMA context right here so we don't have |
| 3380 | * to do it in interrupt path - note that this doesn't |
| 3381 | * waste much memory and avoids the jugglery required to |
| 3382 | * allocate it in IRQ path. */ |
| 3383 | if (alloc_dma_rcv_ctx(ohci, &ohci->ir_legacy_context, |
| 3384 | DMA_CTX_ISO, 0, IR_NUM_DESC, |
| 3385 | IR_BUF_SIZE, IR_SPLIT_BUF_SIZE, |
| 3386 | OHCI1394_IsoRcvContextBase) < 0) { |
| 3387 | FAIL(-ENOMEM, "Cannot allocate IR Legacy DMA context"); |
| 3388 | } |
| 3389 | |
| 3390 | /* We hopefully don't have to pre-allocate IT DMA like we did |
| 3391 | * for IR DMA above. Allocate it on-demand and mark inactive. */ |
| 3392 | ohci->it_legacy_context.ohci = NULL; |
Al Viro | 3515d01 | 2005-08-25 23:13:14 +0100 | [diff] [blame] | 3393 | spin_lock_init(&ohci->event_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3394 | |
Al Viro | 3515d01 | 2005-08-25 23:13:14 +0100 | [diff] [blame] | 3395 | /* |
| 3396 | * interrupts are disabled, all right, but... due to SA_SHIRQ we |
| 3397 | * might get called anyway. We'll see no event, of course, but |
| 3398 | * we need to get to that "no event", so enough should be initialized |
| 3399 | * by that point. |
| 3400 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3401 | if (request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ, |
| 3402 | OHCI1394_DRIVER_NAME, ohci)) |
| 3403 | FAIL(-ENOMEM, "Failed to allocate shared interrupt %d", dev->irq); |
| 3404 | |
| 3405 | ohci->init_state = OHCI_INIT_HAVE_IRQ; |
| 3406 | ohci_initialize(ohci); |
| 3407 | |
| 3408 | /* Set certain csr values */ |
| 3409 | host->csr.guid_hi = reg_read(ohci, OHCI1394_GUIDHi); |
| 3410 | host->csr.guid_lo = reg_read(ohci, OHCI1394_GUIDLo); |
| 3411 | host->csr.cyc_clk_acc = 100; /* how do we determine clk accuracy? */ |
| 3412 | host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf; |
| 3413 | host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7; |
| 3414 | |
Ben Collins | 4611ed3 | 2006-06-12 18:13:32 -0400 | [diff] [blame] | 3415 | if (phys_dma) { |
| 3416 | host->low_addr_space = |
| 3417 | (u64) reg_read(ohci, OHCI1394_PhyUpperBound) << 16; |
| 3418 | if (!host->low_addr_space) |
| 3419 | host->low_addr_space = OHCI1394_PHYS_UPPER_BOUND_FIXED; |
| 3420 | } |
| 3421 | host->middle_addr_space = OHCI1394_MIDDLE_ADDRESS_SPACE; |
| 3422 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3423 | /* Tell the highlevel this host is ready */ |
| 3424 | if (hpsb_add_host(host)) |
| 3425 | FAIL(-ENOMEM, "Failed to register host with highlevel"); |
| 3426 | |
| 3427 | ohci->init_state = OHCI_INIT_DONE; |
| 3428 | |
| 3429 | return 0; |
| 3430 | #undef FAIL |
| 3431 | } |
| 3432 | |
| 3433 | static void ohci1394_pci_remove(struct pci_dev *pdev) |
| 3434 | { |
| 3435 | struct ti_ohci *ohci; |
| 3436 | struct device *dev; |
| 3437 | |
| 3438 | ohci = pci_get_drvdata(pdev); |
| 3439 | if (!ohci) |
| 3440 | return; |
| 3441 | |
| 3442 | dev = get_device(&ohci->host->device); |
| 3443 | |
| 3444 | switch (ohci->init_state) { |
| 3445 | case OHCI_INIT_DONE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3446 | hpsb_remove_host(ohci->host); |
| 3447 | |
| 3448 | /* Clear out BUS Options */ |
| 3449 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); |
| 3450 | reg_write(ohci, OHCI1394_BusOptions, |
| 3451 | (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) | |
| 3452 | 0x00ff0000); |
| 3453 | memset(ohci->csr_config_rom_cpu, 0, OHCI_CONFIG_ROM_LEN); |
| 3454 | |
| 3455 | case OHCI_INIT_HAVE_IRQ: |
| 3456 | /* Clear interrupt registers */ |
| 3457 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); |
| 3458 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); |
| 3459 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff); |
| 3460 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff); |
| 3461 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff); |
| 3462 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff); |
| 3463 | |
| 3464 | /* Disable IRM Contender */ |
| 3465 | set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4)); |
| 3466 | |
| 3467 | /* Clear link control register */ |
| 3468 | reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); |
| 3469 | |
| 3470 | /* Let all other nodes know to ignore us */ |
| 3471 | ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT); |
| 3472 | |
| 3473 | /* Soft reset before we start - this disables |
| 3474 | * interrupts and clears linkEnable and LPS. */ |
| 3475 | ohci_soft_reset(ohci); |
| 3476 | free_irq(ohci->dev->irq, ohci); |
| 3477 | |
| 3478 | case OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE: |
| 3479 | /* The ohci_soft_reset() stops all DMA contexts, so we |
| 3480 | * dont need to do this. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3481 | free_dma_rcv_ctx(&ohci->ar_req_context); |
| 3482 | free_dma_rcv_ctx(&ohci->ar_resp_context); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3483 | free_dma_trm_ctx(&ohci->at_req_context); |
| 3484 | free_dma_trm_ctx(&ohci->at_resp_context); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3485 | free_dma_rcv_ctx(&ohci->ir_legacy_context); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3486 | free_dma_trm_ctx(&ohci->it_legacy_context); |
| 3487 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3488 | case OHCI_INIT_HAVE_SELFID_BUFFER: |
| 3489 | pci_free_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE, |
| 3490 | ohci->selfid_buf_cpu, |
| 3491 | ohci->selfid_buf_bus); |
| 3492 | OHCI_DMA_FREE("consistent selfid_buf"); |
| 3493 | |
| 3494 | case OHCI_INIT_HAVE_CONFIG_ROM_BUFFER: |
| 3495 | pci_free_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN, |
| 3496 | ohci->csr_config_rom_cpu, |
| 3497 | ohci->csr_config_rom_bus); |
| 3498 | OHCI_DMA_FREE("consistent csr_config_rom"); |
| 3499 | |
| 3500 | case OHCI_INIT_HAVE_IOMAPPING: |
| 3501 | iounmap(ohci->registers); |
| 3502 | |
| 3503 | case OHCI_INIT_HAVE_MEM_REGION: |
| 3504 | #ifndef PCMCIA |
| 3505 | release_mem_region(pci_resource_start(ohci->dev, 0), |
| 3506 | OHCI1394_REGISTER_SIZE); |
| 3507 | #endif |
| 3508 | |
| 3509 | #ifdef CONFIG_PPC_PMAC |
| 3510 | /* On UniNorth, power down the cable and turn off the chip |
| 3511 | * clock when the module is removed to save power on |
| 3512 | * laptops. Turning it back ON is done by the arch code when |
| 3513 | * pci_enable_device() is called */ |
| 3514 | { |
| 3515 | struct device_node* of_node; |
| 3516 | |
| 3517 | of_node = pci_device_to_OF_node(ohci->dev); |
| 3518 | if (of_node) { |
| 3519 | pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0); |
| 3520 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, of_node, 0, 0); |
| 3521 | } |
| 3522 | } |
| 3523 | #endif /* CONFIG_PPC_PMAC */ |
| 3524 | |
| 3525 | case OHCI_INIT_ALLOC_HOST: |
| 3526 | pci_set_drvdata(ohci->dev, NULL); |
| 3527 | } |
| 3528 | |
| 3529 | if (dev) |
| 3530 | put_device(dev); |
| 3531 | } |
| 3532 | |
| 3533 | |
| 3534 | static int ohci1394_pci_resume (struct pci_dev *pdev) |
| 3535 | { |
Benjamin Herrenschmidt | 8c87093 | 2005-06-27 14:36:34 -0700 | [diff] [blame] | 3536 | #ifdef CONFIG_PPC_PMAC |
Benjamin Herrenschmidt | e822250 | 2006-03-28 23:15:54 +1100 | [diff] [blame] | 3537 | if (machine_is(powermac)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3538 | struct device_node *of_node; |
| 3539 | |
| 3540 | /* Re-enable 1394 */ |
| 3541 | of_node = pci_device_to_OF_node (pdev); |
| 3542 | if (of_node) |
| 3543 | pmac_call_feature (PMAC_FTR_1394_ENABLE, of_node, 0, 1); |
| 3544 | } |
Benjamin Herrenschmidt | 8c87093 | 2005-06-27 14:36:34 -0700 | [diff] [blame] | 3545 | #endif /* CONFIG_PPC_PMAC */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3546 | |
Ben Collins | b21efb5 | 2006-06-12 18:15:03 -0400 | [diff] [blame] | 3547 | pci_restore_state(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3548 | pci_enable_device(pdev); |
| 3549 | |
| 3550 | return 0; |
| 3551 | } |
| 3552 | |
| 3553 | |
| 3554 | static int ohci1394_pci_suspend (struct pci_dev *pdev, pm_message_t state) |
| 3555 | { |
Benjamin Herrenschmidt | 8c87093 | 2005-06-27 14:36:34 -0700 | [diff] [blame] | 3556 | #ifdef CONFIG_PPC_PMAC |
Benjamin Herrenschmidt | e822250 | 2006-03-28 23:15:54 +1100 | [diff] [blame] | 3557 | if (machine_is(powermac)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3558 | struct device_node *of_node; |
| 3559 | |
| 3560 | /* Disable 1394 */ |
| 3561 | of_node = pci_device_to_OF_node (pdev); |
| 3562 | if (of_node) |
| 3563 | pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0); |
| 3564 | } |
| 3565 | #endif |
| 3566 | |
Ben Collins | b21efb5 | 2006-06-12 18:15:03 -0400 | [diff] [blame] | 3567 | pci_save_state(pdev); |
| 3568 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3569 | return 0; |
| 3570 | } |
| 3571 | |
| 3572 | |
| 3573 | #define PCI_CLASS_FIREWIRE_OHCI ((PCI_CLASS_SERIAL_FIREWIRE << 8) | 0x10) |
| 3574 | |
| 3575 | static struct pci_device_id ohci1394_pci_tbl[] = { |
| 3576 | { |
| 3577 | .class = PCI_CLASS_FIREWIRE_OHCI, |
| 3578 | .class_mask = PCI_ANY_ID, |
| 3579 | .vendor = PCI_ANY_ID, |
| 3580 | .device = PCI_ANY_ID, |
| 3581 | .subvendor = PCI_ANY_ID, |
| 3582 | .subdevice = PCI_ANY_ID, |
| 3583 | }, |
| 3584 | { 0, }, |
| 3585 | }; |
| 3586 | |
| 3587 | MODULE_DEVICE_TABLE(pci, ohci1394_pci_tbl); |
| 3588 | |
| 3589 | static struct pci_driver ohci1394_pci_driver = { |
| 3590 | .name = OHCI1394_DRIVER_NAME, |
| 3591 | .id_table = ohci1394_pci_tbl, |
| 3592 | .probe = ohci1394_pci_probe, |
| 3593 | .remove = ohci1394_pci_remove, |
| 3594 | .resume = ohci1394_pci_resume, |
| 3595 | .suspend = ohci1394_pci_suspend, |
| 3596 | }; |
| 3597 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3598 | /*********************************** |
| 3599 | * OHCI1394 Video Interface * |
| 3600 | ***********************************/ |
| 3601 | |
| 3602 | /* essentially the only purpose of this code is to allow another |
| 3603 | module to hook into ohci's interrupt handler */ |
| 3604 | |
| 3605 | int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg) |
| 3606 | { |
| 3607 | int i=0; |
| 3608 | |
| 3609 | /* stop the channel program if it's still running */ |
| 3610 | reg_write(ohci, reg, 0x8000); |
| 3611 | |
| 3612 | /* Wait until it effectively stops */ |
| 3613 | while (reg_read(ohci, reg) & 0x400) { |
| 3614 | i++; |
| 3615 | if (i>5000) { |
| 3616 | PRINT(KERN_ERR, |
| 3617 | "Runaway loop while stopping context: %s...", msg ? msg : ""); |
| 3618 | return 1; |
| 3619 | } |
| 3620 | |
| 3621 | mb(); |
| 3622 | udelay(10); |
| 3623 | } |
| 3624 | if (msg) PRINT(KERN_ERR, "%s: dma prg stopped", msg); |
| 3625 | return 0; |
| 3626 | } |
| 3627 | |
| 3628 | void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, int type, |
| 3629 | void (*func)(unsigned long), unsigned long data) |
| 3630 | { |
| 3631 | tasklet_init(&tasklet->tasklet, func, data); |
| 3632 | tasklet->type = type; |
| 3633 | /* We init the tasklet->link field, so we can list_del() it |
| 3634 | * without worrying whether it was added to the list or not. */ |
| 3635 | INIT_LIST_HEAD(&tasklet->link); |
| 3636 | } |
| 3637 | |
| 3638 | int ohci1394_register_iso_tasklet(struct ti_ohci *ohci, |
| 3639 | struct ohci1394_iso_tasklet *tasklet) |
| 3640 | { |
| 3641 | unsigned long flags, *usage; |
| 3642 | int n, i, r = -EBUSY; |
| 3643 | |
| 3644 | if (tasklet->type == OHCI_ISO_TRANSMIT) { |
| 3645 | n = ohci->nb_iso_xmit_ctx; |
| 3646 | usage = &ohci->it_ctx_usage; |
| 3647 | } |
| 3648 | else { |
| 3649 | n = ohci->nb_iso_rcv_ctx; |
| 3650 | usage = &ohci->ir_ctx_usage; |
| 3651 | |
| 3652 | /* only one receive context can be multichannel (OHCI sec 10.4.1) */ |
| 3653 | if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) { |
| 3654 | if (test_and_set_bit(0, &ohci->ir_multichannel_used)) { |
| 3655 | return r; |
| 3656 | } |
| 3657 | } |
| 3658 | } |
| 3659 | |
| 3660 | spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags); |
| 3661 | |
| 3662 | for (i = 0; i < n; i++) |
| 3663 | if (!test_and_set_bit(i, usage)) { |
| 3664 | tasklet->context = i; |
| 3665 | list_add_tail(&tasklet->link, &ohci->iso_tasklet_list); |
| 3666 | r = 0; |
| 3667 | break; |
| 3668 | } |
| 3669 | |
| 3670 | spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags); |
| 3671 | |
| 3672 | return r; |
| 3673 | } |
| 3674 | |
| 3675 | void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci, |
| 3676 | struct ohci1394_iso_tasklet *tasklet) |
| 3677 | { |
| 3678 | unsigned long flags; |
| 3679 | |
| 3680 | tasklet_kill(&tasklet->tasklet); |
| 3681 | |
| 3682 | spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags); |
| 3683 | |
| 3684 | if (tasklet->type == OHCI_ISO_TRANSMIT) |
| 3685 | clear_bit(tasklet->context, &ohci->it_ctx_usage); |
| 3686 | else { |
| 3687 | clear_bit(tasklet->context, &ohci->ir_ctx_usage); |
| 3688 | |
| 3689 | if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) { |
| 3690 | clear_bit(0, &ohci->ir_multichannel_used); |
| 3691 | } |
| 3692 | } |
| 3693 | |
| 3694 | list_del(&tasklet->link); |
| 3695 | |
| 3696 | spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags); |
| 3697 | } |
| 3698 | |
| 3699 | EXPORT_SYMBOL(ohci1394_stop_context); |
| 3700 | EXPORT_SYMBOL(ohci1394_init_iso_tasklet); |
| 3701 | EXPORT_SYMBOL(ohci1394_register_iso_tasklet); |
| 3702 | EXPORT_SYMBOL(ohci1394_unregister_iso_tasklet); |
| 3703 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3704 | /*********************************** |
| 3705 | * General module initialization * |
| 3706 | ***********************************/ |
| 3707 | |
| 3708 | MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>"); |
| 3709 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE-1394 controllers"); |
| 3710 | MODULE_LICENSE("GPL"); |
| 3711 | |
| 3712 | static void __exit ohci1394_cleanup (void) |
| 3713 | { |
| 3714 | pci_unregister_driver(&ohci1394_pci_driver); |
| 3715 | } |
| 3716 | |
| 3717 | static int __init ohci1394_init(void) |
| 3718 | { |
| 3719 | return pci_register_driver(&ohci1394_pci_driver); |
| 3720 | } |
| 3721 | |
| 3722 | module_init(ohci1394_init); |
| 3723 | module_exit(ohci1394_cleanup); |