Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/ppc/syslib/ppc83xx_setup.c |
| 3 | * |
| 4 | * MPC83XX common board code |
| 5 | * |
Kumar Gala | 4c8d3d9 | 2005-11-13 16:06:30 -0800 | [diff] [blame] | 6 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
| 8 | * Copyright 2005 Freescale Semiconductor Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
| 13 | * option) any later version. |
Kumar Gala | 66d2cc9 | 2005-09-03 15:55:50 -0700 | [diff] [blame] | 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, but |
| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 18 | * General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License along |
| 21 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 22 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 23 | * |
| 24 | * Added PCI support -- Tony Li <tony.li@freescale.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | */ |
| 26 | |
| 27 | #include <linux/config.h> |
| 28 | #include <linux/types.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/pci.h> |
| 32 | #include <linux/serial.h> |
| 33 | #include <linux/tty.h> /* for linux/serial_core.h */ |
| 34 | #include <linux/serial_core.h> |
| 35 | #include <linux/serial_8250.h> |
| 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | #include <asm/time.h> |
| 38 | #include <asm/mpc83xx.h> |
| 39 | #include <asm/mmu.h> |
| 40 | #include <asm/ppc_sys.h> |
| 41 | #include <asm/kgdb.h> |
Kumar Gala | f9e4a00 | 2005-05-28 15:52:15 -0700 | [diff] [blame] | 42 | #include <asm/delay.h> |
Paul Mackerras | fd582ec | 2005-10-11 22:08:12 +1000 | [diff] [blame] | 43 | #include <asm/machdep.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | |
| 45 | #include <syslib/ppc83xx_setup.h> |
Kumar Gala | 66d2cc9 | 2005-09-03 15:55:50 -0700 | [diff] [blame] | 46 | #if defined(CONFIG_PCI) |
| 47 | #include <asm/delay.h> |
| 48 | #include <syslib/ppc83xx_pci.h> |
| 49 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
| 51 | phys_addr_t immrbar; |
| 52 | |
| 53 | /* Return the amount of memory */ |
| 54 | unsigned long __init |
| 55 | mpc83xx_find_end_of_memory(void) |
| 56 | { |
| 57 | bd_t *binfo; |
| 58 | |
| 59 | binfo = (bd_t *) __res; |
| 60 | |
| 61 | return binfo->bi_memsize; |
| 62 | } |
| 63 | |
| 64 | long __init |
| 65 | mpc83xx_time_init(void) |
| 66 | { |
| 67 | #define SPCR_OFFS 0x00000110 |
| 68 | #define SPCR_TBEN 0x00400000 |
| 69 | |
| 70 | bd_t *binfo = (bd_t *)__res; |
| 71 | u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4); |
| 72 | |
| 73 | *spcr |= SPCR_TBEN; |
| 74 | |
| 75 | iounmap(spcr); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | /* The decrementer counts at the system (internal) clock freq divided by 4 */ |
| 81 | void __init |
| 82 | mpc83xx_calibrate_decr(void) |
| 83 | { |
| 84 | bd_t *binfo = (bd_t *) __res; |
| 85 | unsigned int freq, divisor; |
| 86 | |
| 87 | freq = binfo->bi_busfreq; |
| 88 | divisor = 4; |
| 89 | tb_ticks_per_jiffy = freq / HZ / divisor; |
| 90 | tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); |
| 91 | } |
| 92 | |
| 93 | #ifdef CONFIG_SERIAL_8250 |
| 94 | void __init |
| 95 | mpc83xx_early_serial_map(void) |
| 96 | { |
| 97 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) |
| 98 | struct uart_port serial_req; |
| 99 | #endif |
| 100 | struct plat_serial8250_port *pdata; |
| 101 | bd_t *binfo = (bd_t *) __res; |
| 102 | pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART); |
| 103 | |
| 104 | /* Setup serial port access */ |
| 105 | pdata[0].uartclk = binfo->bi_busfreq; |
| 106 | pdata[0].mapbase += binfo->bi_immr_base; |
| 107 | pdata[0].membase = ioremap(pdata[0].mapbase, 0x100); |
| 108 | |
| 109 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) |
| 110 | memset(&serial_req, 0, sizeof (serial_req)); |
| 111 | serial_req.iotype = SERIAL_IO_MEM; |
| 112 | serial_req.mapbase = pdata[0].mapbase; |
| 113 | serial_req.membase = pdata[0].membase; |
| 114 | serial_req.regshift = 0; |
| 115 | |
| 116 | gen550_init(0, &serial_req); |
| 117 | #endif |
| 118 | |
| 119 | pdata[1].uartclk = binfo->bi_busfreq; |
| 120 | pdata[1].mapbase += binfo->bi_immr_base; |
| 121 | pdata[1].membase = ioremap(pdata[1].mapbase, 0x100); |
| 122 | |
| 123 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) |
| 124 | /* Assume gen550_init() doesn't modify serial_req */ |
| 125 | serial_req.mapbase = pdata[1].mapbase; |
| 126 | serial_req.membase = pdata[1].membase; |
| 127 | |
| 128 | gen550_init(1, &serial_req); |
| 129 | #endif |
| 130 | } |
| 131 | #endif |
| 132 | |
| 133 | void |
| 134 | mpc83xx_restart(char *cmd) |
| 135 | { |
Kumar Gala | f9e4a00 | 2005-05-28 15:52:15 -0700 | [diff] [blame] | 136 | volatile unsigned char __iomem *reg; |
| 137 | unsigned char tmp; |
| 138 | |
| 139 | reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE); |
| 140 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | local_irq_disable(); |
Kumar Gala | f9e4a00 | 2005-05-28 15:52:15 -0700 | [diff] [blame] | 142 | |
| 143 | /* |
| 144 | * Unlock the BCSR bits so a PRST will update the contents. |
| 145 | * Otherwise the reset asserts but doesn't clear. |
| 146 | */ |
| 147 | tmp = in_8(reg + BCSR_MISC_REG3_OFF); |
| 148 | tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */ |
| 149 | out_8(reg + BCSR_MISC_REG3_OFF, tmp); |
| 150 | |
| 151 | /* |
| 152 | * Trigger a reset via a low->high transition of the |
| 153 | * PORESET bit. |
| 154 | */ |
| 155 | tmp = in_8(reg + BCSR_MISC_REG2_OFF); |
| 156 | tmp &= ~BCSR_MISC_REG2_PORESET; |
| 157 | out_8(reg + BCSR_MISC_REG2_OFF, tmp); |
| 158 | |
| 159 | udelay(1); |
| 160 | |
| 161 | tmp |= BCSR_MISC_REG2_PORESET; |
| 162 | out_8(reg + BCSR_MISC_REG2_OFF, tmp); |
| 163 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | for(;;); |
| 165 | } |
| 166 | |
| 167 | void |
| 168 | mpc83xx_power_off(void) |
| 169 | { |
| 170 | local_irq_disable(); |
| 171 | for(;;); |
| 172 | } |
| 173 | |
| 174 | void |
| 175 | mpc83xx_halt(void) |
| 176 | { |
| 177 | local_irq_disable(); |
| 178 | for(;;); |
| 179 | } |
| 180 | |
Kumar Gala | 66d2cc9 | 2005-09-03 15:55:50 -0700 | [diff] [blame] | 181 | #if defined(CONFIG_PCI) |
| 182 | void __init |
| 183 | mpc83xx_setup_pci1(struct pci_controller *hose) |
| 184 | { |
| 185 | u16 reg16; |
| 186 | volatile immr_pcictrl_t * pci_ctrl; |
| 187 | volatile immr_ios_t * ios; |
| 188 | bd_t *binfo = (bd_t *) __res; |
| 189 | |
| 190 | pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t)); |
| 191 | ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); |
| 192 | |
| 193 | /* |
| 194 | * Configure PCI Outbound Translation Windows |
| 195 | */ |
| 196 | ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK; |
| 197 | ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK; |
| 198 | ios->pocmr0 = POCMR_EN | |
| 199 | (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM - |
| 200 | MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK); |
| 201 | |
| 202 | /* mapped to PCI1 IO space */ |
| 203 | ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK; |
| 204 | ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK; |
| 205 | ios->pocmr1 = POCMR_EN | POCMR_IO | |
| 206 | (((0xffffffff - (MPC83xx_PCI1_UPPER_IO - |
| 207 | MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK); |
| 208 | |
| 209 | /* |
| 210 | * Configure PCI Inbound Translation Windows |
| 211 | */ |
| 212 | pci_ctrl->pitar1 = 0x0; |
| 213 | pci_ctrl->pibar1 = 0x0; |
| 214 | pci_ctrl->piebar1 = 0x0; |
| 215 | pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; |
| 216 | |
| 217 | /* |
| 218 | * Release PCI RST signal |
| 219 | */ |
| 220 | pci_ctrl->gcr = 0; |
| 221 | udelay(2000); |
| 222 | pci_ctrl->gcr = 1; |
| 223 | udelay(2000); |
| 224 | |
| 225 | reg16 = 0xff; |
| 226 | early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); |
| 227 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 228 | early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); |
| 229 | |
| 230 | /* |
| 231 | * Clear non-reserved bits in status register. |
| 232 | */ |
| 233 | early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); |
| 234 | early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); |
| 235 | |
| 236 | iounmap(pci_ctrl); |
| 237 | iounmap(ios); |
| 238 | } |
| 239 | |
| 240 | void __init |
| 241 | mpc83xx_setup_pci2(struct pci_controller *hose) |
| 242 | { |
| 243 | u16 reg16; |
| 244 | volatile immr_pcictrl_t * pci_ctrl; |
| 245 | volatile immr_ios_t * ios; |
| 246 | bd_t *binfo = (bd_t *) __res; |
| 247 | |
| 248 | pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t)); |
| 249 | ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); |
| 250 | |
| 251 | /* |
| 252 | * Configure PCI Outbound Translation Windows |
| 253 | */ |
| 254 | ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK; |
| 255 | ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK; |
| 256 | ios->pocmr3 = POCMR_EN | POCMR_DST | |
| 257 | (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM - |
| 258 | MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK); |
| 259 | |
| 260 | /* mapped to PCI2 IO space */ |
| 261 | ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK; |
| 262 | ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK; |
| 263 | ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO | |
| 264 | (((0xffffffff - (MPC83xx_PCI2_UPPER_IO - |
| 265 | MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK); |
| 266 | |
| 267 | /* |
| 268 | * Configure PCI Inbound Translation Windows |
| 269 | */ |
| 270 | pci_ctrl->pitar1 = 0x0; |
| 271 | pci_ctrl->pibar1 = 0x0; |
| 272 | pci_ctrl->piebar1 = 0x0; |
| 273 | pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; |
| 274 | |
| 275 | /* |
| 276 | * Release PCI RST signal |
| 277 | */ |
| 278 | pci_ctrl->gcr = 0; |
| 279 | udelay(2000); |
| 280 | pci_ctrl->gcr = 1; |
| 281 | udelay(2000); |
| 282 | |
| 283 | reg16 = 0xff; |
| 284 | early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); |
| 285 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 286 | early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); |
| 287 | |
| 288 | /* |
| 289 | * Clear non-reserved bits in status register. |
| 290 | */ |
| 291 | early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); |
| 292 | early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); |
| 293 | |
| 294 | iounmap(pci_ctrl); |
| 295 | iounmap(ios); |
| 296 | } |
| 297 | |
| 298 | /* |
| 299 | * PCI buses can be enabled only if SYS board combinates with PIB |
| 300 | * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses |
| 301 | * and 3 PCI slots, so people must configure the routes between them before |
| 302 | * enable PCI bus. This routes are under the control of PCA9555PW device which |
| 303 | * can be accessed via I2C bus 2 and are configured by firmware. Refer to |
| 304 | * Freescale to get more information about firmware configuration. |
| 305 | */ |
| 306 | |
| 307 | extern int mpc83xx_exclude_device(u_char bus, u_char devfn); |
| 308 | extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, |
| 309 | unsigned char pin); |
| 310 | void __init |
| 311 | mpc83xx_setup_hose(void) |
| 312 | { |
| 313 | u32 val32; |
| 314 | volatile immr_clk_t * clk; |
| 315 | struct pci_controller * hose1; |
| 316 | #ifdef CONFIG_MPC83xx_PCI2 |
| 317 | struct pci_controller * hose2; |
| 318 | #endif |
| 319 | bd_t * binfo = (bd_t *)__res; |
| 320 | |
| 321 | clk = ioremap(binfo->bi_immr_base + 0xA00, |
| 322 | sizeof(immr_clk_t)); |
| 323 | |
| 324 | /* |
| 325 | * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode |
| 326 | */ |
| 327 | val32 = clk->occr; |
| 328 | udelay(2000); |
| 329 | clk->occr = 0xff000000; |
| 330 | udelay(2000); |
| 331 | |
| 332 | iounmap(clk); |
| 333 | |
| 334 | hose1 = pcibios_alloc_controller(); |
| 335 | if(!hose1) |
| 336 | return; |
| 337 | |
| 338 | ppc_md.pci_swizzle = common_swizzle; |
| 339 | ppc_md.pci_map_irq = mpc83xx_map_irq; |
| 340 | |
| 341 | hose1->bus_offset = 0; |
| 342 | hose1->first_busno = 0; |
| 343 | hose1->last_busno = 0xff; |
| 344 | |
| 345 | setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, |
| 346 | binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); |
| 347 | hose1->set_cfg_type = 1; |
| 348 | |
| 349 | mpc83xx_setup_pci1(hose1); |
| 350 | |
| 351 | hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET; |
| 352 | hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM; |
| 353 | hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM; |
| 354 | |
| 355 | hose1->io_base_phys = MPC83xx_PCI1_IO_BASE; |
| 356 | hose1->io_space.start = MPC83xx_PCI1_LOWER_IO; |
| 357 | hose1->io_space.end = MPC83xx_PCI1_UPPER_IO; |
| 358 | #ifdef CONFIG_MPC83xx_PCI2 |
| 359 | isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, |
| 360 | MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE); |
| 361 | #else |
| 362 | isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, |
| 363 | MPC83xx_PCI1_IO_SIZE); |
| 364 | #endif /* CONFIG_MPC83xx_PCI2 */ |
| 365 | hose1->io_base_virt = (void *)isa_io_base; |
| 366 | /* setup resources */ |
| 367 | pci_init_resource(&hose1->io_resource, |
| 368 | MPC83xx_PCI1_LOWER_IO, |
| 369 | MPC83xx_PCI1_UPPER_IO, |
| 370 | IORESOURCE_IO, "PCI host bridge 1"); |
| 371 | pci_init_resource(&hose1->mem_resources[0], |
| 372 | MPC83xx_PCI1_LOWER_MEM, |
| 373 | MPC83xx_PCI1_UPPER_MEM, |
| 374 | IORESOURCE_MEM, "PCI host bridge 1"); |
| 375 | |
| 376 | ppc_md.pci_exclude_device = mpc83xx_exclude_device; |
| 377 | hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); |
| 378 | |
| 379 | #ifdef CONFIG_MPC83xx_PCI2 |
| 380 | hose2 = pcibios_alloc_controller(); |
| 381 | if(!hose2) |
| 382 | return; |
| 383 | |
| 384 | hose2->bus_offset = hose1->last_busno + 1; |
| 385 | hose2->first_busno = hose1->last_busno + 1; |
| 386 | hose2->last_busno = 0xff; |
| 387 | setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, |
| 388 | binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); |
| 389 | hose2->set_cfg_type = 1; |
| 390 | |
| 391 | mpc83xx_setup_pci2(hose2); |
| 392 | |
| 393 | hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET; |
| 394 | hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM; |
| 395 | hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM; |
| 396 | |
| 397 | hose2->io_base_phys = MPC83xx_PCI2_IO_BASE; |
| 398 | hose2->io_space.start = MPC83xx_PCI2_LOWER_IO; |
| 399 | hose2->io_space.end = MPC83xx_PCI2_UPPER_IO; |
| 400 | hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE); |
| 401 | /* setup resources */ |
| 402 | pci_init_resource(&hose2->io_resource, |
| 403 | MPC83xx_PCI2_LOWER_IO, |
| 404 | MPC83xx_PCI2_UPPER_IO, |
| 405 | IORESOURCE_IO, "PCI host bridge 2"); |
| 406 | pci_init_resource(&hose2->mem_resources[0], |
| 407 | MPC83xx_PCI2_LOWER_MEM, |
| 408 | MPC83xx_PCI2_UPPER_MEM, |
| 409 | IORESOURCE_MEM, "PCI host bridge 2"); |
| 410 | |
| 411 | hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); |
| 412 | #endif /* CONFIG_MPC83xx_PCI2 */ |
| 413 | } |
| 414 | #endif /*CONFIG_PCI*/ |