blob: 108a6e265185b443985e86fe95dced1108e39260 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/ppc/platforms/chrp_pegasos_eth.c
3 *
4 * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
5 * Thanks to :
6 * Dale Farnsworth <dale@farnsworth.org>
7 * Mark A. Greer <mgreer@mvista.com>
8 * Nicolas DET <nd@bplan-gmbh.de>
9 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
10 * And anyone else who helped me on this.
11 */
12
13#include <linux/types.h>
14#include <linux/init.h>
15#include <linux/ioport.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010016#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/mv643xx.h>
18#include <linux/pci.h>
19
Nicolas DETdd03d252005-10-28 17:46:25 -070020#define PEGASOS2_MARVELL_REGBASE (0xf1000000)
21#define PEGASOS2_MARVELL_REGSIZE (0x00004000)
22#define PEGASOS2_SRAM_BASE (0xf2000000)
23#define PEGASOS2_SRAM_SIZE (256*1024)
24
25#define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE)
26#define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
27
28
29#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
30#define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
31
32#undef BE_VERBOSE
33
Linus Torvalds1da177e2005-04-16 15:20:36 -070034static struct resource mv643xx_eth_shared_resources[] = {
35 [0] = {
36 .name = "ethernet shared base",
37 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
38 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
39 MV643XX_ETH_SHARED_REGS_SIZE - 1,
40 .flags = IORESOURCE_MEM,
41 },
42};
43
44static struct platform_device mv643xx_eth_shared_device = {
45 .name = MV643XX_ETH_SHARED_NAME,
46 .id = 0,
47 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
48 .resource = mv643xx_eth_shared_resources,
49};
50
51static struct resource mv643xx_eth0_resources[] = {
52 [0] = {
53 .name = "eth0 irq",
54 .start = 9,
55 .end = 9,
56 .flags = IORESOURCE_IRQ,
57 },
58};
59
Nicolas DETdd03d252005-10-28 17:46:25 -070060
61static struct mv643xx_eth_platform_data eth0_pd = {
62 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
63 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
64 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
65
66 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE,
67 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
68 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
69};
Linus Torvalds1da177e2005-04-16 15:20:36 -070070
71static struct platform_device eth0_device = {
72 .name = MV643XX_ETH_NAME,
73 .id = 0,
74 .num_resources = ARRAY_SIZE(mv643xx_eth0_resources),
75 .resource = mv643xx_eth0_resources,
76 .dev = {
77 .platform_data = &eth0_pd,
78 },
79};
80
81static struct resource mv643xx_eth1_resources[] = {
82 [0] = {
83 .name = "eth1 irq",
84 .start = 9,
85 .end = 9,
86 .flags = IORESOURCE_IRQ,
87 },
88};
89
Nicolas DETdd03d252005-10-28 17:46:25 -070090static struct mv643xx_eth_platform_data eth1_pd = {
91 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1,
92 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
93 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
94
95 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE,
96 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
97 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
98};
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
100static struct platform_device eth1_device = {
101 .name = MV643XX_ETH_NAME,
102 .id = 1,
103 .num_resources = ARRAY_SIZE(mv643xx_eth1_resources),
104 .resource = mv643xx_eth1_resources,
105 .dev = {
106 .platform_data = &eth1_pd,
107 },
108};
109
110static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
111 &mv643xx_eth_shared_device,
112 &eth0_device,
113 &eth1_device,
114};
115
Nicolas DETdd03d252005-10-28 17:46:25 -0700116/***********/
117/***********/
118#define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
119#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120
Nicolas DETdd03d252005-10-28 17:46:25 -0700121static void __iomem *mv643xx_reg_base;
122
123static int Enable_SRAM(void)
124{
125 u32 ALong;
126
127 if (mv643xx_reg_base == NULL)
128 mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
129 PEGASOS2_MARVELL_REGSIZE);
130
131 if (mv643xx_reg_base == NULL)
132 return -ENOMEM;
133
134#ifdef BE_VERBOSE
135 printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
136 (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
137#endif
138
139 MV_WRITE(MV64340_SRAM_CONFIG, 0);
140
141 MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
142
143 MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
144 ALong &= ~(1 << 19);
145 MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
146
147 ALong = 0x02;
148 ALong |= PEGASOS2_SRAM_BASE & 0xffff0000;
149 MV_WRITE(MV643XX_ETH_BAR_4, ALong);
150
151 MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);
152
153 MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
154 ALong &= ~(1 << 4);
155 MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
156
157#ifdef BE_VERBOSE
158 printk("Pegasos II/Marvell MV64361: register unmapped\n");
159 printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
160#endif
161
162 iounmap(mv643xx_reg_base);
163 mv643xx_reg_base = NULL;
164
165 return 1;
166}
167
168
169/***********/
170/***********/
171int mv643xx_eth_add_pds(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172{
173 int ret = 0;
174 static struct pci_device_id pci_marvell_mv64360[] = {
175 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
176 { }
177 };
178
Nicolas DETdd03d252005-10-28 17:46:25 -0700179#ifdef BE_VERBOSE
180 printk("Pegasos II/Marvell MV64361: init\n");
181#endif
182
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 if (pci_dev_present(pci_marvell_mv64360)) {
Nicolas DETdd03d252005-10-28 17:46:25 -0700184 ret = platform_add_devices(mv643xx_eth_pd_devs,
185 ARRAY_SIZE(mv643xx_eth_pd_devs));
186
187 if ( Enable_SRAM() < 0)
188 {
189 eth0_pd.tx_sram_addr = 0;
190 eth0_pd.tx_sram_size = 0;
191 eth0_pd.rx_sram_addr = 0;
192 eth0_pd.rx_sram_size = 0;
193
194 eth1_pd.tx_sram_addr = 0;
195 eth1_pd.tx_sram_size = 0;
196 eth1_pd.rx_sram_addr = 0;
197 eth1_pd.rx_sram_size = 0;
198
199#ifdef BE_VERBOSE
200 printk("Pegasos II/Marvell MV64361: Can't enable the "
201 "SRAM\n");
202#endif
203 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 }
Nicolas DETdd03d252005-10-28 17:46:25 -0700205
206#ifdef BE_VERBOSE
207 printk("Pegasos II/Marvell MV64361: init is over\n");
208#endif
209
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 return ret;
211}
Nicolas DETdd03d252005-10-28 17:46:25 -0700212
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213device_initcall(mv643xx_eth_add_pds);