Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004 James Cleverdon, IBM. |
| 3 | * Subject to the GNU Public License, v.2 |
| 4 | * |
| 5 | * Clustered APIC subarch code. Up to 255 CPUs, physical delivery. |
| 6 | * (A more realistic maximum is around 230 CPUs.) |
| 7 | * |
| 8 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by |
| 9 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and |
| 10 | * James Cleverdon. |
| 11 | */ |
| 12 | #include <linux/config.h> |
| 13 | #include <linux/threads.h> |
| 14 | #include <linux/cpumask.h> |
| 15 | #include <linux/string.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/ctype.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <asm/smp.h> |
| 20 | #include <asm/ipi.h> |
| 21 | |
| 22 | |
| 23 | /* |
| 24 | * Set up the logical destination ID. |
| 25 | * |
| 26 | * Intel recommends to set DFR, LDR and TPR before enabling |
| 27 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
| 28 | * document number 292116). So here it goes... |
| 29 | */ |
| 30 | static void cluster_init_apic_ldr(void) |
| 31 | { |
| 32 | unsigned long val, id; |
| 33 | long i, count; |
| 34 | u8 lid; |
| 35 | u8 my_id = hard_smp_processor_id(); |
| 36 | u8 my_cluster = APIC_CLUSTER(my_id); |
| 37 | |
| 38 | /* Create logical APIC IDs by counting CPUs already in cluster. */ |
| 39 | for (count = 0, i = NR_CPUS; --i >= 0; ) { |
| 40 | lid = x86_cpu_to_log_apicid[i]; |
| 41 | if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster) |
| 42 | ++count; |
| 43 | } |
| 44 | /* |
| 45 | * We only have a 4 wide bitmap in cluster mode. There's no way |
| 46 | * to get above 60 CPUs and still give each one it's own bit. |
| 47 | * But, we're using physical IRQ delivery, so we don't care. |
| 48 | * Use bit 3 for the 4th through Nth CPU in each cluster. |
| 49 | */ |
| 50 | if (count >= XAPIC_DEST_CPUS_SHIFT) |
| 51 | count = 3; |
| 52 | id = my_cluster | (1UL << count); |
| 53 | x86_cpu_to_log_apicid[smp_processor_id()] = id; |
| 54 | apic_write_around(APIC_DFR, APIC_DFR_CLUSTER); |
| 55 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
| 56 | val |= SET_APIC_LOGICAL_ID(id); |
| 57 | apic_write_around(APIC_LDR, val); |
| 58 | } |
| 59 | |
| 60 | /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */ |
| 61 | |
| 62 | static cpumask_t cluster_target_cpus(void) |
| 63 | { |
| 64 | return cpumask_of_cpu(0); |
| 65 | } |
| 66 | |
| 67 | static void cluster_send_IPI_mask(cpumask_t mask, int vector) |
| 68 | { |
| 69 | send_IPI_mask_sequence(mask, vector); |
| 70 | } |
| 71 | |
| 72 | static void cluster_send_IPI_allbutself(int vector) |
| 73 | { |
| 74 | cpumask_t mask = cpu_online_map; |
| 75 | cpu_clear(smp_processor_id(), mask); |
| 76 | |
| 77 | if (!cpus_empty(mask)) |
| 78 | cluster_send_IPI_mask(mask, vector); |
| 79 | } |
| 80 | |
| 81 | static void cluster_send_IPI_all(int vector) |
| 82 | { |
| 83 | cluster_send_IPI_mask(cpu_online_map, vector); |
| 84 | } |
| 85 | |
| 86 | static int cluster_apic_id_registered(void) |
| 87 | { |
| 88 | return 1; |
| 89 | } |
| 90 | |
| 91 | static unsigned int cluster_cpu_mask_to_apicid(cpumask_t cpumask) |
| 92 | { |
| 93 | int cpu; |
| 94 | |
| 95 | /* |
| 96 | * We're using fixed IRQ delivery, can only return one phys APIC ID. |
| 97 | * May as well be the first. |
| 98 | */ |
| 99 | cpu = first_cpu(cpumask); |
| 100 | if ((unsigned)cpu < NR_CPUS) |
| 101 | return x86_cpu_to_apicid[cpu]; |
| 102 | else |
| 103 | return BAD_APICID; |
| 104 | } |
| 105 | |
| 106 | /* cpuid returns the value latched in the HW at reset, not the APIC ID |
| 107 | * register's value. For any box whose BIOS changes APIC IDs, like |
| 108 | * clustered APIC systems, we must use hard_smp_processor_id. |
| 109 | * |
| 110 | * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID. |
| 111 | */ |
| 112 | static unsigned int phys_pkg_id(int index_msb) |
| 113 | { |
| 114 | return hard_smp_processor_id() >> index_msb; |
| 115 | } |
| 116 | |
| 117 | struct genapic apic_cluster = { |
| 118 | .name = "clustered", |
| 119 | .int_delivery_mode = dest_Fixed, |
| 120 | .int_dest_mode = (APIC_DEST_PHYSICAL != 0), |
| 121 | .int_delivery_dest = APIC_DEST_PHYSICAL | APIC_DM_FIXED, |
| 122 | .target_cpus = cluster_target_cpus, |
| 123 | .apic_id_registered = cluster_apic_id_registered, |
| 124 | .init_apic_ldr = cluster_init_apic_ldr, |
| 125 | .send_IPI_all = cluster_send_IPI_all, |
| 126 | .send_IPI_allbutself = cluster_send_IPI_allbutself, |
| 127 | .send_IPI_mask = cluster_send_IPI_mask, |
| 128 | .cpu_mask_to_apicid = cluster_cpu_mask_to_apicid, |
| 129 | .phys_pkg_id = phys_pkg_id, |
| 130 | }; |