Mikael Starvik | 51533b6 | 2005-07-27 11:44:44 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Low level TLB handling. |
| 3 | * |
| 4 | * Copyright (C) 2000-2003, Axis Communications AB. |
| 5 | * |
| 6 | * Authors: Bjorn Wesen <bjornw@axis.com> |
| 7 | * Tobias Anderberg <tobiasa@axis.com>, CRISv32 port. |
| 8 | */ |
| 9 | |
| 10 | #include <asm/tlb.h> |
| 11 | #include <asm/mmu_context.h> |
| 12 | #include <asm/arch/hwregs/asm/mmu_defs_asm.h> |
| 13 | #include <asm/arch/hwregs/supp_reg.h> |
| 14 | |
| 15 | #define UPDATE_TLB_SEL_IDX(val) \ |
| 16 | do { \ |
| 17 | unsigned long tlb_sel; \ |
| 18 | \ |
| 19 | tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, val); \ |
| 20 | SUPP_REG_WR(RW_MM_TLB_SEL, tlb_sel); \ |
| 21 | } while(0) |
| 22 | |
| 23 | #define UPDATE_TLB_HILO(tlb_hi, tlb_lo) \ |
| 24 | do { \ |
| 25 | SUPP_REG_WR(RW_MM_TLB_HI, tlb_hi); \ |
| 26 | SUPP_REG_WR(RW_MM_TLB_LO, tlb_lo); \ |
| 27 | } while(0) |
| 28 | |
| 29 | /* |
| 30 | * The TLB can host up to 256 different mm contexts at the same time. The running |
| 31 | * context is found in the PID register. Each TLB entry contains a page_id that |
| 32 | * has to match the PID register to give a hit. page_id_map keeps track of which |
| 33 | * mm's is assigned to which page_id's, making sure it's known when to |
| 34 | * invalidate TLB entries. |
| 35 | * |
| 36 | * The last page_id is never running, it is used as an invalid page_id so that |
| 37 | * it's possible to make TLB entries that will nerver match. |
| 38 | * |
| 39 | * Note; the flushes needs to be atomic otherwise an interrupt hander that uses |
| 40 | * vmalloc'ed memory might cause a TLB load in the middle of a flush. |
| 41 | */ |
| 42 | |
| 43 | /* Flush all TLB entries. */ |
| 44 | void |
| 45 | __flush_tlb_all(void) |
| 46 | { |
| 47 | int i; |
| 48 | int mmu; |
| 49 | unsigned long flags; |
| 50 | unsigned long mmu_tlb_hi; |
| 51 | unsigned long mmu_tlb_sel; |
| 52 | |
| 53 | /* |
| 54 | * Mask with 0xf so similar TLB entries aren't written in the same 4-way |
| 55 | * entry group. |
| 56 | */ |
| 57 | local_save_flags(flags); |
| 58 | local_irq_disable(); |
| 59 | |
| 60 | for (mmu = 1; mmu <= 2; mmu++) { |
| 61 | SUPP_BANK_SEL(mmu); /* Select the MMU */ |
| 62 | for (i = 0; i < NUM_TLB_ENTRIES; i++) { |
| 63 | /* Store invalid entry */ |
| 64 | mmu_tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, i); |
| 65 | |
| 66 | mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, INVALID_PAGEID) |
| 67 | | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, i & 0xf)); |
| 68 | |
| 69 | SUPP_REG_WR(RW_MM_TLB_SEL, mmu_tlb_sel); |
| 70 | SUPP_REG_WR(RW_MM_TLB_HI, mmu_tlb_hi); |
| 71 | SUPP_REG_WR(RW_MM_TLB_LO, 0); |
| 72 | } |
| 73 | } |
| 74 | |
| 75 | local_irq_restore(flags); |
| 76 | } |
| 77 | |
| 78 | /* Flush an entire user address space. */ |
| 79 | void |
| 80 | __flush_tlb_mm(struct mm_struct *mm) |
| 81 | { |
| 82 | int i; |
| 83 | int mmu; |
| 84 | unsigned long flags; |
| 85 | unsigned long page_id; |
| 86 | unsigned long tlb_hi; |
| 87 | unsigned long mmu_tlb_hi; |
| 88 | |
| 89 | page_id = mm->context.page_id; |
| 90 | |
| 91 | if (page_id == NO_CONTEXT) |
| 92 | return; |
| 93 | |
| 94 | /* Mark the TLB entries that match the page_id as invalid. */ |
| 95 | local_save_flags(flags); |
| 96 | local_irq_disable(); |
| 97 | |
| 98 | for (mmu = 1; mmu <= 2; mmu++) { |
| 99 | SUPP_BANK_SEL(mmu); |
| 100 | for (i = 0; i < NUM_TLB_ENTRIES; i++) { |
| 101 | UPDATE_TLB_SEL_IDX(i); |
| 102 | |
| 103 | /* Get the page_id */ |
| 104 | SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi); |
| 105 | |
| 106 | /* Check if the page_id match. */ |
| 107 | if ((tlb_hi & 0xff) == page_id) { |
| 108 | mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, |
| 109 | INVALID_PAGEID) |
| 110 | | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, |
| 111 | i & 0xf)); |
| 112 | |
| 113 | UPDATE_TLB_HILO(mmu_tlb_hi, 0); |
| 114 | } |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | local_irq_restore(flags); |
| 119 | } |
| 120 | |
| 121 | /* Invalidate a single page. */ |
| 122 | void |
| 123 | __flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) |
| 124 | { |
| 125 | int i; |
| 126 | int mmu; |
| 127 | unsigned long page_id; |
| 128 | unsigned long flags; |
| 129 | unsigned long tlb_hi; |
| 130 | unsigned long mmu_tlb_hi; |
| 131 | |
| 132 | page_id = vma->vm_mm->context.page_id; |
| 133 | |
| 134 | if (page_id == NO_CONTEXT) |
| 135 | return; |
| 136 | |
| 137 | addr &= PAGE_MASK; |
| 138 | |
| 139 | /* |
| 140 | * Invalidate those TLB entries that match both the mm context and the |
| 141 | * requested virtual address. |
| 142 | */ |
| 143 | local_save_flags(flags); |
| 144 | local_irq_disable(); |
| 145 | |
| 146 | for (mmu = 1; mmu <= 2; mmu++) { |
| 147 | SUPP_BANK_SEL(mmu); |
| 148 | for (i = 0; i < NUM_TLB_ENTRIES; i++) { |
| 149 | UPDATE_TLB_SEL_IDX(i); |
| 150 | SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi); |
| 151 | |
| 152 | /* Check if page_id and address matches */ |
| 153 | if (((tlb_hi & 0xff) == page_id) && |
| 154 | ((tlb_hi & PAGE_MASK) == addr)) { |
| 155 | mmu_tlb_hi = REG_FIELD(mmu, rw_mm_tlb_hi, pid, |
| 156 | INVALID_PAGEID) | addr; |
| 157 | |
| 158 | UPDATE_TLB_HILO(mmu_tlb_hi, 0); |
| 159 | } |
| 160 | } |
| 161 | } |
| 162 | |
| 163 | local_irq_restore(flags); |
| 164 | } |
| 165 | |
| 166 | /* |
| 167 | * Initialize the context related info for a new mm_struct |
| 168 | * instance. |
| 169 | */ |
| 170 | |
| 171 | int |
| 172 | init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
| 173 | { |
| 174 | mm->context.page_id = NO_CONTEXT; |
| 175 | return 0; |
| 176 | } |
| 177 | |
Hugh Dickins | a7e4705 | 2005-10-29 18:16:37 -0700 | [diff] [blame] | 178 | static DEFINE_SPINLOCK(mmu_context_lock); |
| 179 | |
Mikael Starvik | 51533b6 | 2005-07-27 11:44:44 -0700 | [diff] [blame] | 180 | /* Called in schedule() just before actually doing the switch_to. */ |
| 181 | void |
| 182 | switch_mm(struct mm_struct *prev, struct mm_struct *next, |
| 183 | struct task_struct *tsk) |
| 184 | { |
| 185 | int cpu = smp_processor_id(); |
| 186 | |
| 187 | /* Make sure there is a MMU context. */ |
Hugh Dickins | a7e4705 | 2005-10-29 18:16:37 -0700 | [diff] [blame] | 188 | spin_lock(&mmu_context_lock); |
Mikael Starvik | 51533b6 | 2005-07-27 11:44:44 -0700 | [diff] [blame] | 189 | get_mmu_context(next); |
| 190 | cpu_set(cpu, next->cpu_vm_mask); |
Hugh Dickins | a7e4705 | 2005-10-29 18:16:37 -0700 | [diff] [blame] | 191 | spin_unlock(&mmu_context_lock); |
Mikael Starvik | 51533b6 | 2005-07-27 11:44:44 -0700 | [diff] [blame] | 192 | |
| 193 | /* |
| 194 | * Remember the pgd for the fault handlers. Keep a seperate copy of it |
| 195 | * because current and active_mm might be invalid at points where |
| 196 | * there's still a need to derefer the pgd. |
| 197 | */ |
| 198 | per_cpu(current_pgd, cpu) = next->pgd; |
| 199 | |
| 200 | /* Switch context in the MMU. */ |
Al Viro | 718d611 | 2006-01-12 01:06:04 -0800 | [diff] [blame] | 201 | if (tsk && task_thread_info(tsk)) |
Mikael Starvik | 51533b6 | 2005-07-27 11:44:44 -0700 | [diff] [blame] | 202 | { |
Al Viro | 718d611 | 2006-01-12 01:06:04 -0800 | [diff] [blame] | 203 | SPEC_REG_WR(SPEC_REG_PID, next->context.page_id | task_thread_info(tsk)->tls); |
Mikael Starvik | 51533b6 | 2005-07-27 11:44:44 -0700 | [diff] [blame] | 204 | } |
| 205 | else |
| 206 | { |
| 207 | SPEC_REG_WR(SPEC_REG_PID, next->context.page_id); |
| 208 | } |
| 209 | } |
| 210 | |