David Howells | c9034c3 | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto |
| 7 | * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org> |
| 8 | */ |
| 9 | #ifndef _ASM_M32R_BARRIER_H |
| 10 | #define _ASM_M32R_BARRIER_H |
| 11 | |
| 12 | #define nop() __asm__ __volatile__ ("nop" : : ) |
| 13 | |
| 14 | /* |
| 15 | * Memory barrier. |
| 16 | * |
| 17 | * mb() prevents loads and stores being reordered across this point. |
| 18 | * rmb() prevents loads being reordered across this point. |
| 19 | * wmb() prevents stores being reordered across this point. |
| 20 | */ |
| 21 | #define mb() barrier() |
| 22 | #define rmb() mb() |
| 23 | #define wmb() mb() |
| 24 | |
| 25 | /** |
| 26 | * read_barrier_depends - Flush all pending reads that subsequents reads |
| 27 | * depend on. |
| 28 | * |
| 29 | * No data-dependent reads from memory-like regions are ever reordered |
| 30 | * over this barrier. All reads preceding this primitive are guaranteed |
| 31 | * to access memory (but not necessarily other CPUs' caches) before any |
| 32 | * reads following this primitive that depend on the data return by |
| 33 | * any of the preceding reads. This primitive is much lighter weight than |
| 34 | * rmb() on most CPUs, and is never heavier weight than is |
| 35 | * rmb(). |
| 36 | * |
| 37 | * These ordering constraints are respected by both the local CPU |
| 38 | * and the compiler. |
| 39 | * |
| 40 | * Ordering is not guaranteed by anything other than these primitives, |
| 41 | * not even by data dependencies. See the documentation for |
| 42 | * memory_barrier() for examples and URLs to more information. |
| 43 | * |
| 44 | * For example, the following code would force ordering (the initial |
| 45 | * value of "a" is zero, "b" is one, and "p" is "&a"): |
| 46 | * |
| 47 | * <programlisting> |
| 48 | * CPU 0 CPU 1 |
| 49 | * |
| 50 | * b = 2; |
| 51 | * memory_barrier(); |
| 52 | * p = &b; q = p; |
| 53 | * read_barrier_depends(); |
| 54 | * d = *q; |
| 55 | * </programlisting> |
| 56 | * |
| 57 | * |
| 58 | * because the read of "*q" depends on the read of "p" and these |
| 59 | * two reads are separated by a read_barrier_depends(). However, |
| 60 | * the following code, with the same initial values for "a" and "b": |
| 61 | * |
| 62 | * <programlisting> |
| 63 | * CPU 0 CPU 1 |
| 64 | * |
| 65 | * a = 2; |
| 66 | * memory_barrier(); |
| 67 | * b = 3; y = b; |
| 68 | * read_barrier_depends(); |
| 69 | * x = a; |
| 70 | * </programlisting> |
| 71 | * |
| 72 | * does not enforce ordering, since there is no data dependency between |
| 73 | * the read of "a" and the read of "b". Therefore, on some CPUs, such |
| 74 | * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() |
| 75 | * in cases like this where there are no data dependencies. |
| 76 | **/ |
| 77 | |
| 78 | #define read_barrier_depends() do { } while (0) |
| 79 | |
| 80 | #ifdef CONFIG_SMP |
| 81 | #define smp_mb() mb() |
| 82 | #define smp_rmb() rmb() |
| 83 | #define smp_wmb() wmb() |
| 84 | #define smp_read_barrier_depends() read_barrier_depends() |
| 85 | #define set_mb(var, value) do { (void) xchg(&var, value); } while (0) |
| 86 | #else |
| 87 | #define smp_mb() barrier() |
| 88 | #define smp_rmb() barrier() |
| 89 | #define smp_wmb() barrier() |
| 90 | #define smp_read_barrier_depends() do { } while (0) |
| 91 | #define set_mb(var, value) do { var = value; barrier(); } while (0) |
| 92 | #endif |
| 93 | |
| 94 | #endif /* _ASM_M32R_BARRIER_H */ |