blob: ada36057d7cde4727653cf783b165d707d752e86 [file] [log] [blame]
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001/*
2 * QLogic Fibre Channel HBA Driver
Armen Baloyanbd21eaf2014-04-11 16:54:24 -04003 * Copyright (c) 2003-2014 QLogic Corporation
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04004 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7
8#ifndef __QLA_NX2_H
9#define __QLA_NX2_H
10
11#define QSNT_ACK_TOV 30
12#define INTENT_TO_RECOVER 0x01
13#define PROCEED_TO_RECOVER 0x02
14#define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C
15#define IDC_LOCK_RECOVERY_STATE_MASK 0x3
16#define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS 2
17
18#define QLA8044_DRV_LOCK_MSLEEP 200
19#define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL)
20#define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
21
22#define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
23#define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
24#define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
25#define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
26#define MD_MIU_TEST_AGT_RDDATA_LO 0x410000A8
27#define MD_MIU_TEST_AGT_RDDATA_HI 0x410000AC
28#define MD_MIU_TEST_AGT_RDDATA_ULO 0x410000B8
29#define MD_MIU_TEST_AGT_RDDATA_UHI 0x410000BC
30
31/* MIU_TEST_AGT_CTRL flags. work for SIU as well */
32#define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
33#define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \
34 MIU_TA_CTL_START)
35#define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
36
37/* Imbus address bit used to indicate a host address. This bit is
38 * eliminated by the pcie bar and bar select before presentation
39 * over pcie. */
40/* host memory via IMBUS */
41#define QLA8044_P2_ADDR_PCIE (0x0000000800000000ULL)
42#define QLA8044_P3_ADDR_PCIE (0x0000008000000000ULL)
43#define QLA8044_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
44#define QLA8044_ADDR_OCM0 (0x0000000200000000ULL)
45#define QLA8044_ADDR_OCM0_MAX (0x00000002000fffffULL)
46#define QLA8044_ADDR_OCM1 (0x0000000200400000ULL)
47#define QLA8044_ADDR_OCM1_MAX (0x00000002004fffffULL)
48#define QLA8044_ADDR_QDR_NET (0x0000000300000000ULL)
49#define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
50#define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
51#define QLA8044_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
52#define QLA8044_PCI_CRBSPACE ((unsigned long)0x06000000)
53#define QLA8044_PCI_DIRECT_CRB ((unsigned long)0x04400000)
54#define QLA8044_PCI_CAMQM ((unsigned long)0x04800000)
55#define QLA8044_PCI_CAMQM_MAX ((unsigned long)0x04ffffff)
56#define QLA8044_PCI_DDR_NET ((unsigned long)0x00000000)
57#define QLA8044_PCI_QDR_NET ((unsigned long)0x04000000)
58#define QLA8044_PCI_QDR_NET_MAX ((unsigned long)0x043fffff)
59
60/* PCI Windowing for DDR regions. */
61#define QLA8044_ADDR_IN_RANGE(addr, low, high) \
62 (((addr) <= (high)) && ((addr) >= (low)))
63
64/* Indirectly Mapped Registers */
65#define QLA8044_FLASH_SPI_STATUS 0x2808E010
66#define QLA8044_FLASH_SPI_CONTROL 0x2808E014
67#define QLA8044_FLASH_STATUS 0x42100004
68#define QLA8044_FLASH_CONTROL 0x42110004
69#define QLA8044_FLASH_ADDR 0x42110008
70#define QLA8044_FLASH_WRDATA 0x4211000C
71#define QLA8044_FLASH_RDDATA 0x42110018
72#define QLA8044_FLASH_DIRECT_WINDOW 0x42110030
73#define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
74
75/* Flash access regs */
76#define QLA8044_FLASH_LOCK 0x3850
77#define QLA8044_FLASH_UNLOCK 0x3854
78#define QLA8044_FLASH_LOCK_ID 0x3500
79
80/* Driver Lock regs */
81#define QLA8044_DRV_LOCK 0x3868
82#define QLA8044_DRV_UNLOCK 0x386C
83#define QLA8044_DRV_LOCK_ID 0x3504
84#define QLA8044_DRV_LOCKRECOVERY 0x379C
85
86/* IDC version */
87#define QLA8044_IDC_VER_MAJ_VALUE 0x1
88#define QLA8044_IDC_VER_MIN_VALUE 0x0
89
90/* IDC Registers : Driver Coexistence Defines */
91#define QLA8044_CRB_IDC_VER_MAJOR 0x3780
92#define QLA8044_CRB_IDC_VER_MINOR 0x3798
93#define QLA8044_IDC_DRV_AUDIT 0x3794
94#define QLA8044_SRE_SHIM_CONTROL 0x0D200284
95#define QLA8044_PORT0_RXB_PAUSE_THRS 0x0B2003A4
96#define QLA8044_PORT1_RXB_PAUSE_THRS 0x0B2013A4
97#define QLA8044_PORT0_RXB_TC_MAX_CELL 0x0B200388
98#define QLA8044_PORT1_RXB_TC_MAX_CELL 0x0B201388
99#define QLA8044_PORT0_RXB_TC_STATS 0x0B20039C
100#define QLA8044_PORT1_RXB_TC_STATS 0x0B20139C
101#define QLA8044_PORT2_IFB_PAUSE_THRS 0x0B200704
102#define QLA8044_PORT3_IFB_PAUSE_THRS 0x0B201704
103
104/* set value to pause threshold value */
105#define QLA8044_SET_PAUSE_VAL 0x0
106#define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF
107#define QLA8044_PEG_HALT_STATUS1 0x34A8
108#define QLA8044_PEG_HALT_STATUS2 0x34AC
109#define QLA8044_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
110#define QLA8044_FW_CAPABILITIES 0x3528
111#define QLA8044_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
112#define QLA8044_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
113#define QLA8044_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
114#define QLA8044_CRB_DRV_SCRATCH 0x3548
115#define QLA8044_CRB_DEV_PART_INFO1 0x37E0
116#define QLA8044_CRB_DEV_PART_INFO2 0x37E4
117#define QLA8044_FW_VER_MAJOR 0x3550
118#define QLA8044_FW_VER_MINOR 0x3554
119#define QLA8044_FW_VER_SUB 0x3558
120#define QLA8044_NPAR_STATE 0x359C
121#define QLA8044_FW_IMAGE_VALID 0x35FC
122#define QLA8044_CMDPEG_STATE 0x3650
123#define QLA8044_ASIC_TEMP 0x37B4
124#define QLA8044_FW_API 0x356C
125#define QLA8044_DRV_OP_MODE 0x3570
126#define QLA8044_CRB_WIN_BASE 0x3800
127#define QLA8044_CRB_WIN_FUNC(f) (QLA8044_CRB_WIN_BASE+((f)*4))
128#define QLA8044_SEM_LOCK_BASE 0x3840
129#define QLA8044_SEM_UNLOCK_BASE 0x3844
130#define QLA8044_SEM_LOCK_FUNC(f) (QLA8044_SEM_LOCK_BASE+((f)*8))
131#define QLA8044_SEM_UNLOCK_FUNC(f) (QLA8044_SEM_UNLOCK_BASE+((f)*8))
132#define QLA8044_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
133#define QLA8044_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
134#define QLA8044_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
135#define QLA8044_LINK_SPEED_FACTOR 10
Hiral Patela018d8f2014-04-11 16:54:34 -0400136#define QLA8044_FUN7_ACTIVE_INDEX 0x80
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400137
138/* FLASH API Defines */
139#define QLA8044_FLASH_MAX_WAIT_USEC 100
140#define QLA8044_FLASH_LOCK_TIMEOUT 10000
141#define QLA8044_FLASH_SECTOR_SIZE 65536
142#define QLA8044_DRV_LOCK_TIMEOUT 2000
143#define QLA8044_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
144#define QLA8044_FLASH_WRITE_CMD 0xdacdacda
145#define QLA8044_FLASH_BUFFER_WRITE_CMD 0xcadcadca
146#define QLA8044_FLASH_READ_RETRY_COUNT 2000
147#define QLA8044_FLASH_STATUS_READY 0x6
148#define QLA8044_FLASH_BUFFER_WRITE_MIN 2
149#define QLA8044_FLASH_BUFFER_WRITE_MAX 64
150#define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1
151#define QLA8044_ERASE_MODE 1
152#define QLA8044_WRITE_MODE 2
153#define QLA8044_DWORD_WRITE_MODE 3
154#define QLA8044_GLOBAL_RESET 0x38CC
155#define QLA8044_WILDCARD 0x38F0
156#define QLA8044_INFORMANT 0x38FC
157#define QLA8044_HOST_MBX_CTRL 0x3038
158#define QLA8044_FW_MBX_CTRL 0x303C
159#define QLA8044_BOOTLOADER_ADDR 0x355C
160#define QLA8044_BOOTLOADER_SIZE 0x3560
161#define QLA8044_FW_IMAGE_ADDR 0x3564
162#define QLA8044_MBX_INTR_ENABLE 0x1000
163#define QLA8044_MBX_INTR_MASK 0x1200
164
165/* IDC Control Register bit defines */
166#define DONTRESET_BIT0 0x1
167#define GRACEFUL_RESET_BIT1 0x2
168
169/* ISP8044 PEG_HALT_STATUS1 bits */
170#define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
171#define QLA8044_HALT_STATUS_FW_RESET (0x2 << 29)
172#define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
173
174/* Firmware image definitions */
175#define QLA8044_BOOTLOADER_FLASH_ADDR 0x10000
176#define QLA8044_BOOT_FROM_FLASH 0
177#define QLA8044_IDC_PARAM_ADDR 0x3e8020
178
179/* FLASH related definitions */
180#define QLA8044_OPTROM_BURST_SIZE 0x100
181#define QLA8044_MAX_OPTROM_BURST_DWORDS (QLA8044_OPTROM_BURST_SIZE / 4)
182#define QLA8044_MIN_OPTROM_BURST_DWORDS 2
183#define QLA8044_SECTOR_SIZE (64 * 1024)
184
185#define QLA8044_FLASH_SPI_CTL 0x4
186#define QLA8044_FLASH_FIRST_TEMP_VAL 0x00800000
187#define QLA8044_FLASH_SECOND_TEMP_VAL 0x00800001
188#define QLA8044_FLASH_FIRST_MS_PATTERN 0x43
189#define QLA8044_FLASH_SECOND_MS_PATTERN 0x7F
190#define QLA8044_FLASH_LAST_MS_PATTERN 0x7D
191#define QLA8044_FLASH_STATUS_WRITE_DEF_SIG 0xFD0100
192#define QLA8044_FLASH_SECOND_ERASE_MS_VAL 0x5
193#define QLA8044_FLASH_ERASE_SIG 0xFD0300
194#define QLA8044_FLASH_LAST_ERASE_MS_VAL 0x3D
195
196/* Reset template definitions */
197#define QLA8044_MAX_RESET_SEQ_ENTRIES 16
198#define QLA8044_RESTART_TEMPLATE_SIZE 0x2000
199#define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000
200#define QLA8044_RESET_SEQ_VERSION 0x0101
201
202/* Reset template entry opcodes */
203#define OPCODE_NOP 0x0000
204#define OPCODE_WRITE_LIST 0x0001
205#define OPCODE_READ_WRITE_LIST 0x0002
206#define OPCODE_POLL_LIST 0x0004
207#define OPCODE_POLL_WRITE_LIST 0x0008
208#define OPCODE_READ_MODIFY_WRITE 0x0010
209#define OPCODE_SEQ_PAUSE 0x0020
210#define OPCODE_SEQ_END 0x0040
211#define OPCODE_TMPL_END 0x0080
212#define OPCODE_POLL_READ_LIST 0x0100
213
214/* Template Header */
215#define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
216#define QLA8044_IDC_DRV_CTRL 0x3790
217#define AF_8044_NO_FW_DUMP 27 /* 0x08000000 */
218
219#define MINIDUMP_SIZE_36K 36864
220
221struct qla8044_reset_template_hdr {
222 uint16_t version;
223 uint16_t signature;
224 uint16_t size;
225 uint16_t entries;
226 uint16_t hdr_size;
227 uint16_t checksum;
228 uint16_t init_seq_offset;
229 uint16_t start_seq_offset;
230} __packed;
231
232/* Common Entry Header. */
233struct qla8044_reset_entry_hdr {
234 uint16_t cmd;
235 uint16_t size;
236 uint16_t count;
237 uint16_t delay;
238} __packed;
239
240/* Generic poll entry type. */
241struct qla8044_poll {
242 uint32_t test_mask;
243 uint32_t test_value;
244} __packed;
245
246/* Read modify write entry type. */
247struct qla8044_rmw {
248 uint32_t test_mask;
249 uint32_t xor_value;
250 uint32_t or_value;
251 uint8_t shl;
252 uint8_t shr;
253 uint8_t index_a;
254 uint8_t rsvd;
255} __packed;
256
257/* Generic Entry Item with 2 DWords. */
258struct qla8044_entry {
259 uint32_t arg1;
260 uint32_t arg2;
261} __packed;
262
263/* Generic Entry Item with 4 DWords.*/
264struct qla8044_quad_entry {
265 uint32_t dr_addr;
266 uint32_t dr_value;
267 uint32_t ar_addr;
268 uint32_t ar_value;
269} __packed;
270
271struct qla8044_reset_template {
272 int seq_index;
273 int seq_error;
274 int array_index;
275 uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
276 uint8_t *buff;
277 uint8_t *stop_offset;
278 uint8_t *start_offset;
279 uint8_t *init_offset;
280 struct qla8044_reset_template_hdr *hdr;
281 uint8_t seq_end;
282 uint8_t template_end;
283};
284
285/* Driver_code is for driver to write some info about the entry
286 * currently not used.
287 */
288struct qla8044_minidump_entry_hdr {
289 uint32_t entry_type;
290 uint32_t entry_size;
291 uint32_t entry_capture_size;
292 struct {
293 uint8_t entry_capture_mask;
294 uint8_t entry_code;
295 uint8_t driver_code;
296 uint8_t driver_flags;
297 } d_ctrl;
298} __packed;
299
300/* Read CRB entry header */
301struct qla8044_minidump_entry_crb {
302 struct qla8044_minidump_entry_hdr h;
303 uint32_t addr;
304 struct {
305 uint8_t addr_stride;
306 uint8_t state_index_a;
307 uint16_t poll_timeout;
308 } crb_strd;
309 uint32_t data_size;
310 uint32_t op_count;
311
312 struct {
313 uint8_t opcode;
314 uint8_t state_index_v;
315 uint8_t shl;
316 uint8_t shr;
317 } crb_ctrl;
318
319 uint32_t value_1;
320 uint32_t value_2;
321 uint32_t value_3;
322} __packed;
323
324struct qla8044_minidump_entry_cache {
325 struct qla8044_minidump_entry_hdr h;
326 uint32_t tag_reg_addr;
327 struct {
328 uint16_t tag_value_stride;
329 uint16_t init_tag_value;
330 } addr_ctrl;
331 uint32_t data_size;
332 uint32_t op_count;
333 uint32_t control_addr;
334 struct {
335 uint16_t write_value;
336 uint8_t poll_mask;
337 uint8_t poll_wait;
338 } cache_ctrl;
339 uint32_t read_addr;
340 struct {
341 uint8_t read_addr_stride;
342 uint8_t read_addr_cnt;
343 uint16_t rsvd_1;
344 } read_ctrl;
345} __packed;
346
347/* Read OCM */
348struct qla8044_minidump_entry_rdocm {
349 struct qla8044_minidump_entry_hdr h;
350 uint32_t rsvd_0;
351 uint32_t rsvd_1;
352 uint32_t data_size;
353 uint32_t op_count;
354 uint32_t rsvd_2;
355 uint32_t rsvd_3;
356 uint32_t read_addr;
357 uint32_t read_addr_stride;
358} __packed;
359
360/* Read Memory */
361struct qla8044_minidump_entry_rdmem {
362 struct qla8044_minidump_entry_hdr h;
363 uint32_t rsvd[6];
364 uint32_t read_addr;
365 uint32_t read_data_size;
366};
367
368/* Read Memory: For Pex-DMA */
369struct qla8044_minidump_entry_rdmem_pex_dma {
370 struct qla8044_minidump_entry_hdr h;
371 uint32_t desc_card_addr;
372 uint16_t dma_desc_cmd;
373 uint8_t rsvd[2];
374 uint32_t start_dma_cmd;
375 uint8_t rsvd2[12];
376 uint32_t read_addr;
377 uint32_t read_data_size;
378} __packed;
379
380/* Read ROM */
381struct qla8044_minidump_entry_rdrom {
382 struct qla8044_minidump_entry_hdr h;
383 uint32_t rsvd[6];
384 uint32_t read_addr;
385 uint32_t read_data_size;
386} __packed;
387
388/* Mux entry */
389struct qla8044_minidump_entry_mux {
390 struct qla8044_minidump_entry_hdr h;
391 uint32_t select_addr;
392 uint32_t rsvd_0;
393 uint32_t data_size;
394 uint32_t op_count;
395 uint32_t select_value;
396 uint32_t select_value_stride;
397 uint32_t read_addr;
398 uint32_t rsvd_1;
399} __packed;
400
401/* Queue entry */
402struct qla8044_minidump_entry_queue {
403 struct qla8044_minidump_entry_hdr h;
404 uint32_t select_addr;
405 struct {
406 uint16_t queue_id_stride;
407 uint16_t rsvd_0;
408 } q_strd;
409 uint32_t data_size;
410 uint32_t op_count;
411 uint32_t rsvd_1;
412 uint32_t rsvd_2;
413 uint32_t read_addr;
414 struct {
415 uint8_t read_addr_stride;
416 uint8_t read_addr_cnt;
417 uint16_t rsvd_3;
418 } rd_strd;
419} __packed;
420
421/* POLLRD Entry */
422struct qla8044_minidump_entry_pollrd {
423 struct qla8044_minidump_entry_hdr h;
424 uint32_t select_addr;
425 uint32_t read_addr;
426 uint32_t select_value;
427 uint16_t select_value_stride;
428 uint16_t op_count;
429 uint32_t poll_wait;
430 uint32_t poll_mask;
431 uint32_t data_size;
432 uint32_t rsvd_1;
433} __packed;
434
Pratik Mohanty804df802014-04-11 16:54:15 -0400435struct qla8044_minidump_entry_rddfe {
436 struct qla8044_minidump_entry_hdr h;
437 uint32_t addr_1;
438 uint32_t value;
439 uint8_t stride;
440 uint8_t stride2;
441 uint16_t count;
442 uint32_t poll;
443 uint32_t mask;
444 uint32_t modify_mask;
445 uint32_t data_size;
446 uint32_t rsvd;
447
448} __packed;
449
450struct qla8044_minidump_entry_rdmdio {
451 struct qla8044_minidump_entry_hdr h;
452
453 uint32_t addr_1;
454 uint32_t addr_2;
455 uint32_t value_1;
456 uint8_t stride_1;
457 uint8_t stride_2;
458 uint16_t count;
459 uint32_t poll;
460 uint32_t mask;
461 uint32_t value_2;
462 uint32_t data_size;
463
464} __packed;
465
466struct qla8044_minidump_entry_pollwr {
467 struct qla8044_minidump_entry_hdr h;
468 uint32_t addr_1;
469 uint32_t addr_2;
470 uint32_t value_1;
471 uint32_t value_2;
472 uint32_t poll;
473 uint32_t mask;
474 uint32_t data_size;
475 uint32_t rsvd;
476
477} __packed;
478
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400479/* RDMUX2 Entry */
480struct qla8044_minidump_entry_rdmux2 {
481 struct qla8044_minidump_entry_hdr h;
482 uint32_t select_addr_1;
483 uint32_t select_addr_2;
484 uint32_t select_value_1;
485 uint32_t select_value_2;
486 uint32_t op_count;
487 uint32_t select_value_mask;
488 uint32_t read_addr;
489 uint8_t select_value_stride;
490 uint8_t data_size;
491 uint8_t rsvd[2];
492} __packed;
493
494/* POLLRDMWR Entry */
495struct qla8044_minidump_entry_pollrdmwr {
496 struct qla8044_minidump_entry_hdr h;
497 uint32_t addr_1;
498 uint32_t addr_2;
499 uint32_t value_1;
500 uint32_t value_2;
501 uint32_t poll_wait;
502 uint32_t poll_mask;
503 uint32_t modify_mask;
504 uint32_t data_size;
505} __packed;
506
507/* IDC additional information */
508struct qla8044_idc_information {
509 uint32_t request_desc; /* IDC request descriptor */
510 uint32_t info1; /* IDC additional info */
511 uint32_t info2; /* IDC additional info */
512 uint32_t info3; /* IDC additional info */
513} __packed;
514
515enum qla_regs {
516 QLA8044_PEG_HALT_STATUS1_INDEX = 0,
517 QLA8044_PEG_HALT_STATUS2_INDEX,
518 QLA8044_PEG_ALIVE_COUNTER_INDEX,
519 QLA8044_CRB_DRV_ACTIVE_INDEX,
520 QLA8044_CRB_DEV_STATE_INDEX,
521 QLA8044_CRB_DRV_STATE_INDEX,
522 QLA8044_CRB_DRV_SCRATCH_INDEX,
523 QLA8044_CRB_DEV_PART_INFO_INDEX,
524 QLA8044_CRB_DRV_IDC_VERSION_INDEX,
525 QLA8044_FW_VERSION_MAJOR_INDEX,
526 QLA8044_FW_VERSION_MINOR_INDEX,
527 QLA8044_FW_VERSION_SUB_INDEX,
528 QLA8044_CRB_CMDPEG_STATE_INDEX,
529 QLA8044_CRB_TEMP_STATE_INDEX,
530} __packed;
531
532#define CRB_REG_INDEX_MAX 14
533#define CRB_CMDPEG_CHECK_RETRY_COUNT 60
534#define CRB_CMDPEG_CHECK_DELAY 500
535
536static const uint32_t qla8044_reg_tbl[] = {
537 QLA8044_PEG_HALT_STATUS1,
538 QLA8044_PEG_HALT_STATUS2,
539 QLA8044_PEG_ALIVE_COUNTER,
540 QLA8044_CRB_DRV_ACTIVE,
541 QLA8044_CRB_DEV_STATE,
542 QLA8044_CRB_DRV_STATE,
543 QLA8044_CRB_DRV_SCRATCH,
544 QLA8044_CRB_DEV_PART_INFO1,
545 QLA8044_CRB_IDC_VER_MAJOR,
546 QLA8044_FW_VER_MAJOR,
547 QLA8044_FW_VER_MINOR,
548 QLA8044_FW_VER_SUB,
549 QLA8044_CMDPEG_STATE,
550 QLA8044_ASIC_TEMP,
551};
552
553/* MiniDump Structures */
554
555/* Driver_code is for driver to write some info about the entry
556 * currently not used.
557 */
558#define QLA8044_SS_OCM_WNDREG_INDEX 3
559#define QLA8044_DBG_STATE_ARRAY_LEN 16
560#define QLA8044_DBG_CAP_SIZE_ARRAY_LEN 8
561#define QLA8044_DBG_RSVD_ARRAY_LEN 8
562#define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN 16
563#define QLA8044_SS_PCI_INDEX 0
Pratik Mohanty804df802014-04-11 16:54:15 -0400564#define QLA8044_RDDFE 38
565#define QLA8044_RDMDIO 39
566#define QLA8044_POLLWR 40
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400567
568struct qla8044_minidump_template_hdr {
569 uint32_t entry_type;
570 uint32_t first_entry_offset;
571 uint32_t size_of_template;
572 uint32_t capture_debug_level;
573 uint32_t num_of_entries;
574 uint32_t version;
575 uint32_t driver_timestamp;
576 uint32_t checksum;
577
578 uint32_t driver_capture_mask;
579 uint32_t driver_info_word2;
580 uint32_t driver_info_word3;
581 uint32_t driver_info_word4;
582
583 uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
584 uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
585 uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
586};
587
588struct qla8044_pex_dma_descriptor {
589 struct {
590 uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
591 uint8_t rsvd[2];
592 uint16_t dma_desc_cmd;
593 } cmd;
594 uint64_t src_addr;
595 uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/
596 uint8_t rsvd[24];
597} __packed;
598
599#endif