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H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_MCE_H
2#define _ASM_X86_MCE_H
Thomas Gleixnere2f43022007-10-17 18:04:40 +02003
David Howellsaf170c52012-12-14 22:37:13 +00004#include <uapi/asm/mce.h>
Thomas Gleixnere2f43022007-10-17 18:04:40 +02005
Borislav Petkovf51bde62012-12-21 17:03:58 +01006/*
7 * Machine Check support for x86
8 */
9
10/* MCG_CAP register defines */
11#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
12#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
13#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
14#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
15#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
16#define MCG_EXT_CNT_SHIFT 16
17#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
Chen, Gong4b3db702013-10-21 14:29:25 -070019#define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */
Ashok Rajbc12edb2015-06-04 18:55:22 +020020#define MCG_LMCE_P (1ULL<<27) /* Local machine check supported */
Borislav Petkovf51bde62012-12-21 17:03:58 +010021
22/* MCG_STATUS register defines */
23#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
24#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
25#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
Ashok Rajbc12edb2015-06-04 18:55:22 +020026#define MCG_STATUS_LMCES (1ULL<<3) /* LMCE signaled */
27
28/* MCG_EXT_CTL register defines */
29#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
Borislav Petkovf51bde62012-12-21 17:03:58 +010030
31/* MCi_STATUS register defines */
32#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
33#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
34#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
35#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
36#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
37#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
38#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
39#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
40#define MCI_STATUS_AR (1ULL<<55) /* Action required */
Tony Luck0ca06c02013-07-24 13:54:20 -070041
Chen Yuconge3480272014-11-18 10:09:19 +080042/* AMD-specific bits */
Aravind Gopalakrishnan2cd3b5f2016-03-07 14:02:20 +010043#define MCI_STATUS_DEFERRED (1ULL<<44) /* uncorrected error, deferred exception */
Chen Yuconge3480272014-11-18 10:09:19 +080044#define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */
Aravind Gopalakrishnanbe0aec22016-03-07 14:02:18 +010045#define MCI_STATUS_TCC (1ULL<<55) /* Task context corrupt */
46
47/*
48 * McaX field if set indicates a given bank supports MCA extensions:
49 * - Deferred error interrupt type is specifiable by bank.
50 * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
51 * But should not be used to determine MSR numbers.
52 * - TCC bit is present in MCx_STATUS.
53 */
54#define MCI_CONFIG_MCAX 0x1
55#define MCI_IPID_MCATYPE 0xFFFF0000
56#define MCI_IPID_HWID 0xFFF
Chen Yuconge3480272014-11-18 10:09:19 +080057
Tony Luck0ca06c02013-07-24 13:54:20 -070058/*
59 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
60 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected
61 * errors to indicate that errors are being filtered by hardware.
62 * We should mask out bit 12 when looking for specific signatures
63 * of uncorrected errors - so the F bit is deliberately skipped
64 * in this #define.
65 */
66#define MCACOD 0xefff /* MCA Error Code */
Borislav Petkovf51bde62012-12-21 17:03:58 +010067
68/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
69#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
Tony Luck0ca06c02013-07-24 13:54:20 -070070#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
Borislav Petkovf51bde62012-12-21 17:03:58 +010071#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
72#define MCACOD_DATA 0x0134 /* Data Load */
73#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
74
75/* MCi_MISC register defines */
76#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
77#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
78#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
79#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
80#define MCI_MISC_ADDR_PHYS 2 /* physical address */
81#define MCI_MISC_ADDR_MEM 3 /* memory address */
82#define MCI_MISC_ADDR_GENERIC 7 /* generic */
83
84/* CTL2 register defines */
85#define MCI_CTL2_CMCI_EN (1ULL << 30)
86#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
87
88#define MCJ_CTX_MASK 3
89#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
90#define MCJ_CTX_RANDOM 0 /* inject context: random */
91#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
92#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
93#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
94#define MCJ_EXCEPTION 0x8 /* raise as exception */
Mathias Krausea9093682013-06-04 20:54:14 +020095#define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
Borislav Petkovf51bde62012-12-21 17:03:58 +010096
97#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
98
99/* Software defined banks */
100#define MCE_EXTENDED_BANK 128
101#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
Borislav Petkovf51bde62012-12-21 17:03:58 +0100102
103#define MCE_LOG_LEN 32
104#define MCE_LOG_SIGNATURE "MACHINECHECK"
105
Aravind Gopalakrishnanadc53f22016-03-07 14:02:17 +0100106/* AMD Scalable MCA */
Aravind Gopalakrishnan8dd1e172016-03-07 14:02:19 +0100107#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
Aravind Gopalakrishnanadc53f22016-03-07 14:02:17 +0100108#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
Aravind Gopalakrishnanbe0aec22016-03-07 14:02:18 +0100109#define MSR_AMD64_SMCA_MC0_IPID 0xc0002005
Aravind Gopalakrishnan8dd1e172016-03-07 14:02:19 +0100110#define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a
111#define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
Aravind Gopalakrishnanadc53f22016-03-07 14:02:17 +0100112#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
Aravind Gopalakrishnanbe0aec22016-03-07 14:02:18 +0100113#define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
Aravind Gopalakrishnan8dd1e172016-03-07 14:02:19 +0100114#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
Aravind Gopalakrishnanadc53f22016-03-07 14:02:17 +0100115
Borislav Petkovf51bde62012-12-21 17:03:58 +0100116/*
117 * This structure contains all data related to the MCE log. Also
118 * carries a signature to make it easier to find from external
119 * debugging tools. Each entry is only valid when its finished flag
120 * is set.
121 */
122struct mce_log {
123 char signature[12]; /* "MACHINECHECK" */
124 unsigned len; /* = MCE_LOG_LEN */
125 unsigned next;
126 unsigned flags;
127 unsigned recordlen; /* length of struct mce */
128 struct mce entry[MCE_LOG_LEN];
129};
Borislav Petkovd203f0b2012-10-15 18:03:57 +0200130
131struct mca_config {
132 bool dont_log_ce;
Borislav Petkov7af19e42012-10-15 20:25:17 +0200133 bool cmci_disabled;
Ashok Raj88d53862015-06-04 18:55:23 +0200134 bool lmce_disabled;
Borislav Petkov7af19e42012-10-15 20:25:17 +0200135 bool ignore_ce;
Borislav Petkov14625942012-10-17 12:05:33 +0200136 bool disabled;
137 bool ser;
Tony Luck0f68c082016-02-17 10:20:13 -0800138 bool recovery;
Borislav Petkov14625942012-10-17 12:05:33 +0200139 bool bios_cmci_threshold;
Borislav Petkovd203f0b2012-10-15 18:03:57 +0200140 u8 banks;
Borislav Petkov84c25592012-10-15 19:59:18 +0200141 s8 bootlog;
Borislav Petkovd203f0b2012-10-15 18:03:57 +0200142 int tolerant;
Borislav Petkov84c25592012-10-15 19:59:18 +0200143 int monarch_timeout;
Borislav Petkov7af19e42012-10-15 20:25:17 +0200144 int panic_timeout;
Borislav Petkov84c25592012-10-15 19:59:18 +0200145 u32 rip_msr;
Borislav Petkovd203f0b2012-10-15 18:03:57 +0200146};
147
Aravind Gopalakrishnanbf80bbd2015-03-23 10:42:52 -0500148struct mce_vendor_flags {
Aravind Gopalakrishnanc7f54d22015-10-30 13:11:37 +0100149 /*
150 * Indicates that overflow conditions are not fatal, when set.
151 */
152 __u64 overflow_recov : 1,
Aravind Gopalakrishnan7559e132015-05-06 06:58:55 -0500153
Aravind Gopalakrishnanc7f54d22015-10-30 13:11:37 +0100154 /*
155 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
156 * Recovery. It indicates support for data poisoning in HW and deferred
157 * error interrupts.
158 */
159 succor : 1,
160
161 /*
162 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
163 * the register space for each MCA bank and also increases number of
164 * banks. Also, to accommodate the new banks and registers, the MCA
165 * register space is moved to a new MSR range.
166 */
167 smca : 1,
168
169 __reserved_0 : 61;
Aravind Gopalakrishnanbf80bbd2015-03-23 10:42:52 -0500170};
171extern struct mce_vendor_flags mce_flags;
172
Borislav Petkov7af19e42012-10-15 20:25:17 +0200173extern struct mca_config mca_cfg;
Borislav Petkoveef4dfa2015-08-12 18:29:38 +0200174extern void mce_register_decode_chain(struct notifier_block *nb);
Borislav Petkov3653ada2011-12-04 15:12:09 +0100175extern void mce_unregister_decode_chain(struct notifier_block *nb);
Alan Coxdf39a2e2010-01-04 16:17:21 +0000176
Hidetoshi Seto9e55e442009-06-15 17:22:15 +0900177#include <linux/percpu.h>
Arun Sharma600634972011-07-26 16:09:06 -0700178#include <linux/atomic.h>
Hidetoshi Seto9e55e442009-06-15 17:22:15 +0900179
Hidetoshi Setoc6978362009-06-15 17:22:49 +0900180extern int mce_p5_enabled;
Thomas Gleixnere2f43022007-10-17 18:04:40 +0200181
Hidetoshi Seto58995d22009-06-15 17:27:47 +0900182#ifdef CONFIG_X86_MCE
Yong Wanga2202aa2009-11-10 09:38:24 +0800183int mcheck_init(void);
Borislav Petkov5e099542009-10-16 12:31:32 +0200184void mcheck_cpu_init(struct cpuinfo_x86 *c);
Ashok Raj8838eb62015-08-12 18:29:40 +0200185void mcheck_cpu_clear(struct cpuinfo_x86 *c);
Aravind Gopalakrishnan43eaa2a2015-03-23 10:42:53 -0500186void mcheck_vendor_init_severity(void);
Hidetoshi Seto58995d22009-06-15 17:27:47 +0900187#else
Yong Wanga2202aa2009-11-10 09:38:24 +0800188static inline int mcheck_init(void) { return 0; }
Borislav Petkov5e099542009-10-16 12:31:32 +0200189static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
Ashok Raj8838eb62015-08-12 18:29:40 +0200190static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
Aravind Gopalakrishnan43eaa2a2015-03-23 10:42:53 -0500191static inline void mcheck_vendor_init_severity(void) {}
Hidetoshi Seto58995d22009-06-15 17:27:47 +0900192#endif
193
Hidetoshi Seto9e55e442009-06-15 17:22:15 +0900194#ifdef CONFIG_X86_ANCIENT_MCE
195void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
196void winchip_mcheck_init(struct cpuinfo_x86 *c);
Hidetoshi Setoc6978362009-06-15 17:22:49 +0900197static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
Hidetoshi Seto9e55e442009-06-15 17:22:15 +0900198#else
199static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
200static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
Hidetoshi Setoc6978362009-06-15 17:22:49 +0900201static inline void enable_p5_mce(void) {}
Hidetoshi Seto9e55e442009-06-15 17:22:15 +0900202#endif
203
Andi Kleenb5f2fa42009-02-12 13:43:22 +0100204void mce_setup(struct mce *m);
Thomas Gleixnere2f43022007-10-17 18:04:40 +0200205void mce_log(struct mce *m);
Greg Kroah-Hartmand6126ef2012-01-26 15:49:14 -0800206DECLARE_PER_CPU(struct device *, mce_device);
Thomas Gleixnere2f43022007-10-17 18:04:40 +0200207
Andi Kleen41fdff32009-02-12 13:49:30 +0100208/*
Andi Kleen3ccdccf2009-07-09 00:31:45 +0200209 * Maximum banks number.
210 * This is the limit of the current register layout on
211 * Intel CPUs.
Andi Kleen41fdff32009-02-12 13:49:30 +0100212 */
Andi Kleen3ccdccf2009-07-09 00:31:45 +0200213#define MAX_NR_BANKS 32
Andi Kleen41fdff32009-02-12 13:49:30 +0100214
Thomas Gleixnere2f43022007-10-17 18:04:40 +0200215#ifdef CONFIG_X86_MCE_INTEL
216void mce_intel_feature_init(struct cpuinfo_x86 *c);
Ashok Raj8838eb62015-08-12 18:29:40 +0200217void mce_intel_feature_clear(struct cpuinfo_x86 *c);
Andi Kleen88ccbed2009-02-12 13:49:36 +0100218void cmci_clear(void);
219void cmci_reenable(void);
Srivatsa S. Bhat7a0c8192013-03-20 15:31:29 +0530220void cmci_rediscover(void);
Andi Kleen88ccbed2009-02-12 13:49:36 +0100221void cmci_recheck(void);
Thomas Gleixnere2f43022007-10-17 18:04:40 +0200222#else
223static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
Ashok Raj8838eb62015-08-12 18:29:40 +0200224static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
Andi Kleen88ccbed2009-02-12 13:49:36 +0100225static inline void cmci_clear(void) {}
226static inline void cmci_reenable(void) {}
Srivatsa S. Bhat7a0c8192013-03-20 15:31:29 +0530227static inline void cmci_rediscover(void) {}
Andi Kleen88ccbed2009-02-12 13:49:36 +0100228static inline void cmci_recheck(void) {}
Thomas Gleixnere2f43022007-10-17 18:04:40 +0200229#endif
230
231#ifdef CONFIG_X86_MCE_AMD
232void mce_amd_feature_init(struct cpuinfo_x86 *c);
233#else
234static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
235#endif
236
H. Peter Anvin38736072009-05-28 10:05:33 -0700237int mce_available(struct cpuinfo_x86 *c);
Andi Kleen88ccbed2009-02-12 13:49:36 +0100238
Andi Kleen01ca79f2009-05-27 21:56:52 +0200239DECLARE_PER_CPU(unsigned, mce_exception_count);
Andi Kleenca84f692009-05-27 21:56:57 +0200240DECLARE_PER_CPU(unsigned, mce_poll_count);
Andi Kleen01ca79f2009-05-27 21:56:52 +0200241
Andi Kleenee031c32009-02-12 13:49:34 +0100242typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
243DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
244
Andi Kleenb79109c2009-02-12 13:43:23 +0100245enum mcp_flags {
Borislav Petkov3f2f0682015-01-13 15:08:51 +0100246 MCP_TIMESTAMP = BIT(0), /* log time stamp */
247 MCP_UC = BIT(1), /* log uncorrected errors */
248 MCP_DONTLOG = BIT(2), /* only clear, don't log */
Andi Kleenb79109c2009-02-12 13:43:23 +0100249};
Borislav Petkov3f2f0682015-01-13 15:08:51 +0100250bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
Andi Kleenb79109c2009-02-12 13:43:23 +0100251
Andi Kleen9ff36ee2009-05-27 21:56:58 +0200252int mce_notify_irq(void);
Thomas Gleixnere2f43022007-10-17 18:04:40 +0200253
Andi Kleenea149b32009-04-29 19:31:00 +0200254DECLARE_PER_CPU(struct mce, injectm);
Luck, Tony66f5ddf2011-11-03 11:46:47 -0700255
256extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
257 const char __user *ubuf,
258 size_t usize, loff_t *off));
Andi Kleenea149b32009-04-29 19:31:00 +0200259
Naveen N. Raoc3d1fb52013-07-01 21:08:47 +0530260/* Disable CMCI/polling for MCA bank claimed by firmware */
261extern void mce_disable_bank(int bank);
262
Hidetoshi Seto58995d22009-06-15 17:27:47 +0900263/*
264 * Exception handler
265 */
266
267/* Call the installed machine check handler for this CPU setup. */
268extern void (*machine_check_vector)(struct pt_regs *, long error_code);
269void do_machine_check(struct pt_regs *, long);
270
271/*
272 * Threshold handler
273 */
Thomas Gleixnere2f43022007-10-17 18:04:40 +0200274
Andi Kleenb2762682009-02-12 13:49:31 +0100275extern void (*mce_threshold_vector)(void);
Hidetoshi Seto58995d22009-06-15 17:27:47 +0900276extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
Andi Kleenb2762682009-02-12 13:49:31 +0100277
Aravind Gopalakrishnan24fd78a2015-05-06 06:58:56 -0500278/* Deferred error interrupt handler */
279extern void (*deferred_error_int_vector)(void);
280
Hidetoshi Setoe8ce2c52009-06-15 17:24:40 +0900281/*
282 * Thermal handler
283 */
284
Hidetoshi Setoe8ce2c52009-06-15 17:24:40 +0900285void intel_init_thermal(struct cpuinfo_x86 *c);
286
Hidetoshi Setoe8ce2c52009-06-15 17:24:40 +0900287void mce_log_therm_throt_event(__u64 status);
Yong Wanga2202aa2009-11-10 09:38:24 +0800288
R, Durgadoss9e76a972011-01-03 17:22:04 +0530289/* Interrupt Handler for core thermal thresholds */
290extern int (*platform_thermal_notify)(__u64 msr_val);
291
Srinivas Pandruvada25cdce12013-05-17 23:42:01 +0000292/* Interrupt Handler for package thermal thresholds */
293extern int (*platform_thermal_package_notify)(__u64 msr_val);
294
295/* Callback support of rate control, return true, if
296 * callback has rate control */
297extern bool (*platform_thermal_package_rate_control)(void);
298
Yong Wanga2202aa2009-11-10 09:38:24 +0800299#ifdef CONFIG_X86_THERMAL_VECTOR
300extern void mcheck_intel_therm_init(void);
301#else
302static inline void mcheck_intel_therm_init(void) { }
303#endif
304
Huang Yingd334a492010-05-18 14:35:20 +0800305/*
306 * Used by APEI to report memory error via /dev/mcelog
307 */
308
309struct cper_sec_mem_err;
310extern void apei_mce_report_mem_error(int corrected,
311 struct cper_sec_mem_err *mem_err);
312
Aravind Gopalakrishnanbe0aec22016-03-07 14:02:18 +0100313/*
314 * Enumerate new IP types and HWID values in AMD processors which support
315 * Scalable MCA.
316 */
317#ifdef CONFIG_X86_MCE_AMD
318enum amd_ip_types {
319 SMCA_F17H_CORE = 0, /* Core errors */
320 SMCA_DF, /* Data Fabric */
321 SMCA_UMC, /* Unified Memory Controller */
322 SMCA_PB, /* Parameter Block */
323 SMCA_PSP, /* Platform Security Processor */
324 SMCA_SMU, /* System Management Unit */
325 N_AMD_IP_TYPES
326};
327
328struct amd_hwid {
329 const char *name;
330 unsigned int hwid;
331};
332
333extern struct amd_hwid amd_hwids[N_AMD_IP_TYPES];
334
335enum amd_core_mca_blocks {
336 SMCA_LS = 0, /* Load Store */
337 SMCA_IF, /* Instruction Fetch */
338 SMCA_L2_CACHE, /* L2 cache */
339 SMCA_DE, /* Decoder unit */
340 RES, /* Reserved */
341 SMCA_EX, /* Execution unit */
342 SMCA_FP, /* Floating Point */
343 SMCA_L3_CACHE, /* L3 cache */
344 N_CORE_MCA_BLOCKS
345};
346
347extern const char * const amd_core_mcablock_names[N_CORE_MCA_BLOCKS];
348
349enum amd_df_mca_blocks {
350 SMCA_CS = 0, /* Coherent Slave */
351 SMCA_PIE, /* Power management, Interrupts, etc */
352 N_DF_BLOCKS
353};
354
355extern const char * const amd_df_mcablock_names[N_DF_BLOCKS];
356#endif
357
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700358#endif /* _ASM_X86_MCE_H */