H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_MCE_H |
| 2 | #define _ASM_X86_MCE_H |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 3 | |
David Howells | af170c5 | 2012-12-14 22:37:13 +0000 | [diff] [blame] | 4 | #include <uapi/asm/mce.h> |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 5 | |
Borislav Petkov | f51bde6 | 2012-12-21 17:03:58 +0100 | [diff] [blame] | 6 | /* |
| 7 | * Machine Check support for x86 |
| 8 | */ |
| 9 | |
| 10 | /* MCG_CAP register defines */ |
| 11 | #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ |
| 12 | #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ |
| 13 | #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ |
| 14 | #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ |
| 15 | #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ |
| 16 | #define MCG_EXT_CNT_SHIFT 16 |
| 17 | #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) |
| 18 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ |
Chen, Gong | 4b3db70 | 2013-10-21 14:29:25 -0700 | [diff] [blame] | 19 | #define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */ |
Ashok Raj | bc12edb | 2015-06-04 18:55:22 +0200 | [diff] [blame] | 20 | #define MCG_LMCE_P (1ULL<<27) /* Local machine check supported */ |
Borislav Petkov | f51bde6 | 2012-12-21 17:03:58 +0100 | [diff] [blame] | 21 | |
| 22 | /* MCG_STATUS register defines */ |
| 23 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
| 24 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ |
| 25 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
Ashok Raj | bc12edb | 2015-06-04 18:55:22 +0200 | [diff] [blame] | 26 | #define MCG_STATUS_LMCES (1ULL<<3) /* LMCE signaled */ |
| 27 | |
| 28 | /* MCG_EXT_CTL register defines */ |
| 29 | #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */ |
Borislav Petkov | f51bde6 | 2012-12-21 17:03:58 +0100 | [diff] [blame] | 30 | |
| 31 | /* MCi_STATUS register defines */ |
| 32 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
| 33 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ |
| 34 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ |
| 35 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
| 36 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ |
| 37 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ |
| 38 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ |
| 39 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ |
| 40 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ |
Tony Luck | 0ca06c0 | 2013-07-24 13:54:20 -0700 | [diff] [blame] | 41 | |
Chen Yucong | e348027 | 2014-11-18 10:09:19 +0800 | [diff] [blame] | 42 | /* AMD-specific bits */ |
Aravind Gopalakrishnan | 2cd3b5f | 2016-03-07 14:02:20 +0100 | [diff] [blame] | 43 | #define MCI_STATUS_DEFERRED (1ULL<<44) /* uncorrected error, deferred exception */ |
Chen Yucong | e348027 | 2014-11-18 10:09:19 +0800 | [diff] [blame] | 44 | #define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */ |
Aravind Gopalakrishnan | be0aec2 | 2016-03-07 14:02:18 +0100 | [diff] [blame] | 45 | #define MCI_STATUS_TCC (1ULL<<55) /* Task context corrupt */ |
| 46 | |
| 47 | /* |
| 48 | * McaX field if set indicates a given bank supports MCA extensions: |
| 49 | * - Deferred error interrupt type is specifiable by bank. |
| 50 | * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers, |
| 51 | * But should not be used to determine MSR numbers. |
| 52 | * - TCC bit is present in MCx_STATUS. |
| 53 | */ |
| 54 | #define MCI_CONFIG_MCAX 0x1 |
| 55 | #define MCI_IPID_MCATYPE 0xFFFF0000 |
| 56 | #define MCI_IPID_HWID 0xFFF |
Chen Yucong | e348027 | 2014-11-18 10:09:19 +0800 | [diff] [blame] | 57 | |
Tony Luck | 0ca06c0 | 2013-07-24 13:54:20 -0700 | [diff] [blame] | 58 | /* |
| 59 | * Note that the full MCACOD field of IA32_MCi_STATUS MSR is |
| 60 | * bits 15:0. But bit 12 is the 'F' bit, defined for corrected |
| 61 | * errors to indicate that errors are being filtered by hardware. |
| 62 | * We should mask out bit 12 when looking for specific signatures |
| 63 | * of uncorrected errors - so the F bit is deliberately skipped |
| 64 | * in this #define. |
| 65 | */ |
| 66 | #define MCACOD 0xefff /* MCA Error Code */ |
Borislav Petkov | f51bde6 | 2012-12-21 17:03:58 +0100 | [diff] [blame] | 67 | |
| 68 | /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ |
| 69 | #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ |
Tony Luck | 0ca06c0 | 2013-07-24 13:54:20 -0700 | [diff] [blame] | 70 | #define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */ |
Borislav Petkov | f51bde6 | 2012-12-21 17:03:58 +0100 | [diff] [blame] | 71 | #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ |
| 72 | #define MCACOD_DATA 0x0134 /* Data Load */ |
| 73 | #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ |
| 74 | |
| 75 | /* MCi_MISC register defines */ |
| 76 | #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) |
| 77 | #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) |
| 78 | #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ |
| 79 | #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ |
| 80 | #define MCI_MISC_ADDR_PHYS 2 /* physical address */ |
| 81 | #define MCI_MISC_ADDR_MEM 3 /* memory address */ |
| 82 | #define MCI_MISC_ADDR_GENERIC 7 /* generic */ |
| 83 | |
| 84 | /* CTL2 register defines */ |
| 85 | #define MCI_CTL2_CMCI_EN (1ULL << 30) |
| 86 | #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL |
| 87 | |
| 88 | #define MCJ_CTX_MASK 3 |
| 89 | #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) |
| 90 | #define MCJ_CTX_RANDOM 0 /* inject context: random */ |
| 91 | #define MCJ_CTX_PROCESS 0x1 /* inject context: process */ |
| 92 | #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ |
| 93 | #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ |
| 94 | #define MCJ_EXCEPTION 0x8 /* raise as exception */ |
Mathias Krause | a909368 | 2013-06-04 20:54:14 +0200 | [diff] [blame] | 95 | #define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */ |
Borislav Petkov | f51bde6 | 2012-12-21 17:03:58 +0100 | [diff] [blame] | 96 | |
| 97 | #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ |
| 98 | |
| 99 | /* Software defined banks */ |
| 100 | #define MCE_EXTENDED_BANK 128 |
| 101 | #define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0) |
Borislav Petkov | f51bde6 | 2012-12-21 17:03:58 +0100 | [diff] [blame] | 102 | |
| 103 | #define MCE_LOG_LEN 32 |
| 104 | #define MCE_LOG_SIGNATURE "MACHINECHECK" |
| 105 | |
Aravind Gopalakrishnan | adc53f2 | 2016-03-07 14:02:17 +0100 | [diff] [blame] | 106 | /* AMD Scalable MCA */ |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 107 | #define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003 |
Aravind Gopalakrishnan | adc53f2 | 2016-03-07 14:02:17 +0100 | [diff] [blame] | 108 | #define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004 |
Aravind Gopalakrishnan | be0aec2 | 2016-03-07 14:02:18 +0100 | [diff] [blame] | 109 | #define MSR_AMD64_SMCA_MC0_IPID 0xc0002005 |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 110 | #define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a |
| 111 | #define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x)) |
Aravind Gopalakrishnan | adc53f2 | 2016-03-07 14:02:17 +0100 | [diff] [blame] | 112 | #define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x)) |
Aravind Gopalakrishnan | be0aec2 | 2016-03-07 14:02:18 +0100 | [diff] [blame] | 113 | #define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x)) |
Aravind Gopalakrishnan | 8dd1e17 | 2016-03-07 14:02:19 +0100 | [diff] [blame] | 114 | #define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x))) |
Aravind Gopalakrishnan | adc53f2 | 2016-03-07 14:02:17 +0100 | [diff] [blame] | 115 | |
Borislav Petkov | f51bde6 | 2012-12-21 17:03:58 +0100 | [diff] [blame] | 116 | /* |
| 117 | * This structure contains all data related to the MCE log. Also |
| 118 | * carries a signature to make it easier to find from external |
| 119 | * debugging tools. Each entry is only valid when its finished flag |
| 120 | * is set. |
| 121 | */ |
| 122 | struct mce_log { |
| 123 | char signature[12]; /* "MACHINECHECK" */ |
| 124 | unsigned len; /* = MCE_LOG_LEN */ |
| 125 | unsigned next; |
| 126 | unsigned flags; |
| 127 | unsigned recordlen; /* length of struct mce */ |
| 128 | struct mce entry[MCE_LOG_LEN]; |
| 129 | }; |
Borislav Petkov | d203f0b | 2012-10-15 18:03:57 +0200 | [diff] [blame] | 130 | |
| 131 | struct mca_config { |
| 132 | bool dont_log_ce; |
Borislav Petkov | 7af19e4 | 2012-10-15 20:25:17 +0200 | [diff] [blame] | 133 | bool cmci_disabled; |
Ashok Raj | 88d5386 | 2015-06-04 18:55:23 +0200 | [diff] [blame] | 134 | bool lmce_disabled; |
Borislav Petkov | 7af19e4 | 2012-10-15 20:25:17 +0200 | [diff] [blame] | 135 | bool ignore_ce; |
Borislav Petkov | 1462594 | 2012-10-17 12:05:33 +0200 | [diff] [blame] | 136 | bool disabled; |
| 137 | bool ser; |
Tony Luck | 0f68c08 | 2016-02-17 10:20:13 -0800 | [diff] [blame] | 138 | bool recovery; |
Borislav Petkov | 1462594 | 2012-10-17 12:05:33 +0200 | [diff] [blame] | 139 | bool bios_cmci_threshold; |
Borislav Petkov | d203f0b | 2012-10-15 18:03:57 +0200 | [diff] [blame] | 140 | u8 banks; |
Borislav Petkov | 84c2559 | 2012-10-15 19:59:18 +0200 | [diff] [blame] | 141 | s8 bootlog; |
Borislav Petkov | d203f0b | 2012-10-15 18:03:57 +0200 | [diff] [blame] | 142 | int tolerant; |
Borislav Petkov | 84c2559 | 2012-10-15 19:59:18 +0200 | [diff] [blame] | 143 | int monarch_timeout; |
Borislav Petkov | 7af19e4 | 2012-10-15 20:25:17 +0200 | [diff] [blame] | 144 | int panic_timeout; |
Borislav Petkov | 84c2559 | 2012-10-15 19:59:18 +0200 | [diff] [blame] | 145 | u32 rip_msr; |
Borislav Petkov | d203f0b | 2012-10-15 18:03:57 +0200 | [diff] [blame] | 146 | }; |
| 147 | |
Aravind Gopalakrishnan | bf80bbd | 2015-03-23 10:42:52 -0500 | [diff] [blame] | 148 | struct mce_vendor_flags { |
Aravind Gopalakrishnan | c7f54d2 | 2015-10-30 13:11:37 +0100 | [diff] [blame] | 149 | /* |
| 150 | * Indicates that overflow conditions are not fatal, when set. |
| 151 | */ |
| 152 | __u64 overflow_recov : 1, |
Aravind Gopalakrishnan | 7559e13 | 2015-05-06 06:58:55 -0500 | [diff] [blame] | 153 | |
Aravind Gopalakrishnan | c7f54d2 | 2015-10-30 13:11:37 +0100 | [diff] [blame] | 154 | /* |
| 155 | * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and |
| 156 | * Recovery. It indicates support for data poisoning in HW and deferred |
| 157 | * error interrupts. |
| 158 | */ |
| 159 | succor : 1, |
| 160 | |
| 161 | /* |
| 162 | * (AMD) SMCA: This bit indicates support for Scalable MCA which expands |
| 163 | * the register space for each MCA bank and also increases number of |
| 164 | * banks. Also, to accommodate the new banks and registers, the MCA |
| 165 | * register space is moved to a new MSR range. |
| 166 | */ |
| 167 | smca : 1, |
| 168 | |
| 169 | __reserved_0 : 61; |
Aravind Gopalakrishnan | bf80bbd | 2015-03-23 10:42:52 -0500 | [diff] [blame] | 170 | }; |
| 171 | extern struct mce_vendor_flags mce_flags; |
| 172 | |
Borislav Petkov | 7af19e4 | 2012-10-15 20:25:17 +0200 | [diff] [blame] | 173 | extern struct mca_config mca_cfg; |
Borislav Petkov | eef4dfa | 2015-08-12 18:29:38 +0200 | [diff] [blame] | 174 | extern void mce_register_decode_chain(struct notifier_block *nb); |
Borislav Petkov | 3653ada | 2011-12-04 15:12:09 +0100 | [diff] [blame] | 175 | extern void mce_unregister_decode_chain(struct notifier_block *nb); |
Alan Cox | df39a2e | 2010-01-04 16:17:21 +0000 | [diff] [blame] | 176 | |
Hidetoshi Seto | 9e55e44 | 2009-06-15 17:22:15 +0900 | [diff] [blame] | 177 | #include <linux/percpu.h> |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 178 | #include <linux/atomic.h> |
Hidetoshi Seto | 9e55e44 | 2009-06-15 17:22:15 +0900 | [diff] [blame] | 179 | |
Hidetoshi Seto | c697836 | 2009-06-15 17:22:49 +0900 | [diff] [blame] | 180 | extern int mce_p5_enabled; |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 181 | |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 182 | #ifdef CONFIG_X86_MCE |
Yong Wang | a2202aa | 2009-11-10 09:38:24 +0800 | [diff] [blame] | 183 | int mcheck_init(void); |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 184 | void mcheck_cpu_init(struct cpuinfo_x86 *c); |
Ashok Raj | 8838eb6 | 2015-08-12 18:29:40 +0200 | [diff] [blame] | 185 | void mcheck_cpu_clear(struct cpuinfo_x86 *c); |
Aravind Gopalakrishnan | 43eaa2a | 2015-03-23 10:42:53 -0500 | [diff] [blame] | 186 | void mcheck_vendor_init_severity(void); |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 187 | #else |
Yong Wang | a2202aa | 2009-11-10 09:38:24 +0800 | [diff] [blame] | 188 | static inline int mcheck_init(void) { return 0; } |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 189 | static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} |
Ashok Raj | 8838eb6 | 2015-08-12 18:29:40 +0200 | [diff] [blame] | 190 | static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {} |
Aravind Gopalakrishnan | 43eaa2a | 2015-03-23 10:42:53 -0500 | [diff] [blame] | 191 | static inline void mcheck_vendor_init_severity(void) {} |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 192 | #endif |
| 193 | |
Hidetoshi Seto | 9e55e44 | 2009-06-15 17:22:15 +0900 | [diff] [blame] | 194 | #ifdef CONFIG_X86_ANCIENT_MCE |
| 195 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c); |
| 196 | void winchip_mcheck_init(struct cpuinfo_x86 *c); |
Hidetoshi Seto | c697836 | 2009-06-15 17:22:49 +0900 | [diff] [blame] | 197 | static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } |
Hidetoshi Seto | 9e55e44 | 2009-06-15 17:22:15 +0900 | [diff] [blame] | 198 | #else |
| 199 | static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} |
| 200 | static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} |
Hidetoshi Seto | c697836 | 2009-06-15 17:22:49 +0900 | [diff] [blame] | 201 | static inline void enable_p5_mce(void) {} |
Hidetoshi Seto | 9e55e44 | 2009-06-15 17:22:15 +0900 | [diff] [blame] | 202 | #endif |
| 203 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 204 | void mce_setup(struct mce *m); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 205 | void mce_log(struct mce *m); |
Greg Kroah-Hartman | d6126ef | 2012-01-26 15:49:14 -0800 | [diff] [blame] | 206 | DECLARE_PER_CPU(struct device *, mce_device); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 207 | |
Andi Kleen | 41fdff3 | 2009-02-12 13:49:30 +0100 | [diff] [blame] | 208 | /* |
Andi Kleen | 3ccdccf | 2009-07-09 00:31:45 +0200 | [diff] [blame] | 209 | * Maximum banks number. |
| 210 | * This is the limit of the current register layout on |
| 211 | * Intel CPUs. |
Andi Kleen | 41fdff3 | 2009-02-12 13:49:30 +0100 | [diff] [blame] | 212 | */ |
Andi Kleen | 3ccdccf | 2009-07-09 00:31:45 +0200 | [diff] [blame] | 213 | #define MAX_NR_BANKS 32 |
Andi Kleen | 41fdff3 | 2009-02-12 13:49:30 +0100 | [diff] [blame] | 214 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 215 | #ifdef CONFIG_X86_MCE_INTEL |
| 216 | void mce_intel_feature_init(struct cpuinfo_x86 *c); |
Ashok Raj | 8838eb6 | 2015-08-12 18:29:40 +0200 | [diff] [blame] | 217 | void mce_intel_feature_clear(struct cpuinfo_x86 *c); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 218 | void cmci_clear(void); |
| 219 | void cmci_reenable(void); |
Srivatsa S. Bhat | 7a0c819 | 2013-03-20 15:31:29 +0530 | [diff] [blame] | 220 | void cmci_rediscover(void); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 221 | void cmci_recheck(void); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 222 | #else |
| 223 | static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } |
Ashok Raj | 8838eb6 | 2015-08-12 18:29:40 +0200 | [diff] [blame] | 224 | static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { } |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 225 | static inline void cmci_clear(void) {} |
| 226 | static inline void cmci_reenable(void) {} |
Srivatsa S. Bhat | 7a0c819 | 2013-03-20 15:31:29 +0530 | [diff] [blame] | 227 | static inline void cmci_rediscover(void) {} |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 228 | static inline void cmci_recheck(void) {} |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 229 | #endif |
| 230 | |
| 231 | #ifdef CONFIG_X86_MCE_AMD |
| 232 | void mce_amd_feature_init(struct cpuinfo_x86 *c); |
| 233 | #else |
| 234 | static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } |
| 235 | #endif |
| 236 | |
H. Peter Anvin | 3873607 | 2009-05-28 10:05:33 -0700 | [diff] [blame] | 237 | int mce_available(struct cpuinfo_x86 *c); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 238 | |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 239 | DECLARE_PER_CPU(unsigned, mce_exception_count); |
Andi Kleen | ca84f69 | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 240 | DECLARE_PER_CPU(unsigned, mce_poll_count); |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 241 | |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 242 | typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); |
| 243 | DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); |
| 244 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 245 | enum mcp_flags { |
Borislav Petkov | 3f2f068 | 2015-01-13 15:08:51 +0100 | [diff] [blame] | 246 | MCP_TIMESTAMP = BIT(0), /* log time stamp */ |
| 247 | MCP_UC = BIT(1), /* log uncorrected errors */ |
| 248 | MCP_DONTLOG = BIT(2), /* only clear, don't log */ |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 249 | }; |
Borislav Petkov | 3f2f068 | 2015-01-13 15:08:51 +0100 | [diff] [blame] | 250 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 251 | |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 252 | int mce_notify_irq(void); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 253 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 254 | DECLARE_PER_CPU(struct mce, injectm); |
Luck, Tony | 66f5ddf | 2011-11-03 11:46:47 -0700 | [diff] [blame] | 255 | |
| 256 | extern void register_mce_write_callback(ssize_t (*)(struct file *filp, |
| 257 | const char __user *ubuf, |
| 258 | size_t usize, loff_t *off)); |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 259 | |
Naveen N. Rao | c3d1fb5 | 2013-07-01 21:08:47 +0530 | [diff] [blame] | 260 | /* Disable CMCI/polling for MCA bank claimed by firmware */ |
| 261 | extern void mce_disable_bank(int bank); |
| 262 | |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 263 | /* |
| 264 | * Exception handler |
| 265 | */ |
| 266 | |
| 267 | /* Call the installed machine check handler for this CPU setup. */ |
| 268 | extern void (*machine_check_vector)(struct pt_regs *, long error_code); |
| 269 | void do_machine_check(struct pt_regs *, long); |
| 270 | |
| 271 | /* |
| 272 | * Threshold handler |
| 273 | */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 274 | |
Andi Kleen | b276268 | 2009-02-12 13:49:31 +0100 | [diff] [blame] | 275 | extern void (*mce_threshold_vector)(void); |
Hidetoshi Seto | 58995d2 | 2009-06-15 17:27:47 +0900 | [diff] [blame] | 276 | extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
Andi Kleen | b276268 | 2009-02-12 13:49:31 +0100 | [diff] [blame] | 277 | |
Aravind Gopalakrishnan | 24fd78a | 2015-05-06 06:58:56 -0500 | [diff] [blame] | 278 | /* Deferred error interrupt handler */ |
| 279 | extern void (*deferred_error_int_vector)(void); |
| 280 | |
Hidetoshi Seto | e8ce2c5 | 2009-06-15 17:24:40 +0900 | [diff] [blame] | 281 | /* |
| 282 | * Thermal handler |
| 283 | */ |
| 284 | |
Hidetoshi Seto | e8ce2c5 | 2009-06-15 17:24:40 +0900 | [diff] [blame] | 285 | void intel_init_thermal(struct cpuinfo_x86 *c); |
| 286 | |
Hidetoshi Seto | e8ce2c5 | 2009-06-15 17:24:40 +0900 | [diff] [blame] | 287 | void mce_log_therm_throt_event(__u64 status); |
Yong Wang | a2202aa | 2009-11-10 09:38:24 +0800 | [diff] [blame] | 288 | |
R, Durgadoss | 9e76a97 | 2011-01-03 17:22:04 +0530 | [diff] [blame] | 289 | /* Interrupt Handler for core thermal thresholds */ |
| 290 | extern int (*platform_thermal_notify)(__u64 msr_val); |
| 291 | |
Srinivas Pandruvada | 25cdce1 | 2013-05-17 23:42:01 +0000 | [diff] [blame] | 292 | /* Interrupt Handler for package thermal thresholds */ |
| 293 | extern int (*platform_thermal_package_notify)(__u64 msr_val); |
| 294 | |
| 295 | /* Callback support of rate control, return true, if |
| 296 | * callback has rate control */ |
| 297 | extern bool (*platform_thermal_package_rate_control)(void); |
| 298 | |
Yong Wang | a2202aa | 2009-11-10 09:38:24 +0800 | [diff] [blame] | 299 | #ifdef CONFIG_X86_THERMAL_VECTOR |
| 300 | extern void mcheck_intel_therm_init(void); |
| 301 | #else |
| 302 | static inline void mcheck_intel_therm_init(void) { } |
| 303 | #endif |
| 304 | |
Huang Ying | d334a49 | 2010-05-18 14:35:20 +0800 | [diff] [blame] | 305 | /* |
| 306 | * Used by APEI to report memory error via /dev/mcelog |
| 307 | */ |
| 308 | |
| 309 | struct cper_sec_mem_err; |
| 310 | extern void apei_mce_report_mem_error(int corrected, |
| 311 | struct cper_sec_mem_err *mem_err); |
| 312 | |
Aravind Gopalakrishnan | be0aec2 | 2016-03-07 14:02:18 +0100 | [diff] [blame] | 313 | /* |
| 314 | * Enumerate new IP types and HWID values in AMD processors which support |
| 315 | * Scalable MCA. |
| 316 | */ |
| 317 | #ifdef CONFIG_X86_MCE_AMD |
| 318 | enum amd_ip_types { |
| 319 | SMCA_F17H_CORE = 0, /* Core errors */ |
| 320 | SMCA_DF, /* Data Fabric */ |
| 321 | SMCA_UMC, /* Unified Memory Controller */ |
| 322 | SMCA_PB, /* Parameter Block */ |
| 323 | SMCA_PSP, /* Platform Security Processor */ |
| 324 | SMCA_SMU, /* System Management Unit */ |
| 325 | N_AMD_IP_TYPES |
| 326 | }; |
| 327 | |
| 328 | struct amd_hwid { |
| 329 | const char *name; |
| 330 | unsigned int hwid; |
| 331 | }; |
| 332 | |
| 333 | extern struct amd_hwid amd_hwids[N_AMD_IP_TYPES]; |
| 334 | |
| 335 | enum amd_core_mca_blocks { |
| 336 | SMCA_LS = 0, /* Load Store */ |
| 337 | SMCA_IF, /* Instruction Fetch */ |
| 338 | SMCA_L2_CACHE, /* L2 cache */ |
| 339 | SMCA_DE, /* Decoder unit */ |
| 340 | RES, /* Reserved */ |
| 341 | SMCA_EX, /* Execution unit */ |
| 342 | SMCA_FP, /* Floating Point */ |
| 343 | SMCA_L3_CACHE, /* L3 cache */ |
| 344 | N_CORE_MCA_BLOCKS |
| 345 | }; |
| 346 | |
| 347 | extern const char * const amd_core_mcablock_names[N_CORE_MCA_BLOCKS]; |
| 348 | |
| 349 | enum amd_df_mca_blocks { |
| 350 | SMCA_CS = 0, /* Coherent Slave */ |
| 351 | SMCA_PIE, /* Power management, Interrupts, etc */ |
| 352 | N_DF_BLOCKS |
| 353 | }; |
| 354 | |
| 355 | extern const char * const amd_df_mcablock_names[N_DF_BLOCKS]; |
| 356 | #endif |
| 357 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 358 | #endif /* _ASM_X86_MCE_H */ |