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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Ralf Baechle70342282013-01-22 12:59:30 +01002 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
Ralf Baechle27f7681922006-10-09 00:03:05 +01006 *
7 * Copyright (c) 2004 MIPS Inc
8 * Author: chris@mips.com
9 *
10 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/interrupt.h>
13#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/sched.h>
15#include <linux/kernel_stat.h>
16#include <asm/io.h>
17#include <asm/irq.h>
18#include <asm/msc01_ic.h>
Atsushi Nemoto411ba7f2008-04-26 01:55:30 +090019#include <asm/traps.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
21static unsigned long _icctrl_msc;
22#define MSC01_IC_REG_BASE _icctrl_msc
23
24#define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
25#define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0)
26
27static unsigned int irq_base;
28
29/* mask off an interrupt */
Thomas Gleixnere15883d2011-03-23 21:08:59 +000030static inline void mask_msc_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070031{
Thomas Gleixnere15883d2011-03-23 21:08:59 +000032 unsigned int irq = d->irq;
33
Linus Torvalds1da177e2005-04-16 15:20:36 -070034 if (irq < (irq_base + 32))
35 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
36 else
37 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
38}
39
40/* unmask an interrupt */
Thomas Gleixnere15883d2011-03-23 21:08:59 +000041static inline void unmask_msc_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070042{
Thomas Gleixnere15883d2011-03-23 21:08:59 +000043 unsigned int irq = d->irq;
44
Linus Torvalds1da177e2005-04-16 15:20:36 -070045 if (irq < (irq_base + 32))
46 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
47 else
48 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
49}
50
51/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070052 * Masks and ACKs an IRQ
53 */
Thomas Gleixnere15883d2011-03-23 21:08:59 +000054static void level_mask_and_ack_msc_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070055{
Thomas Gleixnere15883d2011-03-23 21:08:59 +000056 unsigned int irq = d->irq;
57
58 mask_msc_irq(d);
Ralf Baechlee01402b2005-07-14 15:57:16 +000059 if (!cpu_has_veic)
Linus Torvalds1da177e2005-04-16 15:20:36 -070060 MSCIC_WRITE(MSC01_IC_EOI, 0);
Ralf Baechle41c594a2006-04-05 09:45:45 +010061 /* This actually needs to be a call into platform code */
Ralf Baechle1146fe32007-09-21 17:13:55 +010062 smtc_im_ack_irq(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070063}
64
65/*
66 * Masks and ACKs an IRQ
67 */
Thomas Gleixnere15883d2011-03-23 21:08:59 +000068static void edge_mask_and_ack_msc_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070069{
Thomas Gleixnere15883d2011-03-23 21:08:59 +000070 unsigned int irq = d->irq;
71
72 mask_msc_irq(d);
Ralf Baechlee01402b2005-07-14 15:57:16 +000073 if (!cpu_has_veic)
Linus Torvalds1da177e2005-04-16 15:20:36 -070074 MSCIC_WRITE(MSC01_IC_EOI, 0);
75 else {
76 u32 r;
77 MSCIC_READ(MSC01_IC_SUP+irq*8, r);
78 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
79 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
80 }
Ralf Baechle1146fe32007-09-21 17:13:55 +010081 smtc_im_ack_irq(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070082}
83
84/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 * Interrupt handler for interrupts coming from SOC-it.
86 */
Ralf Baechle937a8012006-10-07 19:44:33 +010087void ll_msc_irq(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070088{
Ralf Baechle70342282013-01-22 12:59:30 +010089 unsigned int irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -070090
91 /* read the interrupt vector register */
92 MSCIC_READ(MSC01_IC_VEC, irq);
93 if (irq < 64)
Ralf Baechle937a8012006-10-07 19:44:33 +010094 do_IRQ(irq + irq_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 else {
96 /* Ignore spurious interrupt */
97 }
98}
99
Atsushi Nemoto411ba7f2008-04-26 01:55:30 +0900100static void msc_bind_eic_interrupt(int irq, int set)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101{
102 MSCIC_WRITE(MSC01_IC_RAMW,
103 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
104}
105
Atsushi Nemoto411ba7f2008-04-26 01:55:30 +0900106static struct irq_chip msc_levelirq_type = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900107 .name = "SOC-it-Level",
Thomas Gleixnere15883d2011-03-23 21:08:59 +0000108 .irq_ack = level_mask_and_ack_msc_irq,
109 .irq_mask = mask_msc_irq,
110 .irq_mask_ack = level_mask_and_ack_msc_irq,
111 .irq_unmask = unmask_msc_irq,
112 .irq_eoi = unmask_msc_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113};
114
Atsushi Nemoto411ba7f2008-04-26 01:55:30 +0900115static struct irq_chip msc_edgeirq_type = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900116 .name = "SOC-it-Edge",
Thomas Gleixnere15883d2011-03-23 21:08:59 +0000117 .irq_ack = edge_mask_and_ack_msc_irq,
118 .irq_mask = mask_msc_irq,
119 .irq_mask_ack = edge_mask_and_ack_msc_irq,
120 .irq_unmask = unmask_msc_irq,
121 .irq_eoi = unmask_msc_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122};
123
124
Chris Dearmand725cf32007-05-08 14:05:39 +0100125void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126{
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100127 _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128
129 /* Reset interrupt controller - initialises all registers to 0 */
130 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
131
132 board_bind_eic_interrupt = &msc_bind_eic_interrupt;
133
134 for (; nirq >= 0; nirq--, imp++) {
135 int n = imp->im_irq;
136
137 switch (imp->im_type) {
138 case MSC01_IRQ_EDGE:
Thomas Gleixnere4ec7982011-03-27 15:19:28 +0200139 irq_set_chip_and_handler_name(irqbase + n,
140 &msc_edgeirq_type,
141 handle_edge_irq,
142 "edge");
Ralf Baechlee01402b2005-07-14 15:57:16 +0000143 if (cpu_has_veic)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
145 else
146 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
147 break;
148 case MSC01_IRQ_LEVEL:
Thomas Gleixnere4ec7982011-03-27 15:19:28 +0200149 irq_set_chip_and_handler_name(irqbase + n,
150 &msc_levelirq_type,
151 handle_level_irq,
152 "level");
Ralf Baechlee01402b2005-07-14 15:57:16 +0000153 if (cpu_has_veic)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
155 else
156 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
157 }
158 }
159
Chris Dearmand725cf32007-05-08 14:05:39 +0100160 irq_base = irqbase;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161
162 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
163
164}