Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/ppc/syslib/mv64x60_win.c |
| 3 | * |
| 4 | * Tables with info on how to manipulate the 32 & 64 bit windows on the |
| 5 | * various types of Marvell bridge chips. |
| 6 | * |
| 7 | * Author: Mark A. Greer <mgreer@mvista.com> |
| 8 | * |
| 9 | * 2004 (c) MontaVista, Software, Inc. This file is licensed under |
| 10 | * the terms of the GNU General Public License version 2. This program |
| 11 | * is licensed "as is" without any warranty of any kind, whether express |
| 12 | * or implied. |
| 13 | */ |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/pci.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/string.h> |
| 20 | #include <linux/bootmem.h> |
| 21 | #include <linux/mv643xx.h> |
| 22 | |
| 23 | #include <asm/byteorder.h> |
| 24 | #include <asm/io.h> |
| 25 | #include <asm/irq.h> |
| 26 | #include <asm/uaccess.h> |
| 27 | #include <asm/machdep.h> |
| 28 | #include <asm/pci-bridge.h> |
| 29 | #include <asm/delay.h> |
| 30 | #include <asm/mv64x60.h> |
| 31 | |
| 32 | |
| 33 | /* |
| 34 | ***************************************************************************** |
| 35 | * |
| 36 | * Tables describing how to set up windows on each type of bridge |
| 37 | * |
| 38 | ***************************************************************************** |
| 39 | */ |
| 40 | struct mv64x60_32bit_window |
| 41 | gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT] __initdata = { |
| 42 | /* CPU->MEM Windows */ |
| 43 | [MV64x60_CPU2MEM_0_WIN] = { |
| 44 | .base_reg = MV64x60_CPU2MEM_0_BASE, |
| 45 | .size_reg = MV64x60_CPU2MEM_0_SIZE, |
| 46 | .base_bits = 12, |
| 47 | .size_bits = 12, |
| 48 | .get_from_field = mv64x60_shift_left, |
| 49 | .map_to_field = mv64x60_shift_right, |
| 50 | .extra = 0 }, |
| 51 | [MV64x60_CPU2MEM_1_WIN] = { |
| 52 | .base_reg = MV64x60_CPU2MEM_1_BASE, |
| 53 | .size_reg = MV64x60_CPU2MEM_1_SIZE, |
| 54 | .base_bits = 12, |
| 55 | .size_bits = 12, |
| 56 | .get_from_field = mv64x60_shift_left, |
| 57 | .map_to_field = mv64x60_shift_right, |
| 58 | .extra = 0 }, |
| 59 | [MV64x60_CPU2MEM_2_WIN] = { |
| 60 | .base_reg = MV64x60_CPU2MEM_2_BASE, |
| 61 | .size_reg = MV64x60_CPU2MEM_2_SIZE, |
| 62 | .base_bits = 12, |
| 63 | .size_bits = 12, |
| 64 | .get_from_field = mv64x60_shift_left, |
| 65 | .map_to_field = mv64x60_shift_right, |
| 66 | .extra = 0 }, |
| 67 | [MV64x60_CPU2MEM_3_WIN] = { |
| 68 | .base_reg = MV64x60_CPU2MEM_3_BASE, |
| 69 | .size_reg = MV64x60_CPU2MEM_3_SIZE, |
| 70 | .base_bits = 12, |
| 71 | .size_bits = 12, |
| 72 | .get_from_field = mv64x60_shift_left, |
| 73 | .map_to_field = mv64x60_shift_right, |
| 74 | .extra = 0 }, |
| 75 | /* CPU->Device Windows */ |
| 76 | [MV64x60_CPU2DEV_0_WIN] = { |
| 77 | .base_reg = MV64x60_CPU2DEV_0_BASE, |
| 78 | .size_reg = MV64x60_CPU2DEV_0_SIZE, |
| 79 | .base_bits = 12, |
| 80 | .size_bits = 12, |
| 81 | .get_from_field = mv64x60_shift_left, |
| 82 | .map_to_field = mv64x60_shift_right, |
| 83 | .extra = 0 }, |
| 84 | [MV64x60_CPU2DEV_1_WIN] = { |
| 85 | .base_reg = MV64x60_CPU2DEV_1_BASE, |
| 86 | .size_reg = MV64x60_CPU2DEV_1_SIZE, |
| 87 | .base_bits = 12, |
| 88 | .size_bits = 12, |
| 89 | .get_from_field = mv64x60_shift_left, |
| 90 | .map_to_field = mv64x60_shift_right, |
| 91 | .extra = 0 }, |
| 92 | [MV64x60_CPU2DEV_2_WIN] = { |
| 93 | .base_reg = MV64x60_CPU2DEV_2_BASE, |
| 94 | .size_reg = MV64x60_CPU2DEV_2_SIZE, |
| 95 | .base_bits = 12, |
| 96 | .size_bits = 12, |
| 97 | .get_from_field = mv64x60_shift_left, |
| 98 | .map_to_field = mv64x60_shift_right, |
| 99 | .extra = 0 }, |
| 100 | [MV64x60_CPU2DEV_3_WIN] = { |
| 101 | .base_reg = MV64x60_CPU2DEV_3_BASE, |
| 102 | .size_reg = MV64x60_CPU2DEV_3_SIZE, |
| 103 | .base_bits = 12, |
| 104 | .size_bits = 12, |
| 105 | .get_from_field = mv64x60_shift_left, |
| 106 | .map_to_field = mv64x60_shift_right, |
| 107 | .extra = 0 }, |
| 108 | /* CPU->Boot Window */ |
| 109 | [MV64x60_CPU2BOOT_WIN] = { |
| 110 | .base_reg = MV64x60_CPU2BOOT_0_BASE, |
| 111 | .size_reg = MV64x60_CPU2BOOT_0_SIZE, |
| 112 | .base_bits = 12, |
| 113 | .size_bits = 12, |
| 114 | .get_from_field = mv64x60_shift_left, |
| 115 | .map_to_field = mv64x60_shift_right, |
| 116 | .extra = 0 }, |
| 117 | /* CPU->PCI 0 Windows */ |
| 118 | [MV64x60_CPU2PCI0_IO_WIN] = { |
| 119 | .base_reg = MV64x60_CPU2PCI0_IO_BASE, |
| 120 | .size_reg = MV64x60_CPU2PCI0_IO_SIZE, |
| 121 | .base_bits = 12, |
| 122 | .size_bits = 12, |
| 123 | .get_from_field = mv64x60_shift_left, |
| 124 | .map_to_field = mv64x60_shift_right, |
| 125 | .extra = 0 }, |
| 126 | [MV64x60_CPU2PCI0_MEM_0_WIN] = { |
| 127 | .base_reg = MV64x60_CPU2PCI0_MEM_0_BASE, |
| 128 | .size_reg = MV64x60_CPU2PCI0_MEM_0_SIZE, |
| 129 | .base_bits = 12, |
| 130 | .size_bits = 12, |
| 131 | .get_from_field = mv64x60_shift_left, |
| 132 | .map_to_field = mv64x60_shift_right, |
| 133 | .extra = 0 }, |
| 134 | [MV64x60_CPU2PCI0_MEM_1_WIN] = { |
| 135 | .base_reg = MV64x60_CPU2PCI0_MEM_1_BASE, |
| 136 | .size_reg = MV64x60_CPU2PCI0_MEM_1_SIZE, |
| 137 | .base_bits = 12, |
| 138 | .size_bits = 12, |
| 139 | .get_from_field = mv64x60_shift_left, |
| 140 | .map_to_field = mv64x60_shift_right, |
| 141 | .extra = 0 }, |
| 142 | [MV64x60_CPU2PCI0_MEM_2_WIN] = { |
| 143 | .base_reg = MV64x60_CPU2PCI0_MEM_2_BASE, |
| 144 | .size_reg = MV64x60_CPU2PCI0_MEM_2_SIZE, |
| 145 | .base_bits = 12, |
| 146 | .size_bits = 12, |
| 147 | .get_from_field = mv64x60_shift_left, |
| 148 | .map_to_field = mv64x60_shift_right, |
| 149 | .extra = 0 }, |
| 150 | [MV64x60_CPU2PCI0_MEM_3_WIN] = { |
| 151 | .base_reg = MV64x60_CPU2PCI0_MEM_3_BASE, |
| 152 | .size_reg = MV64x60_CPU2PCI0_MEM_3_SIZE, |
| 153 | .base_bits = 12, |
| 154 | .size_bits = 12, |
| 155 | .get_from_field = mv64x60_shift_left, |
| 156 | .map_to_field = mv64x60_shift_right, |
| 157 | .extra = 0 }, |
| 158 | /* CPU->PCI 1 Windows */ |
| 159 | [MV64x60_CPU2PCI1_IO_WIN] = { |
| 160 | .base_reg = MV64x60_CPU2PCI1_IO_BASE, |
| 161 | .size_reg = MV64x60_CPU2PCI1_IO_SIZE, |
| 162 | .base_bits = 12, |
| 163 | .size_bits = 12, |
| 164 | .get_from_field = mv64x60_shift_left, |
| 165 | .map_to_field = mv64x60_shift_right, |
| 166 | .extra = 0 }, |
| 167 | [MV64x60_CPU2PCI1_MEM_0_WIN] = { |
| 168 | .base_reg = MV64x60_CPU2PCI1_MEM_0_BASE, |
| 169 | .size_reg = MV64x60_CPU2PCI1_MEM_0_SIZE, |
| 170 | .base_bits = 12, |
| 171 | .size_bits = 12, |
| 172 | .get_from_field = mv64x60_shift_left, |
| 173 | .map_to_field = mv64x60_shift_right, |
| 174 | .extra = 0 }, |
| 175 | [MV64x60_CPU2PCI1_MEM_1_WIN] = { |
| 176 | .base_reg = MV64x60_CPU2PCI1_MEM_1_BASE, |
| 177 | .size_reg = MV64x60_CPU2PCI1_MEM_1_SIZE, |
| 178 | .base_bits = 12, |
| 179 | .size_bits = 12, |
| 180 | .get_from_field = mv64x60_shift_left, |
| 181 | .map_to_field = mv64x60_shift_right, |
| 182 | .extra = 0 }, |
| 183 | [MV64x60_CPU2PCI1_MEM_2_WIN] = { |
| 184 | .base_reg = MV64x60_CPU2PCI1_MEM_2_BASE, |
| 185 | .size_reg = MV64x60_CPU2PCI1_MEM_2_SIZE, |
| 186 | .base_bits = 12, |
| 187 | .size_bits = 12, |
| 188 | .get_from_field = mv64x60_shift_left, |
| 189 | .map_to_field = mv64x60_shift_right, |
| 190 | .extra = 0 }, |
| 191 | [MV64x60_CPU2PCI1_MEM_3_WIN] = { |
| 192 | .base_reg = MV64x60_CPU2PCI1_MEM_3_BASE, |
| 193 | .size_reg = MV64x60_CPU2PCI1_MEM_3_SIZE, |
| 194 | .base_bits = 12, |
| 195 | .size_bits = 12, |
| 196 | .get_from_field = mv64x60_shift_left, |
| 197 | .map_to_field = mv64x60_shift_right, |
| 198 | .extra = 0 }, |
| 199 | /* CPU->SRAM Window (64260 has no integrated SRAM) */ |
| 200 | /* CPU->PCI 0 Remap I/O Window */ |
| 201 | [MV64x60_CPU2PCI0_IO_REMAP_WIN] = { |
| 202 | .base_reg = MV64x60_CPU2PCI0_IO_REMAP, |
| 203 | .size_reg = 0, |
| 204 | .base_bits = 12, |
| 205 | .size_bits = 0, |
| 206 | .get_from_field = mv64x60_shift_left, |
| 207 | .map_to_field = mv64x60_shift_right, |
| 208 | .extra = 0 }, |
| 209 | /* CPU->PCI 1 Remap I/O Window */ |
| 210 | [MV64x60_CPU2PCI1_IO_REMAP_WIN] = { |
| 211 | .base_reg = MV64x60_CPU2PCI1_IO_REMAP, |
| 212 | .size_reg = 0, |
| 213 | .base_bits = 12, |
| 214 | .size_bits = 0, |
| 215 | .get_from_field = mv64x60_shift_left, |
| 216 | .map_to_field = mv64x60_shift_right, |
| 217 | .extra = 0 }, |
| 218 | /* CPU Memory Protection Windows */ |
| 219 | [MV64x60_CPU_PROT_0_WIN] = { |
| 220 | .base_reg = MV64x60_CPU_PROT_BASE_0, |
| 221 | .size_reg = MV64x60_CPU_PROT_SIZE_0, |
| 222 | .base_bits = 12, |
| 223 | .size_bits = 12, |
| 224 | .get_from_field = mv64x60_shift_left, |
| 225 | .map_to_field = mv64x60_shift_right, |
| 226 | .extra = 0 }, |
| 227 | [MV64x60_CPU_PROT_1_WIN] = { |
| 228 | .base_reg = MV64x60_CPU_PROT_BASE_1, |
| 229 | .size_reg = MV64x60_CPU_PROT_SIZE_1, |
| 230 | .base_bits = 12, |
| 231 | .size_bits = 12, |
| 232 | .get_from_field = mv64x60_shift_left, |
| 233 | .map_to_field = mv64x60_shift_right, |
| 234 | .extra = 0 }, |
| 235 | [MV64x60_CPU_PROT_2_WIN] = { |
| 236 | .base_reg = MV64x60_CPU_PROT_BASE_2, |
| 237 | .size_reg = MV64x60_CPU_PROT_SIZE_2, |
| 238 | .base_bits = 12, |
| 239 | .size_bits = 12, |
| 240 | .get_from_field = mv64x60_shift_left, |
| 241 | .map_to_field = mv64x60_shift_right, |
| 242 | .extra = 0 }, |
| 243 | [MV64x60_CPU_PROT_3_WIN] = { |
| 244 | .base_reg = MV64x60_CPU_PROT_BASE_3, |
| 245 | .size_reg = MV64x60_CPU_PROT_SIZE_3, |
| 246 | .base_bits = 12, |
| 247 | .size_bits = 12, |
| 248 | .get_from_field = mv64x60_shift_left, |
| 249 | .map_to_field = mv64x60_shift_right, |
| 250 | .extra = 0 }, |
| 251 | /* CPU Snoop Windows */ |
| 252 | [MV64x60_CPU_SNOOP_0_WIN] = { |
| 253 | .base_reg = GT64260_CPU_SNOOP_BASE_0, |
| 254 | .size_reg = GT64260_CPU_SNOOP_SIZE_0, |
| 255 | .base_bits = 12, |
| 256 | .size_bits = 12, |
| 257 | .get_from_field = mv64x60_shift_left, |
| 258 | .map_to_field = mv64x60_shift_right, |
| 259 | .extra = 0 }, |
| 260 | [MV64x60_CPU_SNOOP_1_WIN] = { |
| 261 | .base_reg = GT64260_CPU_SNOOP_BASE_1, |
| 262 | .size_reg = GT64260_CPU_SNOOP_SIZE_1, |
| 263 | .base_bits = 12, |
| 264 | .size_bits = 12, |
| 265 | .get_from_field = mv64x60_shift_left, |
| 266 | .map_to_field = mv64x60_shift_right, |
| 267 | .extra = 0 }, |
| 268 | [MV64x60_CPU_SNOOP_2_WIN] = { |
| 269 | .base_reg = GT64260_CPU_SNOOP_BASE_2, |
| 270 | .size_reg = GT64260_CPU_SNOOP_SIZE_2, |
| 271 | .base_bits = 12, |
| 272 | .size_bits = 12, |
| 273 | .get_from_field = mv64x60_shift_left, |
| 274 | .map_to_field = mv64x60_shift_right, |
| 275 | .extra = 0 }, |
| 276 | [MV64x60_CPU_SNOOP_3_WIN] = { |
| 277 | .base_reg = GT64260_CPU_SNOOP_BASE_3, |
| 278 | .size_reg = GT64260_CPU_SNOOP_SIZE_3, |
| 279 | .base_bits = 12, |
| 280 | .size_bits = 12, |
| 281 | .get_from_field = mv64x60_shift_left, |
| 282 | .map_to_field = mv64x60_shift_right, |
| 283 | .extra = 0 }, |
| 284 | /* PCI 0->System Memory Remap Windows */ |
| 285 | [MV64x60_PCI02MEM_REMAP_0_WIN] = { |
| 286 | .base_reg = MV64x60_PCI0_SLAVE_MEM_0_REMAP, |
| 287 | .size_reg = 0, |
| 288 | .base_bits = 20, |
| 289 | .size_bits = 0, |
| 290 | .get_from_field = mv64x60_mask, |
| 291 | .map_to_field = mv64x60_mask, |
| 292 | .extra = 0 }, |
| 293 | [MV64x60_PCI02MEM_REMAP_1_WIN] = { |
| 294 | .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, |
| 295 | .size_reg = 0, |
| 296 | .base_bits = 20, |
| 297 | .size_bits = 0, |
| 298 | .get_from_field = mv64x60_mask, |
| 299 | .map_to_field = mv64x60_mask, |
| 300 | .extra = 0 }, |
| 301 | [MV64x60_PCI02MEM_REMAP_2_WIN] = { |
| 302 | .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, |
| 303 | .size_reg = 0, |
| 304 | .base_bits = 20, |
| 305 | .size_bits = 0, |
| 306 | .get_from_field = mv64x60_mask, |
| 307 | .map_to_field = mv64x60_mask, |
| 308 | .extra = 0 }, |
| 309 | [MV64x60_PCI02MEM_REMAP_3_WIN] = { |
| 310 | .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, |
| 311 | .size_reg = 0, |
| 312 | .base_bits = 20, |
| 313 | .size_bits = 0, |
| 314 | .get_from_field = mv64x60_mask, |
| 315 | .map_to_field = mv64x60_mask, |
| 316 | .extra = 0 }, |
| 317 | /* PCI 1->System Memory Remap Windows */ |
| 318 | [MV64x60_PCI12MEM_REMAP_0_WIN] = { |
| 319 | .base_reg = MV64x60_PCI1_SLAVE_MEM_0_REMAP, |
| 320 | .size_reg = 0, |
| 321 | .base_bits = 20, |
| 322 | .size_bits = 0, |
| 323 | .get_from_field = mv64x60_mask, |
| 324 | .map_to_field = mv64x60_mask, |
| 325 | .extra = 0 }, |
| 326 | [MV64x60_PCI12MEM_REMAP_1_WIN] = { |
| 327 | .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, |
| 328 | .size_reg = 0, |
| 329 | .base_bits = 20, |
| 330 | .size_bits = 0, |
| 331 | .get_from_field = mv64x60_mask, |
| 332 | .map_to_field = mv64x60_mask, |
| 333 | .extra = 0 }, |
| 334 | [MV64x60_PCI12MEM_REMAP_2_WIN] = { |
| 335 | .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, |
| 336 | .size_reg = 0, |
| 337 | .base_bits = 20, |
| 338 | .size_bits = 0, |
| 339 | .get_from_field = mv64x60_mask, |
| 340 | .map_to_field = mv64x60_mask, |
| 341 | .extra = 0 }, |
| 342 | [MV64x60_PCI12MEM_REMAP_3_WIN] = { |
| 343 | .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, |
| 344 | .size_reg = 0, |
| 345 | .base_bits = 20, |
| 346 | .size_bits = 0, |
| 347 | .get_from_field = mv64x60_mask, |
| 348 | .map_to_field = mv64x60_mask, |
| 349 | .extra = 0 }, |
| 350 | /* ENET->SRAM Window (64260 doesn't have separate windows) */ |
| 351 | /* MPSC->SRAM Window (64260 doesn't have separate windows) */ |
| 352 | /* IDMA->SRAM Window (64260 doesn't have separate windows) */ |
| 353 | }; |
| 354 | |
| 355 | struct mv64x60_64bit_window |
| 356 | gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT] __initdata = { |
| 357 | /* CPU->PCI 0 MEM Remap Windows */ |
| 358 | [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = { |
| 359 | .base_hi_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_HI, |
| 360 | .base_lo_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_LO, |
| 361 | .size_reg = 0, |
| 362 | .base_lo_bits = 12, |
| 363 | .size_bits = 0, |
| 364 | .get_from_field = mv64x60_shift_left, |
| 365 | .map_to_field = mv64x60_shift_right, |
| 366 | .extra = 0 }, |
| 367 | [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = { |
| 368 | .base_hi_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_HI, |
| 369 | .base_lo_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_LO, |
| 370 | .size_reg = 0, |
| 371 | .base_lo_bits = 12, |
| 372 | .size_bits = 0, |
| 373 | .get_from_field = mv64x60_shift_left, |
| 374 | .map_to_field = mv64x60_shift_right, |
| 375 | .extra = 0 }, |
| 376 | [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = { |
| 377 | .base_hi_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_HI, |
| 378 | .base_lo_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_LO, |
| 379 | .size_reg = 0, |
| 380 | .base_lo_bits = 12, |
| 381 | .size_bits = 0, |
| 382 | .get_from_field = mv64x60_shift_left, |
| 383 | .map_to_field = mv64x60_shift_right, |
| 384 | .extra = 0 }, |
| 385 | [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = { |
| 386 | .base_hi_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_HI, |
| 387 | .base_lo_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_LO, |
| 388 | .size_reg = 0, |
| 389 | .base_lo_bits = 12, |
| 390 | .size_bits = 0, |
| 391 | .get_from_field = mv64x60_shift_left, |
| 392 | .map_to_field = mv64x60_shift_right, |
| 393 | .extra = 0 }, |
| 394 | /* CPU->PCI 1 MEM Remap Windows */ |
| 395 | [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = { |
| 396 | .base_hi_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_HI, |
| 397 | .base_lo_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_LO, |
| 398 | .size_reg = 0, |
| 399 | .base_lo_bits = 12, |
| 400 | .size_bits = 0, |
| 401 | .get_from_field = mv64x60_shift_left, |
| 402 | .map_to_field = mv64x60_shift_right, |
| 403 | .extra = 0 }, |
| 404 | [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = { |
| 405 | .base_hi_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_HI, |
| 406 | .base_lo_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_LO, |
| 407 | .size_reg = 0, |
| 408 | .base_lo_bits = 12, |
| 409 | .size_bits = 0, |
| 410 | .get_from_field = mv64x60_shift_left, |
| 411 | .map_to_field = mv64x60_shift_right, |
| 412 | .extra = 0 }, |
| 413 | [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = { |
| 414 | .base_hi_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_HI, |
| 415 | .base_lo_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_LO, |
| 416 | .size_reg = 0, |
| 417 | .base_lo_bits = 12, |
| 418 | .size_bits = 0, |
| 419 | .get_from_field = mv64x60_shift_left, |
| 420 | .map_to_field = mv64x60_shift_right, |
| 421 | .extra = 0 }, |
| 422 | [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = { |
| 423 | .base_hi_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_HI, |
| 424 | .base_lo_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_LO, |
| 425 | .size_reg = 0, |
| 426 | .base_lo_bits = 12, |
| 427 | .size_bits = 0, |
| 428 | .get_from_field = mv64x60_shift_left, |
| 429 | .map_to_field = mv64x60_shift_right, |
| 430 | .extra = 0 }, |
| 431 | /* PCI 0->MEM Access Control Windows */ |
| 432 | [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = { |
| 433 | .base_hi_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_HI, |
| 434 | .base_lo_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_LO, |
| 435 | .size_reg = MV64x60_PCI0_ACC_CNTL_0_SIZE, |
| 436 | .base_lo_bits = 12, |
| 437 | .size_bits = 12, |
| 438 | .get_from_field = mv64x60_shift_left, |
| 439 | .map_to_field = mv64x60_shift_right, |
| 440 | .extra = 0 }, |
| 441 | [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = { |
| 442 | .base_hi_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_HI, |
| 443 | .base_lo_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_LO, |
| 444 | .size_reg = MV64x60_PCI0_ACC_CNTL_1_SIZE, |
| 445 | .base_lo_bits = 12, |
| 446 | .size_bits = 12, |
| 447 | .get_from_field = mv64x60_shift_left, |
| 448 | .map_to_field = mv64x60_shift_right, |
| 449 | .extra = 0 }, |
| 450 | [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = { |
| 451 | .base_hi_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_HI, |
| 452 | .base_lo_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_LO, |
| 453 | .size_reg = MV64x60_PCI0_ACC_CNTL_2_SIZE, |
| 454 | .base_lo_bits = 12, |
| 455 | .size_bits = 12, |
| 456 | .get_from_field = mv64x60_shift_left, |
| 457 | .map_to_field = mv64x60_shift_right, |
| 458 | .extra = 0 }, |
| 459 | [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = { |
| 460 | .base_hi_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_HI, |
| 461 | .base_lo_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_LO, |
| 462 | .size_reg = MV64x60_PCI0_ACC_CNTL_3_SIZE, |
| 463 | .base_lo_bits = 12, |
| 464 | .size_bits = 12, |
| 465 | .get_from_field = mv64x60_shift_left, |
| 466 | .map_to_field = mv64x60_shift_right, |
| 467 | .extra = 0 }, |
| 468 | /* PCI 1->MEM Access Control Windows */ |
| 469 | [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = { |
| 470 | .base_hi_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_HI, |
| 471 | .base_lo_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_LO, |
| 472 | .size_reg = MV64x60_PCI1_ACC_CNTL_0_SIZE, |
| 473 | .base_lo_bits = 12, |
| 474 | .size_bits = 12, |
| 475 | .get_from_field = mv64x60_shift_left, |
| 476 | .map_to_field = mv64x60_shift_right, |
| 477 | .extra = 0 }, |
| 478 | [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = { |
| 479 | .base_hi_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_HI, |
| 480 | .base_lo_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_LO, |
| 481 | .size_reg = MV64x60_PCI1_ACC_CNTL_1_SIZE, |
| 482 | .base_lo_bits = 12, |
| 483 | .size_bits = 12, |
| 484 | .get_from_field = mv64x60_shift_left, |
| 485 | .map_to_field = mv64x60_shift_right, |
| 486 | .extra = 0 }, |
| 487 | [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = { |
| 488 | .base_hi_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_HI, |
| 489 | .base_lo_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_LO, |
| 490 | .size_reg = MV64x60_PCI1_ACC_CNTL_2_SIZE, |
| 491 | .base_lo_bits = 12, |
| 492 | .size_bits = 12, |
| 493 | .get_from_field = mv64x60_shift_left, |
| 494 | .map_to_field = mv64x60_shift_right, |
| 495 | .extra = 0 }, |
| 496 | [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = { |
| 497 | .base_hi_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_HI, |
| 498 | .base_lo_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_LO, |
| 499 | .size_reg = MV64x60_PCI1_ACC_CNTL_3_SIZE, |
| 500 | .base_lo_bits = 12, |
| 501 | .size_bits = 12, |
| 502 | .get_from_field = mv64x60_shift_left, |
| 503 | .map_to_field = mv64x60_shift_right, |
| 504 | .extra = 0 }, |
| 505 | /* PCI 0->MEM Snoop Windows */ |
| 506 | [MV64x60_PCI02MEM_SNOOP_0_WIN] = { |
| 507 | .base_hi_reg = GT64260_PCI0_SNOOP_0_BASE_HI, |
| 508 | .base_lo_reg = GT64260_PCI0_SNOOP_0_BASE_LO, |
| 509 | .size_reg = GT64260_PCI0_SNOOP_0_SIZE, |
| 510 | .base_lo_bits = 12, |
| 511 | .size_bits = 12, |
| 512 | .get_from_field = mv64x60_shift_left, |
| 513 | .map_to_field = mv64x60_shift_right, |
| 514 | .extra = 0 }, |
| 515 | [MV64x60_PCI02MEM_SNOOP_1_WIN] = { |
| 516 | .base_hi_reg = GT64260_PCI0_SNOOP_1_BASE_HI, |
| 517 | .base_lo_reg = GT64260_PCI0_SNOOP_1_BASE_LO, |
| 518 | .size_reg = GT64260_PCI0_SNOOP_1_SIZE, |
| 519 | .base_lo_bits = 12, |
| 520 | .size_bits = 12, |
| 521 | .get_from_field = mv64x60_shift_left, |
| 522 | .map_to_field = mv64x60_shift_right, |
| 523 | .extra = 0 }, |
| 524 | [MV64x60_PCI02MEM_SNOOP_2_WIN] = { |
| 525 | .base_hi_reg = GT64260_PCI0_SNOOP_2_BASE_HI, |
| 526 | .base_lo_reg = GT64260_PCI0_SNOOP_2_BASE_LO, |
| 527 | .size_reg = GT64260_PCI0_SNOOP_2_SIZE, |
| 528 | .base_lo_bits = 12, |
| 529 | .size_bits = 12, |
| 530 | .get_from_field = mv64x60_shift_left, |
| 531 | .map_to_field = mv64x60_shift_right, |
| 532 | .extra = 0 }, |
| 533 | [MV64x60_PCI02MEM_SNOOP_3_WIN] = { |
| 534 | .base_hi_reg = GT64260_PCI0_SNOOP_3_BASE_HI, |
| 535 | .base_lo_reg = GT64260_PCI0_SNOOP_3_BASE_LO, |
| 536 | .size_reg = GT64260_PCI0_SNOOP_3_SIZE, |
| 537 | .base_lo_bits = 12, |
| 538 | .size_bits = 12, |
| 539 | .get_from_field = mv64x60_shift_left, |
| 540 | .map_to_field = mv64x60_shift_right, |
| 541 | .extra = 0 }, |
| 542 | /* PCI 1->MEM Snoop Windows */ |
| 543 | [MV64x60_PCI12MEM_SNOOP_0_WIN] = { |
| 544 | .base_hi_reg = GT64260_PCI1_SNOOP_0_BASE_HI, |
| 545 | .base_lo_reg = GT64260_PCI1_SNOOP_0_BASE_LO, |
| 546 | .size_reg = GT64260_PCI1_SNOOP_0_SIZE, |
| 547 | .base_lo_bits = 12, |
| 548 | .size_bits = 12, |
| 549 | .get_from_field = mv64x60_shift_left, |
| 550 | .map_to_field = mv64x60_shift_right, |
| 551 | .extra = 0 }, |
| 552 | [MV64x60_PCI12MEM_SNOOP_1_WIN] = { |
| 553 | .base_hi_reg = GT64260_PCI1_SNOOP_1_BASE_HI, |
| 554 | .base_lo_reg = GT64260_PCI1_SNOOP_1_BASE_LO, |
| 555 | .size_reg = GT64260_PCI1_SNOOP_1_SIZE, |
| 556 | .base_lo_bits = 12, |
| 557 | .size_bits = 12, |
| 558 | .get_from_field = mv64x60_shift_left, |
| 559 | .map_to_field = mv64x60_shift_right, |
| 560 | .extra = 0 }, |
| 561 | [MV64x60_PCI12MEM_SNOOP_2_WIN] = { |
| 562 | .base_hi_reg = GT64260_PCI1_SNOOP_2_BASE_HI, |
| 563 | .base_lo_reg = GT64260_PCI1_SNOOP_2_BASE_LO, |
| 564 | .size_reg = GT64260_PCI1_SNOOP_2_SIZE, |
| 565 | .base_lo_bits = 12, |
| 566 | .size_bits = 12, |
| 567 | .get_from_field = mv64x60_shift_left, |
| 568 | .map_to_field = mv64x60_shift_right, |
| 569 | .extra = 0 }, |
| 570 | [MV64x60_PCI12MEM_SNOOP_3_WIN] = { |
| 571 | .base_hi_reg = GT64260_PCI1_SNOOP_3_BASE_HI, |
| 572 | .base_lo_reg = GT64260_PCI1_SNOOP_3_BASE_LO, |
| 573 | .size_reg = GT64260_PCI1_SNOOP_3_SIZE, |
| 574 | .base_lo_bits = 12, |
| 575 | .size_bits = 12, |
| 576 | .get_from_field = mv64x60_shift_left, |
| 577 | .map_to_field = mv64x60_shift_right, |
| 578 | .extra = 0 }, |
| 579 | }; |
| 580 | |
| 581 | struct mv64x60_32bit_window |
| 582 | mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT] __initdata = { |
| 583 | /* CPU->MEM Windows */ |
| 584 | [MV64x60_CPU2MEM_0_WIN] = { |
| 585 | .base_reg = MV64x60_CPU2MEM_0_BASE, |
| 586 | .size_reg = MV64x60_CPU2MEM_0_SIZE, |
| 587 | .base_bits = 16, |
| 588 | .size_bits = 16, |
| 589 | .get_from_field = mv64x60_shift_left, |
| 590 | .map_to_field = mv64x60_shift_right, |
| 591 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 0 }, |
| 592 | [MV64x60_CPU2MEM_1_WIN] = { |
| 593 | .base_reg = MV64x60_CPU2MEM_1_BASE, |
| 594 | .size_reg = MV64x60_CPU2MEM_1_SIZE, |
| 595 | .base_bits = 16, |
| 596 | .size_bits = 16, |
| 597 | .get_from_field = mv64x60_shift_left, |
| 598 | .map_to_field = mv64x60_shift_right, |
| 599 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 1 }, |
| 600 | [MV64x60_CPU2MEM_2_WIN] = { |
| 601 | .base_reg = MV64x60_CPU2MEM_2_BASE, |
| 602 | .size_reg = MV64x60_CPU2MEM_2_SIZE, |
| 603 | .base_bits = 16, |
| 604 | .size_bits = 16, |
| 605 | .get_from_field = mv64x60_shift_left, |
| 606 | .map_to_field = mv64x60_shift_right, |
| 607 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 2 }, |
| 608 | [MV64x60_CPU2MEM_3_WIN] = { |
| 609 | .base_reg = MV64x60_CPU2MEM_3_BASE, |
| 610 | .size_reg = MV64x60_CPU2MEM_3_SIZE, |
| 611 | .base_bits = 16, |
| 612 | .size_bits = 16, |
| 613 | .get_from_field = mv64x60_shift_left, |
| 614 | .map_to_field = mv64x60_shift_right, |
| 615 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 3 }, |
| 616 | /* CPU->Device Windows */ |
| 617 | [MV64x60_CPU2DEV_0_WIN] = { |
| 618 | .base_reg = MV64x60_CPU2DEV_0_BASE, |
| 619 | .size_reg = MV64x60_CPU2DEV_0_SIZE, |
| 620 | .base_bits = 16, |
| 621 | .size_bits = 16, |
| 622 | .get_from_field = mv64x60_shift_left, |
| 623 | .map_to_field = mv64x60_shift_right, |
| 624 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 4 }, |
| 625 | [MV64x60_CPU2DEV_1_WIN] = { |
| 626 | .base_reg = MV64x60_CPU2DEV_1_BASE, |
| 627 | .size_reg = MV64x60_CPU2DEV_1_SIZE, |
| 628 | .base_bits = 16, |
| 629 | .size_bits = 16, |
| 630 | .get_from_field = mv64x60_shift_left, |
| 631 | .map_to_field = mv64x60_shift_right, |
| 632 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 5 }, |
| 633 | [MV64x60_CPU2DEV_2_WIN] = { |
| 634 | .base_reg = MV64x60_CPU2DEV_2_BASE, |
| 635 | .size_reg = MV64x60_CPU2DEV_2_SIZE, |
| 636 | .base_bits = 16, |
| 637 | .size_bits = 16, |
| 638 | .get_from_field = mv64x60_shift_left, |
| 639 | .map_to_field = mv64x60_shift_right, |
| 640 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 6 }, |
| 641 | [MV64x60_CPU2DEV_3_WIN] = { |
| 642 | .base_reg = MV64x60_CPU2DEV_3_BASE, |
| 643 | .size_reg = MV64x60_CPU2DEV_3_SIZE, |
| 644 | .base_bits = 16, |
| 645 | .size_bits = 16, |
| 646 | .get_from_field = mv64x60_shift_left, |
| 647 | .map_to_field = mv64x60_shift_right, |
| 648 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 7 }, |
| 649 | /* CPU->Boot Window */ |
| 650 | [MV64x60_CPU2BOOT_WIN] = { |
| 651 | .base_reg = MV64x60_CPU2BOOT_0_BASE, |
| 652 | .size_reg = MV64x60_CPU2BOOT_0_SIZE, |
| 653 | .base_bits = 16, |
| 654 | .size_bits = 16, |
| 655 | .get_from_field = mv64x60_shift_left, |
| 656 | .map_to_field = mv64x60_shift_right, |
| 657 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 8 }, |
| 658 | /* CPU->PCI 0 Windows */ |
| 659 | [MV64x60_CPU2PCI0_IO_WIN] = { |
| 660 | .base_reg = MV64x60_CPU2PCI0_IO_BASE, |
| 661 | .size_reg = MV64x60_CPU2PCI0_IO_SIZE, |
| 662 | .base_bits = 16, |
| 663 | .size_bits = 16, |
| 664 | .get_from_field = mv64x60_shift_left, |
| 665 | .map_to_field = mv64x60_shift_right, |
| 666 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 9 }, |
| 667 | [MV64x60_CPU2PCI0_MEM_0_WIN] = { |
| 668 | .base_reg = MV64x60_CPU2PCI0_MEM_0_BASE, |
| 669 | .size_reg = MV64x60_CPU2PCI0_MEM_0_SIZE, |
| 670 | .base_bits = 16, |
| 671 | .size_bits = 16, |
| 672 | .get_from_field = mv64x60_shift_left, |
| 673 | .map_to_field = mv64x60_shift_right, |
| 674 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 10 }, |
| 675 | [MV64x60_CPU2PCI0_MEM_1_WIN] = { |
| 676 | .base_reg = MV64x60_CPU2PCI0_MEM_1_BASE, |
| 677 | .size_reg = MV64x60_CPU2PCI0_MEM_1_SIZE, |
| 678 | .base_bits = 16, |
| 679 | .size_bits = 16, |
| 680 | .get_from_field = mv64x60_shift_left, |
| 681 | .map_to_field = mv64x60_shift_right, |
| 682 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 11 }, |
| 683 | [MV64x60_CPU2PCI0_MEM_2_WIN] = { |
| 684 | .base_reg = MV64x60_CPU2PCI0_MEM_2_BASE, |
| 685 | .size_reg = MV64x60_CPU2PCI0_MEM_2_SIZE, |
| 686 | .base_bits = 16, |
| 687 | .size_bits = 16, |
| 688 | .get_from_field = mv64x60_shift_left, |
| 689 | .map_to_field = mv64x60_shift_right, |
| 690 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 12 }, |
| 691 | [MV64x60_CPU2PCI0_MEM_3_WIN] = { |
| 692 | .base_reg = MV64x60_CPU2PCI0_MEM_3_BASE, |
| 693 | .size_reg = MV64x60_CPU2PCI0_MEM_3_SIZE, |
| 694 | .base_bits = 16, |
| 695 | .size_bits = 16, |
| 696 | .get_from_field = mv64x60_shift_left, |
| 697 | .map_to_field = mv64x60_shift_right, |
| 698 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 13 }, |
| 699 | /* CPU->PCI 1 Windows */ |
| 700 | [MV64x60_CPU2PCI1_IO_WIN] = { |
| 701 | .base_reg = MV64x60_CPU2PCI1_IO_BASE, |
| 702 | .size_reg = MV64x60_CPU2PCI1_IO_SIZE, |
| 703 | .base_bits = 16, |
| 704 | .size_bits = 16, |
| 705 | .get_from_field = mv64x60_shift_left, |
| 706 | .map_to_field = mv64x60_shift_right, |
| 707 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 14 }, |
| 708 | [MV64x60_CPU2PCI1_MEM_0_WIN] = { |
| 709 | .base_reg = MV64x60_CPU2PCI1_MEM_0_BASE, |
| 710 | .size_reg = MV64x60_CPU2PCI1_MEM_0_SIZE, |
| 711 | .base_bits = 16, |
| 712 | .size_bits = 16, |
| 713 | .get_from_field = mv64x60_shift_left, |
| 714 | .map_to_field = mv64x60_shift_right, |
| 715 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 15 }, |
| 716 | [MV64x60_CPU2PCI1_MEM_1_WIN] = { |
| 717 | .base_reg = MV64x60_CPU2PCI1_MEM_1_BASE, |
| 718 | .size_reg = MV64x60_CPU2PCI1_MEM_1_SIZE, |
| 719 | .base_bits = 16, |
| 720 | .size_bits = 16, |
| 721 | .get_from_field = mv64x60_shift_left, |
| 722 | .map_to_field = mv64x60_shift_right, |
| 723 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 16 }, |
| 724 | [MV64x60_CPU2PCI1_MEM_2_WIN] = { |
| 725 | .base_reg = MV64x60_CPU2PCI1_MEM_2_BASE, |
| 726 | .size_reg = MV64x60_CPU2PCI1_MEM_2_SIZE, |
| 727 | .base_bits = 16, |
| 728 | .size_bits = 16, |
| 729 | .get_from_field = mv64x60_shift_left, |
| 730 | .map_to_field = mv64x60_shift_right, |
| 731 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 17 }, |
| 732 | [MV64x60_CPU2PCI1_MEM_3_WIN] = { |
| 733 | .base_reg = MV64x60_CPU2PCI1_MEM_3_BASE, |
| 734 | .size_reg = MV64x60_CPU2PCI1_MEM_3_SIZE, |
| 735 | .base_bits = 16, |
| 736 | .size_bits = 16, |
| 737 | .get_from_field = mv64x60_shift_left, |
| 738 | .map_to_field = mv64x60_shift_right, |
| 739 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 18 }, |
| 740 | /* CPU->SRAM Window */ |
| 741 | [MV64x60_CPU2SRAM_WIN] = { |
| 742 | .base_reg = MV64360_CPU2SRAM_BASE, |
| 743 | .size_reg = 0, |
| 744 | .base_bits = 16, |
| 745 | .size_bits = 0, |
| 746 | .get_from_field = mv64x60_shift_left, |
| 747 | .map_to_field = mv64x60_shift_right, |
| 748 | .extra = MV64x60_EXTRA_CPUWIN_ENAB | 19 }, |
| 749 | /* CPU->PCI 0 Remap I/O Window */ |
| 750 | [MV64x60_CPU2PCI0_IO_REMAP_WIN] = { |
| 751 | .base_reg = MV64x60_CPU2PCI0_IO_REMAP, |
| 752 | .size_reg = 0, |
| 753 | .base_bits = 16, |
| 754 | .size_bits = 0, |
| 755 | .get_from_field = mv64x60_shift_left, |
| 756 | .map_to_field = mv64x60_shift_right, |
| 757 | .extra = 0 }, |
| 758 | /* CPU->PCI 1 Remap I/O Window */ |
| 759 | [MV64x60_CPU2PCI1_IO_REMAP_WIN] = { |
| 760 | .base_reg = MV64x60_CPU2PCI1_IO_REMAP, |
| 761 | .size_reg = 0, |
| 762 | .base_bits = 16, |
| 763 | .size_bits = 0, |
| 764 | .get_from_field = mv64x60_shift_left, |
| 765 | .map_to_field = mv64x60_shift_right, |
| 766 | .extra = 0 }, |
| 767 | /* CPU Memory Protection Windows */ |
| 768 | [MV64x60_CPU_PROT_0_WIN] = { |
| 769 | .base_reg = MV64x60_CPU_PROT_BASE_0, |
| 770 | .size_reg = MV64x60_CPU_PROT_SIZE_0, |
| 771 | .base_bits = 16, |
| 772 | .size_bits = 16, |
| 773 | .get_from_field = mv64x60_shift_left, |
| 774 | .map_to_field = mv64x60_shift_right, |
| 775 | .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 }, |
| 776 | [MV64x60_CPU_PROT_1_WIN] = { |
| 777 | .base_reg = MV64x60_CPU_PROT_BASE_1, |
| 778 | .size_reg = MV64x60_CPU_PROT_SIZE_1, |
| 779 | .base_bits = 16, |
| 780 | .size_bits = 16, |
| 781 | .get_from_field = mv64x60_shift_left, |
| 782 | .map_to_field = mv64x60_shift_right, |
| 783 | .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 }, |
| 784 | [MV64x60_CPU_PROT_2_WIN] = { |
| 785 | .base_reg = MV64x60_CPU_PROT_BASE_2, |
| 786 | .size_reg = MV64x60_CPU_PROT_SIZE_2, |
| 787 | .base_bits = 16, |
| 788 | .size_bits = 16, |
| 789 | .get_from_field = mv64x60_shift_left, |
| 790 | .map_to_field = mv64x60_shift_right, |
| 791 | .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 }, |
| 792 | [MV64x60_CPU_PROT_3_WIN] = { |
| 793 | .base_reg = MV64x60_CPU_PROT_BASE_3, |
| 794 | .size_reg = MV64x60_CPU_PROT_SIZE_3, |
| 795 | .base_bits = 16, |
| 796 | .size_bits = 16, |
| 797 | .get_from_field = mv64x60_shift_left, |
| 798 | .map_to_field = mv64x60_shift_right, |
| 799 | .extra = MV64x60_EXTRA_CPUPROT_ENAB | 31 }, |
| 800 | /* CPU Snoop Windows -- don't exist on 64360 */ |
| 801 | /* PCI 0->System Memory Remap Windows */ |
| 802 | [MV64x60_PCI02MEM_REMAP_0_WIN] = { |
| 803 | .base_reg = MV64x60_PCI0_SLAVE_MEM_0_REMAP, |
| 804 | .size_reg = 0, |
| 805 | .base_bits = 20, |
| 806 | .size_bits = 0, |
| 807 | .get_from_field = mv64x60_mask, |
| 808 | .map_to_field = mv64x60_mask, |
| 809 | .extra = 0 }, |
| 810 | [MV64x60_PCI02MEM_REMAP_1_WIN] = { |
| 811 | .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, |
| 812 | .size_reg = 0, |
| 813 | .base_bits = 20, |
| 814 | .size_bits = 0, |
| 815 | .get_from_field = mv64x60_mask, |
| 816 | .map_to_field = mv64x60_mask, |
| 817 | .extra = 0 }, |
| 818 | [MV64x60_PCI02MEM_REMAP_2_WIN] = { |
| 819 | .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, |
| 820 | .size_reg = 0, |
| 821 | .base_bits = 20, |
| 822 | .size_bits = 0, |
| 823 | .get_from_field = mv64x60_mask, |
| 824 | .map_to_field = mv64x60_mask, |
| 825 | .extra = 0 }, |
| 826 | [MV64x60_PCI02MEM_REMAP_3_WIN] = { |
| 827 | .base_reg = MV64x60_PCI0_SLAVE_MEM_1_REMAP, |
| 828 | .size_reg = 0, |
| 829 | .base_bits = 20, |
| 830 | .size_bits = 0, |
| 831 | .get_from_field = mv64x60_mask, |
| 832 | .map_to_field = mv64x60_mask, |
| 833 | .extra = 0 }, |
| 834 | /* PCI 1->System Memory Remap Windows */ |
| 835 | [MV64x60_PCI12MEM_REMAP_0_WIN] = { |
| 836 | .base_reg = MV64x60_PCI1_SLAVE_MEM_0_REMAP, |
| 837 | .size_reg = 0, |
| 838 | .base_bits = 20, |
| 839 | .size_bits = 0, |
| 840 | .get_from_field = mv64x60_mask, |
| 841 | .map_to_field = mv64x60_mask, |
| 842 | .extra = 0 }, |
| 843 | [MV64x60_PCI12MEM_REMAP_1_WIN] = { |
| 844 | .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, |
| 845 | .size_reg = 0, |
| 846 | .base_bits = 20, |
| 847 | .size_bits = 0, |
| 848 | .get_from_field = mv64x60_mask, |
| 849 | .map_to_field = mv64x60_mask, |
| 850 | .extra = 0 }, |
| 851 | [MV64x60_PCI12MEM_REMAP_2_WIN] = { |
| 852 | .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, |
| 853 | .size_reg = 0, |
| 854 | .base_bits = 20, |
| 855 | .size_bits = 0, |
| 856 | .get_from_field = mv64x60_mask, |
| 857 | .map_to_field = mv64x60_mask, |
| 858 | .extra = 0 }, |
| 859 | [MV64x60_PCI12MEM_REMAP_3_WIN] = { |
| 860 | .base_reg = MV64x60_PCI1_SLAVE_MEM_1_REMAP, |
| 861 | .size_reg = 0, |
| 862 | .base_bits = 20, |
| 863 | .size_bits = 0, |
| 864 | .get_from_field = mv64x60_mask, |
| 865 | .map_to_field = mv64x60_mask, |
| 866 | .extra = 0 }, |
| 867 | /* ENET->System Memory Windows */ |
| 868 | [MV64x60_ENET2MEM_0_WIN] = { |
| 869 | .base_reg = MV64360_ENET2MEM_0_BASE, |
| 870 | .size_reg = MV64360_ENET2MEM_0_SIZE, |
| 871 | .base_bits = 16, |
| 872 | .size_bits = 16, |
| 873 | .get_from_field = mv64x60_mask, |
| 874 | .map_to_field = mv64x60_mask, |
| 875 | .extra = MV64x60_EXTRA_ENET_ENAB | 0 }, |
| 876 | [MV64x60_ENET2MEM_1_WIN] = { |
| 877 | .base_reg = MV64360_ENET2MEM_1_BASE, |
| 878 | .size_reg = MV64360_ENET2MEM_1_SIZE, |
| 879 | .base_bits = 16, |
| 880 | .size_bits = 16, |
| 881 | .get_from_field = mv64x60_mask, |
| 882 | .map_to_field = mv64x60_mask, |
| 883 | .extra = MV64x60_EXTRA_ENET_ENAB | 1 }, |
| 884 | [MV64x60_ENET2MEM_2_WIN] = { |
| 885 | .base_reg = MV64360_ENET2MEM_2_BASE, |
| 886 | .size_reg = MV64360_ENET2MEM_2_SIZE, |
| 887 | .base_bits = 16, |
| 888 | .size_bits = 16, |
| 889 | .get_from_field = mv64x60_mask, |
| 890 | .map_to_field = mv64x60_mask, |
| 891 | .extra = MV64x60_EXTRA_ENET_ENAB | 2 }, |
| 892 | [MV64x60_ENET2MEM_3_WIN] = { |
| 893 | .base_reg = MV64360_ENET2MEM_3_BASE, |
| 894 | .size_reg = MV64360_ENET2MEM_3_SIZE, |
| 895 | .base_bits = 16, |
| 896 | .size_bits = 16, |
| 897 | .get_from_field = mv64x60_mask, |
| 898 | .map_to_field = mv64x60_mask, |
| 899 | .extra = MV64x60_EXTRA_ENET_ENAB | 3 }, |
| 900 | [MV64x60_ENET2MEM_4_WIN] = { |
| 901 | .base_reg = MV64360_ENET2MEM_4_BASE, |
| 902 | .size_reg = MV64360_ENET2MEM_4_SIZE, |
| 903 | .base_bits = 16, |
| 904 | .size_bits = 16, |
| 905 | .get_from_field = mv64x60_mask, |
| 906 | .map_to_field = mv64x60_mask, |
| 907 | .extra = MV64x60_EXTRA_ENET_ENAB | 4 }, |
| 908 | [MV64x60_ENET2MEM_5_WIN] = { |
| 909 | .base_reg = MV64360_ENET2MEM_5_BASE, |
| 910 | .size_reg = MV64360_ENET2MEM_5_SIZE, |
| 911 | .base_bits = 16, |
| 912 | .size_bits = 16, |
| 913 | .get_from_field = mv64x60_mask, |
| 914 | .map_to_field = mv64x60_mask, |
| 915 | .extra = MV64x60_EXTRA_ENET_ENAB | 5 }, |
| 916 | /* MPSC->System Memory Windows */ |
| 917 | [MV64x60_MPSC2MEM_0_WIN] = { |
| 918 | .base_reg = MV64360_MPSC2MEM_0_BASE, |
| 919 | .size_reg = MV64360_MPSC2MEM_0_SIZE, |
| 920 | .base_bits = 16, |
| 921 | .size_bits = 16, |
| 922 | .get_from_field = mv64x60_mask, |
| 923 | .map_to_field = mv64x60_mask, |
| 924 | .extra = MV64x60_EXTRA_MPSC_ENAB | 0 }, |
| 925 | [MV64x60_MPSC2MEM_1_WIN] = { |
| 926 | .base_reg = MV64360_MPSC2MEM_1_BASE, |
| 927 | .size_reg = MV64360_MPSC2MEM_1_SIZE, |
| 928 | .base_bits = 16, |
| 929 | .size_bits = 16, |
| 930 | .get_from_field = mv64x60_mask, |
| 931 | .map_to_field = mv64x60_mask, |
| 932 | .extra = MV64x60_EXTRA_MPSC_ENAB | 1 }, |
| 933 | [MV64x60_MPSC2MEM_2_WIN] = { |
| 934 | .base_reg = MV64360_MPSC2MEM_2_BASE, |
| 935 | .size_reg = MV64360_MPSC2MEM_2_SIZE, |
| 936 | .base_bits = 16, |
| 937 | .size_bits = 16, |
| 938 | .get_from_field = mv64x60_mask, |
| 939 | .map_to_field = mv64x60_mask, |
| 940 | .extra = MV64x60_EXTRA_MPSC_ENAB | 2 }, |
| 941 | [MV64x60_MPSC2MEM_3_WIN] = { |
| 942 | .base_reg = MV64360_MPSC2MEM_3_BASE, |
| 943 | .size_reg = MV64360_MPSC2MEM_3_SIZE, |
| 944 | .base_bits = 16, |
| 945 | .size_bits = 16, |
| 946 | .get_from_field = mv64x60_mask, |
| 947 | .map_to_field = mv64x60_mask, |
| 948 | .extra = MV64x60_EXTRA_MPSC_ENAB | 3 }, |
| 949 | /* IDMA->System Memory Windows */ |
| 950 | [MV64x60_IDMA2MEM_0_WIN] = { |
| 951 | .base_reg = MV64360_IDMA2MEM_0_BASE, |
| 952 | .size_reg = MV64360_IDMA2MEM_0_SIZE, |
| 953 | .base_bits = 16, |
| 954 | .size_bits = 16, |
| 955 | .get_from_field = mv64x60_mask, |
| 956 | .map_to_field = mv64x60_mask, |
| 957 | .extra = MV64x60_EXTRA_IDMA_ENAB | 0 }, |
| 958 | [MV64x60_IDMA2MEM_1_WIN] = { |
| 959 | .base_reg = MV64360_IDMA2MEM_1_BASE, |
| 960 | .size_reg = MV64360_IDMA2MEM_1_SIZE, |
| 961 | .base_bits = 16, |
| 962 | .size_bits = 16, |
| 963 | .get_from_field = mv64x60_mask, |
| 964 | .map_to_field = mv64x60_mask, |
| 965 | .extra = MV64x60_EXTRA_IDMA_ENAB | 1 }, |
| 966 | [MV64x60_IDMA2MEM_2_WIN] = { |
| 967 | .base_reg = MV64360_IDMA2MEM_2_BASE, |
| 968 | .size_reg = MV64360_IDMA2MEM_2_SIZE, |
| 969 | .base_bits = 16, |
| 970 | .size_bits = 16, |
| 971 | .get_from_field = mv64x60_mask, |
| 972 | .map_to_field = mv64x60_mask, |
| 973 | .extra = MV64x60_EXTRA_IDMA_ENAB | 2 }, |
| 974 | [MV64x60_IDMA2MEM_3_WIN] = { |
| 975 | .base_reg = MV64360_IDMA2MEM_3_BASE, |
| 976 | .size_reg = MV64360_IDMA2MEM_3_SIZE, |
| 977 | .base_bits = 16, |
| 978 | .size_bits = 16, |
| 979 | .get_from_field = mv64x60_mask, |
| 980 | .map_to_field = mv64x60_mask, |
| 981 | .extra = MV64x60_EXTRA_IDMA_ENAB | 3 }, |
| 982 | [MV64x60_IDMA2MEM_4_WIN] = { |
| 983 | .base_reg = MV64360_IDMA2MEM_4_BASE, |
| 984 | .size_reg = MV64360_IDMA2MEM_4_SIZE, |
| 985 | .base_bits = 16, |
| 986 | .size_bits = 16, |
| 987 | .get_from_field = mv64x60_mask, |
| 988 | .map_to_field = mv64x60_mask, |
| 989 | .extra = MV64x60_EXTRA_IDMA_ENAB | 4 }, |
| 990 | [MV64x60_IDMA2MEM_5_WIN] = { |
| 991 | .base_reg = MV64360_IDMA2MEM_5_BASE, |
| 992 | .size_reg = MV64360_IDMA2MEM_5_SIZE, |
| 993 | .base_bits = 16, |
| 994 | .size_bits = 16, |
| 995 | .get_from_field = mv64x60_mask, |
| 996 | .map_to_field = mv64x60_mask, |
| 997 | .extra = MV64x60_EXTRA_IDMA_ENAB | 5 }, |
| 998 | [MV64x60_IDMA2MEM_6_WIN] = { |
| 999 | .base_reg = MV64360_IDMA2MEM_6_BASE, |
| 1000 | .size_reg = MV64360_IDMA2MEM_6_SIZE, |
| 1001 | .base_bits = 16, |
| 1002 | .size_bits = 16, |
| 1003 | .get_from_field = mv64x60_mask, |
| 1004 | .map_to_field = mv64x60_mask, |
| 1005 | .extra = MV64x60_EXTRA_IDMA_ENAB | 6 }, |
| 1006 | [MV64x60_IDMA2MEM_7_WIN] = { |
| 1007 | .base_reg = MV64360_IDMA2MEM_7_BASE, |
| 1008 | .size_reg = MV64360_IDMA2MEM_7_SIZE, |
| 1009 | .base_bits = 16, |
| 1010 | .size_bits = 16, |
| 1011 | .get_from_field = mv64x60_mask, |
| 1012 | .map_to_field = mv64x60_mask, |
| 1013 | .extra = MV64x60_EXTRA_IDMA_ENAB | 7 }, |
| 1014 | }; |
| 1015 | |
| 1016 | struct mv64x60_64bit_window |
| 1017 | mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT] __initdata = { |
| 1018 | /* CPU->PCI 0 MEM Remap Windows */ |
| 1019 | [MV64x60_CPU2PCI0_MEM_0_REMAP_WIN] = { |
| 1020 | .base_hi_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_HI, |
| 1021 | .base_lo_reg = MV64x60_CPU2PCI0_MEM_0_REMAP_LO, |
| 1022 | .size_reg = 0, |
| 1023 | .base_lo_bits = 16, |
| 1024 | .size_bits = 0, |
| 1025 | .get_from_field = mv64x60_shift_left, |
| 1026 | .map_to_field = mv64x60_shift_right, |
| 1027 | .extra = 0 }, |
| 1028 | [MV64x60_CPU2PCI0_MEM_1_REMAP_WIN] = { |
| 1029 | .base_hi_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_HI, |
| 1030 | .base_lo_reg = MV64x60_CPU2PCI0_MEM_1_REMAP_LO, |
| 1031 | .size_reg = 0, |
| 1032 | .base_lo_bits = 16, |
| 1033 | .size_bits = 0, |
| 1034 | .get_from_field = mv64x60_shift_left, |
| 1035 | .map_to_field = mv64x60_shift_right, |
| 1036 | .extra = 0 }, |
| 1037 | [MV64x60_CPU2PCI0_MEM_2_REMAP_WIN] = { |
| 1038 | .base_hi_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_HI, |
| 1039 | .base_lo_reg = MV64x60_CPU2PCI0_MEM_2_REMAP_LO, |
| 1040 | .size_reg = 0, |
| 1041 | .base_lo_bits = 16, |
| 1042 | .size_bits = 0, |
| 1043 | .get_from_field = mv64x60_shift_left, |
| 1044 | .map_to_field = mv64x60_shift_right, |
| 1045 | .extra = 0 }, |
| 1046 | [MV64x60_CPU2PCI0_MEM_3_REMAP_WIN] = { |
| 1047 | .base_hi_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_HI, |
| 1048 | .base_lo_reg = MV64x60_CPU2PCI0_MEM_3_REMAP_LO, |
| 1049 | .size_reg = 0, |
| 1050 | .base_lo_bits = 16, |
| 1051 | .size_bits = 0, |
| 1052 | .get_from_field = mv64x60_shift_left, |
| 1053 | .map_to_field = mv64x60_shift_right, |
| 1054 | .extra = 0 }, |
| 1055 | /* CPU->PCI 1 MEM Remap Windows */ |
| 1056 | [MV64x60_CPU2PCI1_MEM_0_REMAP_WIN] = { |
| 1057 | .base_hi_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_HI, |
| 1058 | .base_lo_reg = MV64x60_CPU2PCI1_MEM_0_REMAP_LO, |
| 1059 | .size_reg = 0, |
| 1060 | .base_lo_bits = 16, |
| 1061 | .size_bits = 0, |
| 1062 | .get_from_field = mv64x60_shift_left, |
| 1063 | .map_to_field = mv64x60_shift_right, |
| 1064 | .extra = 0 }, |
| 1065 | [MV64x60_CPU2PCI1_MEM_1_REMAP_WIN] = { |
| 1066 | .base_hi_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_HI, |
| 1067 | .base_lo_reg = MV64x60_CPU2PCI1_MEM_1_REMAP_LO, |
| 1068 | .size_reg = 0, |
| 1069 | .base_lo_bits = 16, |
| 1070 | .size_bits = 0, |
| 1071 | .get_from_field = mv64x60_shift_left, |
| 1072 | .map_to_field = mv64x60_shift_right, |
| 1073 | .extra = 0 }, |
| 1074 | [MV64x60_CPU2PCI1_MEM_2_REMAP_WIN] = { |
| 1075 | .base_hi_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_HI, |
| 1076 | .base_lo_reg = MV64x60_CPU2PCI1_MEM_2_REMAP_LO, |
| 1077 | .size_reg = 0, |
| 1078 | .base_lo_bits = 16, |
| 1079 | .size_bits = 0, |
| 1080 | .get_from_field = mv64x60_shift_left, |
| 1081 | .map_to_field = mv64x60_shift_right, |
| 1082 | .extra = 0 }, |
| 1083 | [MV64x60_CPU2PCI1_MEM_3_REMAP_WIN] = { |
| 1084 | .base_hi_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_HI, |
| 1085 | .base_lo_reg = MV64x60_CPU2PCI1_MEM_3_REMAP_LO, |
| 1086 | .size_reg = 0, |
| 1087 | .base_lo_bits = 16, |
| 1088 | .size_bits = 0, |
| 1089 | .get_from_field = mv64x60_shift_left, |
| 1090 | .map_to_field = mv64x60_shift_right, |
| 1091 | .extra = 0 }, |
| 1092 | /* PCI 0->MEM Access Control Windows */ |
| 1093 | [MV64x60_PCI02MEM_ACC_CNTL_0_WIN] = { |
| 1094 | .base_hi_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_HI, |
| 1095 | .base_lo_reg = MV64x60_PCI0_ACC_CNTL_0_BASE_LO, |
| 1096 | .size_reg = MV64x60_PCI0_ACC_CNTL_0_SIZE, |
| 1097 | .base_lo_bits = 20, |
| 1098 | .size_bits = 20, |
| 1099 | .get_from_field = mv64x60_mask, |
| 1100 | .map_to_field = mv64x60_mask, |
| 1101 | .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, |
| 1102 | [MV64x60_PCI02MEM_ACC_CNTL_1_WIN] = { |
| 1103 | .base_hi_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_HI, |
| 1104 | .base_lo_reg = MV64x60_PCI0_ACC_CNTL_1_BASE_LO, |
| 1105 | .size_reg = MV64x60_PCI0_ACC_CNTL_1_SIZE, |
| 1106 | .base_lo_bits = 20, |
| 1107 | .size_bits = 20, |
| 1108 | .get_from_field = mv64x60_mask, |
| 1109 | .map_to_field = mv64x60_mask, |
| 1110 | .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, |
| 1111 | [MV64x60_PCI02MEM_ACC_CNTL_2_WIN] = { |
| 1112 | .base_hi_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_HI, |
| 1113 | .base_lo_reg = MV64x60_PCI0_ACC_CNTL_2_BASE_LO, |
| 1114 | .size_reg = MV64x60_PCI0_ACC_CNTL_2_SIZE, |
| 1115 | .base_lo_bits = 20, |
| 1116 | .size_bits = 20, |
| 1117 | .get_from_field = mv64x60_mask, |
| 1118 | .map_to_field = mv64x60_mask, |
| 1119 | .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, |
| 1120 | [MV64x60_PCI02MEM_ACC_CNTL_3_WIN] = { |
| 1121 | .base_hi_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_HI, |
| 1122 | .base_lo_reg = MV64x60_PCI0_ACC_CNTL_3_BASE_LO, |
| 1123 | .size_reg = MV64x60_PCI0_ACC_CNTL_3_SIZE, |
| 1124 | .base_lo_bits = 20, |
| 1125 | .size_bits = 20, |
| 1126 | .get_from_field = mv64x60_mask, |
| 1127 | .map_to_field = mv64x60_mask, |
| 1128 | .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, |
| 1129 | /* PCI 1->MEM Access Control Windows */ |
| 1130 | [MV64x60_PCI12MEM_ACC_CNTL_0_WIN] = { |
| 1131 | .base_hi_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_HI, |
| 1132 | .base_lo_reg = MV64x60_PCI1_ACC_CNTL_0_BASE_LO, |
| 1133 | .size_reg = MV64x60_PCI1_ACC_CNTL_0_SIZE, |
| 1134 | .base_lo_bits = 20, |
| 1135 | .size_bits = 20, |
| 1136 | .get_from_field = mv64x60_mask, |
| 1137 | .map_to_field = mv64x60_mask, |
| 1138 | .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, |
| 1139 | [MV64x60_PCI12MEM_ACC_CNTL_1_WIN] = { |
| 1140 | .base_hi_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_HI, |
| 1141 | .base_lo_reg = MV64x60_PCI1_ACC_CNTL_1_BASE_LO, |
| 1142 | .size_reg = MV64x60_PCI1_ACC_CNTL_1_SIZE, |
| 1143 | .base_lo_bits = 20, |
| 1144 | .size_bits = 20, |
| 1145 | .get_from_field = mv64x60_mask, |
| 1146 | .map_to_field = mv64x60_mask, |
| 1147 | .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, |
| 1148 | [MV64x60_PCI12MEM_ACC_CNTL_2_WIN] = { |
| 1149 | .base_hi_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_HI, |
| 1150 | .base_lo_reg = MV64x60_PCI1_ACC_CNTL_2_BASE_LO, |
| 1151 | .size_reg = MV64x60_PCI1_ACC_CNTL_2_SIZE, |
| 1152 | .base_lo_bits = 20, |
| 1153 | .size_bits = 20, |
| 1154 | .get_from_field = mv64x60_mask, |
| 1155 | .map_to_field = mv64x60_mask, |
| 1156 | .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, |
| 1157 | [MV64x60_PCI12MEM_ACC_CNTL_3_WIN] = { |
| 1158 | .base_hi_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_HI, |
| 1159 | .base_lo_reg = MV64x60_PCI1_ACC_CNTL_3_BASE_LO, |
| 1160 | .size_reg = MV64x60_PCI1_ACC_CNTL_3_SIZE, |
| 1161 | .base_lo_bits = 20, |
| 1162 | .size_bits = 20, |
| 1163 | .get_from_field = mv64x60_mask, |
| 1164 | .map_to_field = mv64x60_mask, |
| 1165 | .extra = MV64x60_EXTRA_PCIACC_ENAB | 0 }, |
| 1166 | /* PCI 0->MEM Snoop Windows -- don't exist on 64360 */ |
| 1167 | /* PCI 1->MEM Snoop Windows -- don't exist on 64360 */ |
| 1168 | }; |