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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
2 * head.S: Initial boot code for the Sparc64 port of Linux.
3 *
4 * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
6 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 */
9
Linus Torvalds1da177e2005-04-16 15:20:36 -070010#include <linux/version.h>
11#include <linux/errno.h>
David S. Miller951bc822006-05-31 01:24:02 -070012#include <linux/threads.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <asm/thread_info.h>
14#include <asm/asi.h>
15#include <asm/pstate.h>
16#include <asm/ptrace.h>
17#include <asm/spitfire.h>
18#include <asm/page.h>
19#include <asm/pgtable.h>
20#include <asm/errno.h>
21#include <asm/signal.h>
22#include <asm/processor.h>
23#include <asm/lsu.h>
24#include <asm/dcr.h>
25#include <asm/dcu.h>
26#include <asm/head.h>
27#include <asm/ttable.h>
28#include <asm/mmu.h>
David S. Miller56fb4df2006-02-26 23:24:22 -080029#include <asm/cpudata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
31/* This section from from _start to sparc64_boot_end should fit into
David S. Millerc9c10832005-10-12 12:22:46 -070032 * 0x0000000000404000 to 0x0000000000408000.
Linus Torvalds1da177e2005-04-16 15:20:36 -070033 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070034 .text
35 .globl start, _start, stext, _stext
36_start:
37start:
38_stext:
39stext:
Linus Torvalds1da177e2005-04-16 15:20:36 -070040! 0x0000000000404000
41 b sparc64_boot
42 flushw /* Flush register file. */
43
44/* This stuff has to be in sync with SILO and other potential boot loaders
45 * Fields should be kept upward compatible and whenever any change is made,
46 * HdrS version should be incremented.
47 */
48 .global root_flags, ram_flags, root_dev
49 .global sparc_ramdisk_image, sparc_ramdisk_size
50 .global sparc_ramdisk_image64
51
52 .ascii "HdrS"
53 .word LINUX_VERSION_CODE
54
55 /* History:
56 *
57 * 0x0300 : Supports being located at other than 0x4000
58 * 0x0202 : Supports kernel params string
59 * 0x0201 : Supports reboot_command
60 */
61 .half 0x0301 /* HdrS version */
62
63root_flags:
64 .half 1
65root_dev:
66 .half 0
67ram_flags:
68 .half 0
69sparc_ramdisk_image:
70 .word 0
71sparc_ramdisk_size:
72 .word 0
73 .xword reboot_command
74 .xword bootstr_info
75sparc_ramdisk_image64:
76 .xword 0
77 .word _end
78
David S. Millerbff06d52005-09-22 20:11:33 -070079 /* PROM cif handler code address is in %o4. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070080sparc64_boot:
David S. Millerbff06d52005-09-22 20:11:33 -0700811: rd %pc, %g7
82 set 1b, %g1
83 cmp %g1, %g7
84 be,pn %xcc, sparc64_boot_after_remap
85 mov %o4, %l7
86
87 /* We need to remap the kernel. Use position independant
88 * code to remap us to KERNBASE.
89 *
90 * SILO can invoke us with 32-bit address masking enabled,
91 * so make sure that's clear.
92 */
93 rdpr %pstate, %g1
94 andn %g1, PSTATE_AM, %g1
95 wrpr %g1, 0x0, %pstate
96 ba,a,pt %xcc, 1f
97
David S. Millerd82ace72006-02-09 02:52:44 -080098 .globl prom_finddev_name, prom_chosen_path, prom_root_node
99 .globl prom_getprop_name, prom_mmu_name, prom_peer_name
100 .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
David S. Millerbff06d52005-09-22 20:11:33 -0700101 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
102 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
103 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
David S. Millerd82ace72006-02-09 02:52:44 -0800104 .globl is_sun4v
105prom_peer_name:
106 .asciz "peer"
107prom_compatible_name:
108 .asciz "compatible"
David S. Millerbff06d52005-09-22 20:11:33 -0700109prom_finddev_name:
110 .asciz "finddevice"
111prom_chosen_path:
112 .asciz "/chosen"
113prom_getprop_name:
114 .asciz "getprop"
115prom_mmu_name:
116 .asciz "mmu"
117prom_callmethod_name:
118 .asciz "call-method"
119prom_translate_name:
120 .asciz "translate"
121prom_map_name:
122 .asciz "map"
123prom_unmap_name:
124 .asciz "unmap"
David S. Millerd82ace72006-02-09 02:52:44 -0800125prom_sun4v_name:
David S. Miller6cebb522006-02-11 10:56:43 -0800126 .asciz "sun4v"
David S. Millerbff06d52005-09-22 20:11:33 -0700127 .align 4
David S. Millerd82ace72006-02-09 02:52:44 -0800128prom_root_compatible:
129 .skip 64
130prom_root_node:
131 .word 0
David S. Millerbff06d52005-09-22 20:11:33 -0700132prom_mmu_ihandle_cache:
133 .word 0
134prom_boot_mapped_pc:
135 .word 0
136prom_boot_mapping_mode:
137 .word 0
138 .align 8
139prom_boot_mapping_phys_high:
140 .xword 0
141prom_boot_mapping_phys_low:
142 .xword 0
David S. Millerd82ace72006-02-09 02:52:44 -0800143is_sun4v:
144 .word 0
David S. Millerbff06d52005-09-22 20:11:33 -07001451:
146 rd %pc, %l0
David S. Millerd82ace72006-02-09 02:52:44 -0800147
148 mov (1b - prom_peer_name), %l1
149 sub %l0, %l1, %l1
150 mov 0, %l2
151
152 /* prom_root_node = prom_peer(0) */
153 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
154 mov 1, %l3
155 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
156 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
157 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
158 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
159 call %l7
160 add %sp, (2047 + 128), %o0 ! argument array
161
162 ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
163 mov (1b - prom_root_node), %l1
164 sub %l0, %l1, %l1
165 stw %l4, [%l1]
166
167 mov (1b - prom_getprop_name), %l1
168 mov (1b - prom_compatible_name), %l2
169 mov (1b - prom_root_compatible), %l5
170 sub %l0, %l1, %l1
171 sub %l0, %l2, %l2
172 sub %l0, %l5, %l5
173
174 /* prom_getproperty(prom_root_node, "compatible",
175 * &prom_root_compatible, 64)
176 */
177 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
178 mov 4, %l3
179 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
180 mov 1, %l3
181 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
182 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
183 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
184 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
185 mov 64, %l3
186 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
187 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
188 call %l7
189 add %sp, (2047 + 128), %o0 ! argument array
190
David S. Millerbff06d52005-09-22 20:11:33 -0700191 mov (1b - prom_finddev_name), %l1
192 mov (1b - prom_chosen_path), %l2
193 mov (1b - prom_boot_mapped_pc), %l3
194 sub %l0, %l1, %l1
195 sub %l0, %l2, %l2
196 sub %l0, %l3, %l3
197 stw %l0, [%l3]
198 sub %sp, (192 + 128), %sp
199
200 /* chosen_node = prom_finddevice("/chosen") */
201 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
202 mov 1, %l3
203 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
204 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
205 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
206 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
207 call %l7
208 add %sp, (2047 + 128), %o0 ! argument array
209
210 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
211
212 mov (1b - prom_getprop_name), %l1
213 mov (1b - prom_mmu_name), %l2
214 mov (1b - prom_mmu_ihandle_cache), %l5
215 sub %l0, %l1, %l1
216 sub %l0, %l2, %l2
217 sub %l0, %l5, %l5
218
219 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
220 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
221 mov 4, %l3
222 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
223 mov 1, %l3
224 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
225 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
226 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
227 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
228 mov 4, %l3
229 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
230 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
231 call %l7
232 add %sp, (2047 + 128), %o0 ! argument array
233
234 mov (1b - prom_callmethod_name), %l1
235 mov (1b - prom_translate_name), %l2
236 sub %l0, %l1, %l1
237 sub %l0, %l2, %l2
238 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
239
240 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
241 mov 3, %l3
242 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
243 mov 5, %l3
244 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
245 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
246 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
David S. Millerb1b510a2005-10-11 15:45:16 -0700247 /* PAGE align */
248 srlx %l0, 13, %l3
249 sllx %l3, 13, %l3
David S. Millerbff06d52005-09-22 20:11:33 -0700250 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
251 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
252 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
253 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
254 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
255 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
256 call %l7
257 add %sp, (2047 + 128), %o0 ! argument array
258
259 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
260 mov (1b - prom_boot_mapping_mode), %l4
261 sub %l0, %l4, %l4
262 stw %l1, [%l4]
263 mov (1b - prom_boot_mapping_phys_high), %l4
264 sub %l0, %l4, %l4
265 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
266 stx %l2, [%l4 + 0x0]
267 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
David S. Millerb1b510a2005-10-11 15:45:16 -0700268 /* 4MB align */
269 srlx %l3, 22, %l3
270 sllx %l3, 22, %l3
David S. Millerbff06d52005-09-22 20:11:33 -0700271 stx %l3, [%l4 + 0x8]
272
273 /* Leave service as-is, "call-method" */
274 mov 7, %l3
275 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
276 mov 1, %l3
David S. Millera8201c62005-09-22 20:31:29 -0700277 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
David S. Millerbff06d52005-09-22 20:11:33 -0700278 mov (1b - prom_map_name), %l3
279 sub %l0, %l3, %l3
280 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
281 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
282 mov -1, %l3
283 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
284 sethi %hi(8 * 1024 * 1024), %l3
285 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB)
286 sethi %hi(KERNBASE), %l3
287 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
288 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
289 mov (1b - prom_boot_mapping_phys_low), %l3
290 sub %l0, %l3, %l3
291 ldx [%l3], %l3
292 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
293 call %l7
294 add %sp, (2047 + 128), %o0 ! argument array
295
296 add %sp, (192 + 128), %sp
297
298sparc64_boot_after_remap:
David S. Millerd82ace72006-02-09 02:52:44 -0800299 sethi %hi(prom_root_compatible), %g1
300 or %g1, %lo(prom_root_compatible), %g1
301 sethi %hi(prom_sun4v_name), %g7
302 or %g7, %lo(prom_sun4v_name), %g7
David S. Miller6cebb522006-02-11 10:56:43 -0800303 mov 5, %g3
David S. Millerd82ace72006-02-09 02:52:44 -08003041: ldub [%g7], %g2
305 ldub [%g1], %g4
306 cmp %g2, %g4
307 bne,pn %icc, 2f
308 add %g7, 1, %g7
309 subcc %g3, 1, %g3
310 bne,pt %xcc, 1b
311 add %g1, 1, %g1
312
313 sethi %hi(is_sun4v), %g1
314 or %g1, %lo(is_sun4v), %g1
315 mov 1, %g7
316 stw %g7, [%g1]
317
3182:
319 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
321 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
322 ba,pt %xcc, spitfire_boot
323 nop
324
325cheetah_plus_boot:
326 /* Preserve OBP chosen DCU and DCR register settings. */
327 ba,pt %xcc, cheetah_generic_boot
328 nop
329
330cheetah_boot:
331 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
332 wr %g1, %asr18
333
334 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
335 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
336 sllx %g7, 32, %g7
337 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
338 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
339 membar #Sync
340
341cheetah_generic_boot:
342 mov TSB_EXTENSION_P, %g3
343 stxa %g0, [%g3] ASI_DMMU
344 stxa %g0, [%g3] ASI_IMMU
345 membar #Sync
346
347 mov TSB_EXTENSION_S, %g3
348 stxa %g0, [%g3] ASI_DMMU
349 membar #Sync
350
351 mov TSB_EXTENSION_N, %g3
352 stxa %g0, [%g3] ASI_DMMU
353 stxa %g0, [%g3] ASI_IMMU
354 membar #Sync
355
David S. Millerbff06d52005-09-22 20:11:33 -0700356 ba,a,pt %xcc, jump_to_sun4u_init
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357
358spitfire_boot:
359 /* Typically PROM has already enabled both MMU's and both on-chip
360 * caches, but we do it here anyway just to be paranoid.
361 */
362 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
363 stxa %g1, [%g0] ASI_LSU_CONTROL
364 membar #Sync
365
David S. Millerbff06d52005-09-22 20:11:33 -0700366jump_to_sun4u_init:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 /*
368 * Make sure we are in privileged mode, have address masking,
369 * using the ordinary globals and have enabled floating
370 * point.
371 *
372 * Again, typically PROM has left %pil at 13 or similar, and
373 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
374 */
375 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
376 wr %g0, 0, %fprs
377
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 set sun4u_init, %g2
379 jmpl %g2 + %g0, %g0
380 nop
381
382sun4u_init:
David S. Miller6cebb522006-02-11 10:56:43 -0800383 BRANCH_IF_SUN4V(g1, sun4v_init)
384
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385 /* Set ctx 0 */
David S. Miller8b11bd12006-02-07 22:13:05 -0800386 mov PRIMARY_CONTEXT, %g7
David S. Miller6cebb522006-02-11 10:56:43 -0800387 stxa %g0, [%g7] ASI_DMMU
David S. Miller8b11bd12006-02-07 22:13:05 -0800388 membar #Sync
389
390 mov SECONDARY_CONTEXT, %g7
David S. Miller6cebb522006-02-11 10:56:43 -0800391 stxa %g0, [%g7] ASI_DMMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 membar #Sync
393
David S. Miller6cebb522006-02-11 10:56:43 -0800394 ba,pt %xcc, sun4u_continue
395 nop
396
397sun4v_init:
398 /* Set ctx 0 */
399 mov PRIMARY_CONTEXT, %g7
400 stxa %g0, [%g7] ASI_MMU
401 membar #Sync
402
403 mov SECONDARY_CONTEXT, %g7
404 stxa %g0, [%g7] ASI_MMU
405 membar #Sync
406 ba,pt %xcc, niagara_tlb_fixup
407 nop
408
409sun4u_continue:
David S. Millerd82ace72006-02-09 02:52:44 -0800410 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411
412 ba,pt %xcc, spitfire_tlb_fixup
413 nop
414
David S. Miller8591e302006-02-07 16:09:12 -0800415niagara_tlb_fixup:
416 mov 3, %g2 /* Set TLB type to hypervisor. */
417 sethi %hi(tlb_type), %g1
418 stw %g2, [%g1 + %lo(tlb_type)]
419
420 /* Patch copy/clear ops. */
421 call niagara_patch_copyops
422 nop
David S. Miller8ca25572006-02-21 14:29:42 -0800423 call niagara_patch_bzero
424 nop
David S. Miller8591e302006-02-07 16:09:12 -0800425 call niagara_patch_pageops
426 nop
427
428 /* Patch TLB/cache ops. */
429 call hypervisor_patch_cachetlbops
430 nop
431
David S. Millerd82ace72006-02-09 02:52:44 -0800432 ba,pt %xcc, tlb_fixup_done
433 nop
434
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435cheetah_tlb_fixup:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 mov 2, %g2 /* Set TLB type to cheetah+. */
437 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
438
439 mov 1, %g2 /* Set TLB type to cheetah. */
440
4411: sethi %hi(tlb_type), %g1
442 stw %g2, [%g1 + %lo(tlb_type)]
443
David S. Miller0835ae02005-10-04 15:23:20 -0700444 /* Patch copy/page operations to cheetah optimized versions. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 call cheetah_patch_copyops
446 nop
David S. Millerdbd2fdf2005-08-30 11:26:15 -0700447 call cheetah_patch_copy_page
448 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449 call cheetah_patch_cachetlbops
450 nop
451
452 ba,pt %xcc, tlb_fixup_done
453 nop
454
455spitfire_tlb_fixup:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456 /* Set TLB type to spitfire. */
457 mov 0, %g2
458 sethi %hi(tlb_type), %g1
459 stw %g2, [%g1 + %lo(tlb_type)]
460
461tlb_fixup_done:
462 sethi %hi(init_thread_union), %g6
463 or %g6, %lo(init_thread_union), %g6
464 ldx [%g6 + TI_TASK], %g4
465 mov %sp, %l6
466 mov %o4, %l7
467
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468 wr %g0, ASI_P, %asi
469 mov 1, %g1
470 sllx %g1, THREAD_SHIFT, %g1
471 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
472 add %g6, %g1, %sp
473 mov 0, %fp
474
475 /* Set per-cpu pointer initially to zero, this makes
476 * the boot-cpu use the in-kernel-image per-cpu areas
477 * before setup_per_cpu_area() is invoked.
478 */
479 clr %g5
480
481 wrpr %g0, 0, %wstate
482 wrpr %g0, 0x0, %tl
483
484 /* Clear the bss */
485 sethi %hi(__bss_start), %o0
486 or %o0, %lo(__bss_start), %o0
487 sethi %hi(_end), %o1
488 or %o1, %lo(_end), %o1
489 call __bzero
490 sub %o1, %o0, %o1
491
492 mov %l6, %o1 ! OpenPROM stack
493 call prom_init
494 mov %l7, %o0 ! OpenPROM cif handler
495
David S. Miller951bc822006-05-31 01:24:02 -0700496 /* Initialize current_thread_info()->cpu as early as possible.
497 * In order to do that accurately we have to patch up the get_cpuid()
498 * assembler sequences. And that, in turn, requires that we know
499 * if we are on a Starfire box or not. While we're here, patch up
500 * the sun4v sequences as well.
501 */
502 call check_if_starfire
503 nop
504 call per_cpu_patch
505 nop
506 call sun4v_patch
507 nop
508
509#ifdef CONFIG_SMP
510 call hard_smp_processor_id
511 nop
512 cmp %o0, NR_CPUS
513 blu,pt %xcc, 1f
514 nop
515 call boot_cpu_id_too_large
516 nop
517 /* Not reached... */
518
5191:
520#else
521 mov 0, %o0
522#endif
523 stb %o0, [%g6 + TI_CPU]
524
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 /* Off we go.... */
526 call start_kernel
527 nop
528 /* Not reached... */
529
David S. Miller5d8e1b12005-10-10 16:12:13 -0700530 /* This is meant to allow the sharing of this code between
531 * boot processor invocation (via setup_tba() below) and
532 * secondary processor startup (via trampoline.S). The
533 * former does use this code, the latter does not yet due
534 * to some complexities. That should be fixed up at some
535 * point.
David S. Millerc9c10832005-10-12 12:22:46 -0700536 *
537 * There used to be enormous complexity wrt. transferring
538 * over from the firwmare's trap table to the Linux kernel's.
539 * For example, there was a chicken & egg problem wrt. building
540 * the OBP page tables, yet needing to be on the Linux kernel
541 * trap table (to translate PAGE_OFFSET addresses) in order to
542 * do that.
543 *
544 * We now handle OBP tlb misses differently, via linear lookups
545 * into the prom_trans[] array. So that specific problem no
546 * longer exists. Yet, unfortunately there are still some issues
547 * preventing trampoline.S from using this code... ho hum.
David S. Miller5d8e1b12005-10-10 16:12:13 -0700548 */
549 .globl setup_trap_table
550setup_trap_table:
551 save %sp, -192, %sp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552
David S. Millerc9c10832005-10-12 12:22:46 -0700553 /* Force interrupts to be disabled. */
David S. Millerd8573e22006-07-13 16:05:26 -0700554 rdpr %pstate, %l0
555 andn %l0, PSTATE_IE, %o1
David S. Miller5d8e1b12005-10-10 16:12:13 -0700556 wrpr %o1, 0x0, %pstate
David S. Millerd8573e22006-07-13 16:05:26 -0700557 rdpr %pil, %l1
David S. Miller5d8e1b12005-10-10 16:12:13 -0700558 wrpr %g0, 15, %pil
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559
David S. Millerc9c10832005-10-12 12:22:46 -0700560 /* Make the firmware call to jump over to the Linux trap table. */
David S. Miller12eaa322006-02-10 15:39:51 -0800561 sethi %hi(is_sun4v), %o0
562 lduw [%o0 + %lo(is_sun4v)], %o0
563 brz,pt %o0, 1f
564 nop
565
566 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
567 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
568 stxa %g2, [%g0] ASI_SCRATCHPAD
569
570 /* Compute physical address:
571 *
572 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
573 */
574 sethi %hi(KERNBASE), %g3
575 sub %g2, %g3, %g2
576 sethi %hi(kern_base), %g3
577 ldx [%g3 + %lo(kern_base)], %g3
578 add %g2, %g3, %o1
579
580 call prom_set_trap_table_sun4v
581 sethi %hi(sparc64_ttable_tl0), %o0
582
583 ba,pt %xcc, 2f
584 nop
585
5861: call prom_set_trap_table
David S. Miller5d8e1b12005-10-10 16:12:13 -0700587 sethi %hi(sparc64_ttable_tl0), %o0
588
589 /* Start using proper page size encodings in ctx register. */
David S. Miller12eaa322006-02-10 15:39:51 -08005902: sethi %hi(sparc64_kern_pri_context), %g3
David S. Miller5d8e1b12005-10-10 16:12:13 -0700591 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
David S. Miller8b11bd12006-02-07 22:13:05 -0800592
593 mov PRIMARY_CONTEXT, %g1
594
595661: stxa %g2, [%g1] ASI_DMMU
596 .section .sun4v_1insn_patch, "ax"
597 .word 661b
598 stxa %g2, [%g1] ASI_MMU
599 .previous
600
David S. Miller5d8e1b12005-10-10 16:12:13 -0700601 membar #Sync
602
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603 /* Kill PROM timer */
604 sethi %hi(0x80000000), %o2
605 sllx %o2, 32, %o2
606 wr %o2, 0, %tick_cmpr
607
David S. Millerd82ace72006-02-09 02:52:44 -0800608 BRANCH_IF_SUN4V(o2, 1f)
609 BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610
611 ba,pt %xcc, 2f
612 nop
613
614 /* Disable STICK_INT interrupts. */
6151:
616 sethi %hi(0x80000000), %o2
617 sllx %o2, 32, %o2
618 wr %o2, %asr25
619
Linus Torvalds1da177e2005-04-16 15:20:36 -07006202:
621 wrpr %g0, %g0, %wstate
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622
623 call init_irqwork_curcpu
624 nop
625
David S. Millerd8573e22006-07-13 16:05:26 -0700626 /* Now we can restore interrupt state. */
627 wrpr %l0, 0, %pstate
628 wrpr %l1, 0x0, %pil
David S. Miller5d8e1b12005-10-10 16:12:13 -0700629
630 ret
631 restore
632
633 .globl setup_tba
David S. Millera8b900d2006-01-31 18:33:37 -0800634setup_tba:
David S. Miller5d8e1b12005-10-10 16:12:13 -0700635 save %sp, -192, %sp
636
637 /* The boot processor is the only cpu which invokes this
638 * routine, the other cpus set things up via trampoline.S.
639 * So save the OBP trap table address here.
640 */
641 rdpr %tba, %g7
642 sethi %hi(prom_tba), %o1
643 or %o1, %lo(prom_tba), %o1
644 stx %g7, [%o1]
645
646 call setup_trap_table
647 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648
649 ret
650 restore
David S. Millerc9c10832005-10-12 12:22:46 -0700651sparc64_boot_end:
652
David S. Millerc9c10832005-10-12 12:22:46 -0700653#include "ktlb.S"
David S. Miller74bf4312006-01-31 18:29:18 -0800654#include "tsb.S"
David S. Millerc9c10832005-10-12 12:22:46 -0700655#include "etrap.S"
656#include "rtrap.S"
657#include "winfixup.S"
658#include "entry.S"
David S. Miller5b0c0572006-02-08 02:53:50 -0800659#include "sun4v_tlb_miss.S"
660#include "sun4v_ivec.S"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661
662/*
David S. Millerc9c10832005-10-12 12:22:46 -0700663 * The following skip makes sure the trap table in ttable.S is aligned
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664 * on a 32K boundary as required by the v9 specs for TBA register.
David S. Miller2f7ee7c2006-01-31 18:33:49 -0800665 *
666 * We align to a 32K boundary, then we have the 32K kernel TSB,
667 * then the 32K aligned trap table.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668 */
David S. Millerc9c10832005-10-12 12:22:46 -07006691:
670 .skip 0x4000 + _start - 1b
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671
David S. Miller2f7ee7c2006-01-31 18:33:49 -0800672 .globl swapper_tsb
673swapper_tsb:
674 .skip (32 * 1024)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675
676! 0x0000000000408000
677
678#include "ttable.S"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679
David S. Miller074d82c2006-02-23 02:28:25 -0800680#include "systbls.S"
681
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 .data
683 .align 8
684 .globl prom_tba, tlb_type
685prom_tba: .xword 0
686tlb_type: .word 0 /* Must NOT end up in BSS */
687 .section ".fixup",#alloc,#execinstr
David S. Miller5fd29752005-09-28 20:41:45 -0700688
689 .globl __ret_efault, __retl_efault
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690__ret_efault:
691 ret
692 restore %g0, -EFAULT, %o0
David S. Miller5fd29752005-09-28 20:41:45 -0700693__retl_efault:
694 retl
695 mov -EFAULT, %o0