Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* drivers/video/pvr2fb.c |
| 2 | * |
| 3 | * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega |
| 4 | * Dreamcast. |
| 5 | * |
| 6 | * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org> |
| 7 | * Copyright (c) 2001, 2002, 2003, 2004, 2005 Paul Mundt <lethal@linux-sh.org> |
| 8 | * |
| 9 | * This file is part of the LinuxDC project (linuxdc.sourceforge.net). |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * This driver is mostly based on the excellent amifb and vfb sources. It uses |
| 15 | * an odd scheme for converting hardware values to/from framebuffer values, |
| 16 | * here are some hacked-up formulas: |
| 17 | * |
| 18 | * The Dreamcast has screen offsets from each side of its four borders and |
| 19 | * the start offsets of the display window. I used these values to calculate |
| 20 | * 'pseudo' values (think of them as placeholders) for the fb video mode, so |
| 21 | * that when it came time to convert these values back into their hardware |
| 22 | * values, I could just add mode- specific offsets to get the correct mode |
| 23 | * settings: |
| 24 | * |
| 25 | * left_margin = diwstart_h - borderstart_h; |
| 26 | * right_margin = borderstop_h - (diwstart_h + xres); |
| 27 | * upper_margin = diwstart_v - borderstart_v; |
| 28 | * lower_margin = borderstop_v - (diwstart_h + yres); |
| 29 | * |
| 30 | * hsync_len = borderstart_h + (hsync_total - borderstop_h); |
| 31 | * vsync_len = borderstart_v + (vsync_total - borderstop_v); |
| 32 | * |
| 33 | * Then, when it's time to convert back to hardware settings, the only |
| 34 | * constants are the borderstart_* offsets, all other values are derived from |
| 35 | * the fb video mode: |
| 36 | * |
| 37 | * // PAL |
| 38 | * borderstart_h = 116; |
| 39 | * borderstart_v = 44; |
| 40 | * ... |
| 41 | * borderstop_h = borderstart_h + hsync_total - hsync_len; |
| 42 | * ... |
| 43 | * diwstart_v = borderstart_v - upper_margin; |
| 44 | * |
| 45 | * However, in the current implementation, the borderstart values haven't had |
| 46 | * the benefit of being fully researched, so some modes may be broken. |
| 47 | */ |
| 48 | |
| 49 | #undef DEBUG |
| 50 | |
| 51 | #include <linux/module.h> |
| 52 | #include <linux/kernel.h> |
| 53 | #include <linux/errno.h> |
| 54 | #include <linux/string.h> |
| 55 | #include <linux/mm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | #include <linux/slab.h> |
| 57 | #include <linux/delay.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | #include <linux/interrupt.h> |
| 59 | #include <linux/fb.h> |
| 60 | #include <linux/init.h> |
| 61 | #include <linux/pci.h> |
| 62 | |
| 63 | #ifdef CONFIG_SH_DREAMCAST |
| 64 | #include <asm/machvec.h> |
| 65 | #include <asm/mach/sysasic.h> |
| 66 | #endif |
| 67 | |
| 68 | #ifdef CONFIG_SH_DMA |
| 69 | #include <linux/pagemap.h> |
| 70 | #include <asm/mach/dma.h> |
| 71 | #include <asm/dma.h> |
| 72 | #endif |
| 73 | |
| 74 | #ifdef CONFIG_SH_STORE_QUEUES |
| 75 | #include <asm/uaccess.h> |
| 76 | #include <asm/cpu/sq.h> |
| 77 | #endif |
| 78 | |
| 79 | #ifndef PCI_DEVICE_ID_NEC_NEON250 |
| 80 | # define PCI_DEVICE_ID_NEC_NEON250 0x0067 |
| 81 | #endif |
| 82 | |
| 83 | /* 2D video registers */ |
| 84 | #define DISP_BASE par->mmio_base |
| 85 | #define DISP_BRDRCOLR (DISP_BASE + 0x40) |
| 86 | #define DISP_DIWMODE (DISP_BASE + 0x44) |
| 87 | #define DISP_DIWADDRL (DISP_BASE + 0x50) |
| 88 | #define DISP_DIWADDRS (DISP_BASE + 0x54) |
| 89 | #define DISP_DIWSIZE (DISP_BASE + 0x5c) |
| 90 | #define DISP_SYNCCONF (DISP_BASE + 0xd0) |
| 91 | #define DISP_BRDRHORZ (DISP_BASE + 0xd4) |
| 92 | #define DISP_SYNCSIZE (DISP_BASE + 0xd8) |
| 93 | #define DISP_BRDRVERT (DISP_BASE + 0xdc) |
| 94 | #define DISP_DIWCONF (DISP_BASE + 0xe8) |
| 95 | #define DISP_DIWHSTRT (DISP_BASE + 0xec) |
| 96 | #define DISP_DIWVSTRT (DISP_BASE + 0xf0) |
| 97 | |
| 98 | /* Pixel clocks, one for TV output, doubled for VGA output */ |
| 99 | #define TV_CLK 74239 |
| 100 | #define VGA_CLK 37119 |
| 101 | |
| 102 | /* This is for 60Hz - the VTOTAL is doubled for interlaced modes */ |
| 103 | #define PAL_HTOTAL 863 |
| 104 | #define PAL_VTOTAL 312 |
| 105 | #define NTSC_HTOTAL 857 |
| 106 | #define NTSC_VTOTAL 262 |
| 107 | |
| 108 | /* Supported cable types */ |
| 109 | enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE }; |
| 110 | |
| 111 | /* Supported video output types */ |
| 112 | enum { VO_PAL, VO_NTSC, VO_VGA }; |
| 113 | |
| 114 | /* Supported palette types */ |
| 115 | enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 }; |
| 116 | |
| 117 | struct pvr2_params { unsigned int val; char *name; }; |
| 118 | static struct pvr2_params cables[] __initdata = { |
| 119 | { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" }, |
| 120 | }; |
| 121 | |
| 122 | static struct pvr2_params outputs[] __initdata = { |
| 123 | { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" }, |
| 124 | }; |
| 125 | |
| 126 | /* |
| 127 | * This describes the current video mode |
| 128 | */ |
| 129 | |
| 130 | static struct pvr2fb_par { |
| 131 | unsigned int hsync_total; /* Clocks/line */ |
| 132 | unsigned int vsync_total; /* Lines/field */ |
| 133 | unsigned int borderstart_h; |
| 134 | unsigned int borderstop_h; |
| 135 | unsigned int borderstart_v; |
| 136 | unsigned int borderstop_v; |
| 137 | unsigned int diwstart_h; /* Horizontal offset of the display field */ |
| 138 | unsigned int diwstart_v; /* Vertical offset of the display field, for |
| 139 | interlaced modes, this is the long field */ |
| 140 | unsigned long disp_start; /* Address of image within VRAM */ |
| 141 | unsigned char is_interlaced; /* Is the display interlaced? */ |
| 142 | unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */ |
| 143 | unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */ |
| 144 | |
| 145 | unsigned long mmio_base; /* MMIO base */ |
| 146 | } *currentpar; |
| 147 | |
| 148 | static struct fb_info *fb_info; |
| 149 | |
| 150 | static struct fb_fix_screeninfo pvr2_fix __initdata = { |
| 151 | .id = "NEC PowerVR2", |
| 152 | .type = FB_TYPE_PACKED_PIXELS, |
| 153 | .visual = FB_VISUAL_TRUECOLOR, |
| 154 | .ypanstep = 1, |
| 155 | .ywrapstep = 1, |
| 156 | .accel = FB_ACCEL_NONE, |
| 157 | }; |
| 158 | |
| 159 | static struct fb_var_screeninfo pvr2_var __initdata = { |
| 160 | .xres = 640, |
| 161 | .yres = 480, |
| 162 | .xres_virtual = 640, |
| 163 | .yres_virtual = 480, |
| 164 | .bits_per_pixel =16, |
| 165 | .red = { 11, 5, 0 }, |
| 166 | .green = { 5, 6, 0 }, |
| 167 | .blue = { 0, 5, 0 }, |
| 168 | .activate = FB_ACTIVATE_NOW, |
| 169 | .height = -1, |
| 170 | .width = -1, |
| 171 | .vmode = FB_VMODE_NONINTERLACED, |
| 172 | }; |
| 173 | |
| 174 | static int cable_type = CT_VGA; |
| 175 | static int video_output = VO_VGA; |
| 176 | |
| 177 | static int nopan = 0; |
| 178 | static int nowrap = 1; |
| 179 | |
| 180 | /* |
| 181 | * We do all updating, blanking, etc. during the vertical retrace period |
| 182 | */ |
| 183 | static unsigned int do_vmode_full = 0; /* Change the video mode */ |
| 184 | static unsigned int do_vmode_pan = 0; /* Update the video mode */ |
| 185 | static short do_blank = 0; /* (Un)Blank the screen */ |
| 186 | |
| 187 | static unsigned int is_blanked = 0; /* Is the screen blanked? */ |
| 188 | |
| 189 | #ifdef CONFIG_SH_STORE_QUEUES |
| 190 | static struct sq_mapping *pvr2fb_map; |
| 191 | #endif |
| 192 | |
| 193 | #ifdef CONFIG_SH_DMA |
| 194 | static unsigned int shdma = PVR2_CASCADE_CHAN; |
| 195 | static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS; |
| 196 | #endif |
| 197 | |
| 198 | /* Interface used by the world */ |
| 199 | |
| 200 | int pvr2fb_setup(char*); |
| 201 | |
| 202 | static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue, |
| 203 | unsigned int transp, struct fb_info *info); |
| 204 | static int pvr2fb_blank(int blank, struct fb_info *info); |
| 205 | static unsigned long get_line_length(int xres_virtual, int bpp); |
| 206 | static void set_color_bitfields(struct fb_var_screeninfo *var); |
| 207 | static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info); |
| 208 | static int pvr2fb_set_par(struct fb_info *info); |
| 209 | static void pvr2_update_display(struct fb_info *info); |
| 210 | static void pvr2_init_display(struct fb_info *info); |
| 211 | static void pvr2_do_blank(void); |
| 212 | static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id, struct pt_regs *fp); |
| 213 | static int pvr2_init_cable(void); |
| 214 | static int pvr2_get_param(const struct pvr2_params *p, const char *s, |
| 215 | int val, int size); |
| 216 | static ssize_t pvr2fb_write(struct file *file, const char *buf, |
| 217 | size_t count, loff_t *ppos); |
| 218 | |
| 219 | static struct fb_ops pvr2fb_ops = { |
| 220 | .owner = THIS_MODULE, |
| 221 | .fb_setcolreg = pvr2fb_setcolreg, |
| 222 | .fb_blank = pvr2fb_blank, |
| 223 | .fb_check_var = pvr2fb_check_var, |
| 224 | .fb_set_par = pvr2fb_set_par, |
| 225 | #ifdef CONFIG_SH_DMA |
| 226 | .fb_write = pvr2fb_write, |
| 227 | #endif |
| 228 | .fb_fillrect = cfb_fillrect, |
| 229 | .fb_copyarea = cfb_copyarea, |
| 230 | .fb_imageblit = cfb_imageblit, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | }; |
| 232 | |
| 233 | static struct fb_videomode pvr2_modedb[] __initdata = { |
| 234 | /* |
| 235 | * Broadcast video modes (PAL and NTSC). I'm unfamiliar with |
| 236 | * PAL-M and PAL-N, but from what I've read both modes parallel PAL and |
| 237 | * NTSC, so it shouldn't be a problem (I hope). |
| 238 | */ |
| 239 | |
| 240 | { |
| 241 | /* 640x480 @ 60Hz interlaced (NTSC) */ |
| 242 | "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26, |
| 243 | FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP |
| 244 | }, { |
| 245 | /* 640x240 @ 60Hz (NTSC) */ |
| 246 | /* XXX: Broken! Don't use... */ |
| 247 | "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22, |
| 248 | FB_SYNC_BROADCAST, FB_VMODE_YWRAP |
| 249 | }, { |
| 250 | /* 640x480 @ 60hz (VGA) */ |
| 251 | "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26, |
| 252 | 0, FB_VMODE_YWRAP |
| 253 | }, |
| 254 | }; |
| 255 | |
| 256 | #define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb) |
| 257 | |
| 258 | #define DEFMODE_NTSC 0 |
| 259 | #define DEFMODE_PAL 0 |
| 260 | #define DEFMODE_VGA 2 |
| 261 | |
| 262 | static int defmode = DEFMODE_NTSC; |
| 263 | static char *mode_option __initdata = NULL; |
| 264 | |
| 265 | static inline void pvr2fb_set_pal_type(unsigned int type) |
| 266 | { |
| 267 | struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par; |
| 268 | |
| 269 | fb_writel(type, par->mmio_base + 0x108); |
| 270 | } |
| 271 | |
| 272 | static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par, |
| 273 | unsigned int regno, |
| 274 | unsigned int val) |
| 275 | { |
| 276 | fb_writel(val, par->mmio_base + 0x1000 + (4 * regno)); |
| 277 | } |
| 278 | |
| 279 | static int pvr2fb_blank(int blank, struct fb_info *info) |
| 280 | { |
| 281 | do_blank = blank ? blank : -1; |
| 282 | return 0; |
| 283 | } |
| 284 | |
| 285 | static inline unsigned long get_line_length(int xres_virtual, int bpp) |
| 286 | { |
| 287 | return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3); |
| 288 | } |
| 289 | |
| 290 | static void set_color_bitfields(struct fb_var_screeninfo *var) |
| 291 | { |
| 292 | switch (var->bits_per_pixel) { |
| 293 | case 16: /* RGB 565 */ |
| 294 | pvr2fb_set_pal_type(PAL_RGB565); |
| 295 | var->red.offset = 11; var->red.length = 5; |
| 296 | var->green.offset = 5; var->green.length = 6; |
| 297 | var->blue.offset = 0; var->blue.length = 5; |
| 298 | var->transp.offset = 0; var->transp.length = 0; |
| 299 | break; |
| 300 | case 24: /* RGB 888 */ |
| 301 | var->red.offset = 16; var->red.length = 8; |
| 302 | var->green.offset = 8; var->green.length = 8; |
| 303 | var->blue.offset = 0; var->blue.length = 8; |
| 304 | var->transp.offset = 0; var->transp.length = 0; |
| 305 | break; |
| 306 | case 32: /* ARGB 8888 */ |
| 307 | pvr2fb_set_pal_type(PAL_ARGB8888); |
| 308 | var->red.offset = 16; var->red.length = 8; |
| 309 | var->green.offset = 8; var->green.length = 8; |
| 310 | var->blue.offset = 0; var->blue.length = 8; |
| 311 | var->transp.offset = 24; var->transp.length = 8; |
| 312 | break; |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, |
| 317 | unsigned int green, unsigned int blue, |
| 318 | unsigned int transp, struct fb_info *info) |
| 319 | { |
| 320 | struct pvr2fb_par *par = (struct pvr2fb_par *)info->par; |
| 321 | unsigned int tmp; |
| 322 | |
| 323 | if (regno > info->cmap.len) |
| 324 | return 1; |
| 325 | |
| 326 | /* |
| 327 | * We only support the hardware palette for 16 and 32bpp. It's also |
| 328 | * expected that the palette format has been set by the time we get |
| 329 | * here, so we don't waste time setting it again. |
| 330 | */ |
| 331 | switch (info->var.bits_per_pixel) { |
| 332 | case 16: /* RGB 565 */ |
| 333 | tmp = (red & 0xf800) | |
| 334 | ((green & 0xfc00) >> 5) | |
| 335 | ((blue & 0xf800) >> 11); |
| 336 | |
| 337 | pvr2fb_set_pal_entry(par, regno, tmp); |
| 338 | ((u16*)(info->pseudo_palette))[regno] = tmp; |
| 339 | break; |
| 340 | case 24: /* RGB 888 */ |
| 341 | red >>= 8; green >>= 8; blue >>= 8; |
| 342 | ((u32*)(info->pseudo_palette))[regno] = (red << 16) | (green << 8) | blue; |
| 343 | break; |
| 344 | case 32: /* ARGB 8888 */ |
| 345 | red >>= 8; green >>= 8; blue >>= 8; |
| 346 | tmp = (transp << 24) | (red << 16) | (green << 8) | blue; |
| 347 | |
| 348 | pvr2fb_set_pal_entry(par, regno, tmp); |
| 349 | ((u32*)(info->pseudo_palette))[regno] = tmp; |
| 350 | break; |
| 351 | default: |
| 352 | pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel); |
| 353 | return 1; |
| 354 | } |
| 355 | |
| 356 | return 0; |
| 357 | } |
| 358 | |
| 359 | static int pvr2fb_set_par(struct fb_info *info) |
| 360 | { |
| 361 | struct pvr2fb_par *par = (struct pvr2fb_par *)info->par; |
| 362 | struct fb_var_screeninfo *var = &info->var; |
| 363 | unsigned long line_length; |
| 364 | unsigned int vtotal; |
| 365 | |
| 366 | /* |
| 367 | * XXX: It's possible that a user could use a VGA box, change the cable |
| 368 | * type in hardware (i.e. switch from VGA<->composite), then change |
| 369 | * modes (i.e. switching to another VT). If that happens we should |
| 370 | * automagically change the output format to cope, but currently I |
| 371 | * don't have a VGA box to make sure this works properly. |
| 372 | */ |
| 373 | cable_type = pvr2_init_cable(); |
| 374 | if (cable_type == CT_VGA && video_output != VO_VGA) |
| 375 | video_output = VO_VGA; |
| 376 | |
| 377 | var->vmode &= FB_VMODE_MASK; |
| 378 | if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA) |
| 379 | par->is_interlaced = 1; |
| 380 | /* |
| 381 | * XXX: Need to be more creative with this (i.e. allow doublecan for |
| 382 | * PAL/NTSC output). |
| 383 | */ |
| 384 | if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA) |
| 385 | par->is_doublescan = 1; |
| 386 | |
| 387 | par->hsync_total = var->left_margin + var->xres + var->right_margin + |
| 388 | var->hsync_len; |
| 389 | par->vsync_total = var->upper_margin + var->yres + var->lower_margin + |
| 390 | var->vsync_len; |
| 391 | |
| 392 | if (var->sync & FB_SYNC_BROADCAST) { |
| 393 | vtotal = par->vsync_total; |
| 394 | if (par->is_interlaced) |
| 395 | vtotal /= 2; |
| 396 | if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) { |
| 397 | /* XXX: Check for start values here... */ |
| 398 | /* XXX: Check hardware for PAL-compatibility */ |
| 399 | par->borderstart_h = 116; |
| 400 | par->borderstart_v = 44; |
| 401 | } else { |
| 402 | /* NTSC video output */ |
| 403 | par->borderstart_h = 126; |
| 404 | par->borderstart_v = 18; |
| 405 | } |
| 406 | } else { |
| 407 | /* VGA mode */ |
| 408 | /* XXX: What else needs to be checked? */ |
| 409 | /* |
| 410 | * XXX: We have a little freedom in VGA modes, what ranges |
| 411 | * should be here (i.e. hsync/vsync totals, etc.)? |
| 412 | */ |
| 413 | par->borderstart_h = 126; |
| 414 | par->borderstart_v = 40; |
| 415 | } |
| 416 | |
| 417 | /* Calculate the remainding offsets */ |
| 418 | par->diwstart_h = par->borderstart_h + var->left_margin; |
| 419 | par->diwstart_v = par->borderstart_v + var->upper_margin; |
| 420 | par->borderstop_h = par->diwstart_h + var->xres + |
| 421 | var->right_margin; |
| 422 | par->borderstop_v = par->diwstart_v + var->yres + |
| 423 | var->lower_margin; |
| 424 | |
| 425 | if (!par->is_interlaced) |
| 426 | par->borderstop_v /= 2; |
| 427 | if (info->var.xres < 640) |
| 428 | par->is_lowres = 1; |
| 429 | |
| 430 | line_length = get_line_length(var->xres_virtual, var->bits_per_pixel); |
| 431 | par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length; |
| 432 | info->fix.line_length = line_length; |
| 433 | return 0; |
| 434 | } |
| 435 | |
| 436 | static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
| 437 | { |
| 438 | struct pvr2fb_par *par = (struct pvr2fb_par *)info->par; |
| 439 | unsigned int vtotal, hsync_total; |
| 440 | unsigned long line_length; |
| 441 | |
| 442 | if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) { |
| 443 | pr_debug("Invalid pixclock value %d\n", var->pixclock); |
| 444 | return -EINVAL; |
| 445 | } |
| 446 | |
| 447 | if (var->xres < 320) |
| 448 | var->xres = 320; |
| 449 | if (var->yres < 240) |
| 450 | var->yres = 240; |
| 451 | if (var->xres_virtual < var->xres) |
| 452 | var->xres_virtual = var->xres; |
| 453 | if (var->yres_virtual < var->yres) |
| 454 | var->yres_virtual = var->yres; |
| 455 | |
| 456 | if (var->bits_per_pixel <= 16) |
| 457 | var->bits_per_pixel = 16; |
| 458 | else if (var->bits_per_pixel <= 24) |
| 459 | var->bits_per_pixel = 24; |
| 460 | else if (var->bits_per_pixel <= 32) |
| 461 | var->bits_per_pixel = 32; |
| 462 | |
| 463 | set_color_bitfields(var); |
| 464 | |
| 465 | if (var->vmode & FB_VMODE_YWRAP) { |
| 466 | if (var->xoffset || var->yoffset < 0 || |
| 467 | var->yoffset >= var->yres_virtual) { |
| 468 | var->xoffset = var->yoffset = 0; |
| 469 | } else { |
| 470 | if (var->xoffset > var->xres_virtual - var->xres || |
| 471 | var->yoffset > var->yres_virtual - var->yres || |
| 472 | var->xoffset < 0 || var->yoffset < 0) |
| 473 | var->xoffset = var->yoffset = 0; |
| 474 | } |
| 475 | } else { |
| 476 | var->xoffset = var->yoffset = 0; |
| 477 | } |
| 478 | |
| 479 | /* |
| 480 | * XXX: Need to be more creative with this (i.e. allow doublecan for |
| 481 | * PAL/NTSC output). |
| 482 | */ |
| 483 | if (var->yres < 480 && video_output == VO_VGA) |
| 484 | var->vmode |= FB_VMODE_DOUBLE; |
| 485 | |
| 486 | if (video_output != VO_VGA) { |
| 487 | var->sync |= FB_SYNC_BROADCAST; |
| 488 | var->vmode |= FB_VMODE_INTERLACED; |
| 489 | } else { |
| 490 | var->sync &= ~FB_SYNC_BROADCAST; |
| 491 | var->vmode &= ~FB_VMODE_INTERLACED; |
| 492 | var->vmode |= pvr2_var.vmode; |
| 493 | } |
| 494 | |
| 495 | if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) { |
| 496 | var->right_margin = par->borderstop_h - |
| 497 | (par->diwstart_h + var->xres); |
| 498 | var->left_margin = par->diwstart_h - par->borderstart_h; |
| 499 | var->hsync_len = par->borderstart_h + |
| 500 | (par->hsync_total - par->borderstop_h); |
| 501 | |
| 502 | var->upper_margin = par->diwstart_v - par->borderstart_v; |
| 503 | var->lower_margin = par->borderstop_v - |
| 504 | (par->diwstart_v + var->yres); |
| 505 | var->vsync_len = par->borderstop_v + |
| 506 | (par->vsync_total - par->borderstop_v); |
| 507 | } |
| 508 | |
| 509 | hsync_total = var->left_margin + var->xres + var->right_margin + |
| 510 | var->hsync_len; |
| 511 | vtotal = var->upper_margin + var->yres + var->lower_margin + |
| 512 | var->vsync_len; |
| 513 | |
| 514 | if (var->sync & FB_SYNC_BROADCAST) { |
| 515 | if (var->vmode & FB_VMODE_INTERLACED) |
| 516 | vtotal /= 2; |
| 517 | if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) { |
| 518 | /* PAL video output */ |
| 519 | /* XXX: Should be using a range here ... ? */ |
| 520 | if (hsync_total != PAL_HTOTAL) { |
| 521 | pr_debug("invalid hsync total for PAL\n"); |
| 522 | return -EINVAL; |
| 523 | } |
| 524 | } else { |
| 525 | /* NTSC video output */ |
| 526 | if (hsync_total != NTSC_HTOTAL) { |
| 527 | pr_debug("invalid hsync total for NTSC\n"); |
| 528 | return -EINVAL; |
| 529 | } |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | /* Check memory sizes */ |
| 534 | line_length = get_line_length(var->xres_virtual, var->bits_per_pixel); |
| 535 | if (line_length * var->yres_virtual > info->fix.smem_len) |
| 536 | return -ENOMEM; |
| 537 | |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | static void pvr2_update_display(struct fb_info *info) |
| 542 | { |
| 543 | struct pvr2fb_par *par = (struct pvr2fb_par *) info->par; |
| 544 | struct fb_var_screeninfo *var = &info->var; |
| 545 | |
| 546 | /* Update the start address of the display image */ |
| 547 | fb_writel(par->disp_start, DISP_DIWADDRL); |
| 548 | fb_writel(par->disp_start + |
| 549 | get_line_length(var->xoffset+var->xres, var->bits_per_pixel), |
| 550 | DISP_DIWADDRS); |
| 551 | } |
| 552 | |
| 553 | /* |
| 554 | * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't |
| 555 | * very stable. It's probably due to the fact that a lot of the 2D video |
| 556 | * registers are still undocumented. |
| 557 | */ |
| 558 | |
| 559 | static void pvr2_init_display(struct fb_info *info) |
| 560 | { |
| 561 | struct pvr2fb_par *par = (struct pvr2fb_par *) info->par; |
| 562 | struct fb_var_screeninfo *var = &info->var; |
| 563 | unsigned int diw_height, diw_width, diw_modulo = 1; |
| 564 | unsigned int bytesperpixel = var->bits_per_pixel >> 3; |
| 565 | |
| 566 | /* hsync and vsync totals */ |
| 567 | fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE); |
| 568 | |
| 569 | /* column height, modulo, row width */ |
| 570 | /* since we're "panning" within vram, we need to offset things based |
| 571 | * on the offset from the virtual x start to our real gfx. */ |
| 572 | if (video_output != VO_VGA && par->is_interlaced) |
| 573 | diw_modulo += info->fix.line_length / 4; |
| 574 | diw_height = (par->is_interlaced ? var->yres / 2 : var->yres); |
| 575 | diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4; |
| 576 | fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width, |
| 577 | DISP_DIWSIZE); |
| 578 | |
| 579 | /* display address, long and short fields */ |
| 580 | fb_writel(par->disp_start, DISP_DIWADDRL); |
| 581 | fb_writel(par->disp_start + |
| 582 | get_line_length(var->xoffset+var->xres, var->bits_per_pixel), |
| 583 | DISP_DIWADDRS); |
| 584 | |
| 585 | /* border horizontal, border vertical, border color */ |
| 586 | fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ); |
| 587 | fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT); |
| 588 | fb_writel(0, DISP_BRDRCOLR); |
| 589 | |
| 590 | /* display window start position */ |
| 591 | fb_writel(par->diwstart_h, DISP_DIWHSTRT); |
| 592 | fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT); |
| 593 | |
| 594 | /* misc. settings */ |
| 595 | fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF); |
| 596 | |
| 597 | /* clock doubler (for VGA), scan doubler, display enable */ |
| 598 | fb_writel(((video_output == VO_VGA) << 23) | |
| 599 | (par->is_doublescan << 1) | 1, DISP_DIWMODE); |
| 600 | |
| 601 | /* bits per pixel */ |
| 602 | fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE); |
| 603 | |
| 604 | /* video enable, color sync, interlace, |
| 605 | * hsync and vsync polarity (currently unused) */ |
| 606 | fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF); |
| 607 | } |
| 608 | |
| 609 | /* Simulate blanking by making the border cover the entire screen */ |
| 610 | |
| 611 | #define BLANK_BIT (1<<3) |
| 612 | |
| 613 | static void pvr2_do_blank(void) |
| 614 | { |
| 615 | struct pvr2fb_par *par = currentpar; |
| 616 | unsigned long diwconf; |
| 617 | |
| 618 | diwconf = fb_readl(DISP_DIWCONF); |
| 619 | if (do_blank > 0) |
| 620 | fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF); |
| 621 | else |
| 622 | fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF); |
| 623 | |
| 624 | is_blanked = do_blank > 0 ? do_blank : 0; |
| 625 | } |
| 626 | |
| 627 | static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id, struct pt_regs *fp) |
| 628 | { |
| 629 | struct fb_info *info = dev_id; |
| 630 | |
| 631 | if (do_vmode_pan || do_vmode_full) |
| 632 | pvr2_update_display(info); |
| 633 | if (do_vmode_full) |
| 634 | pvr2_init_display(info); |
| 635 | if (do_vmode_pan) |
| 636 | do_vmode_pan = 0; |
| 637 | if (do_vmode_full) |
| 638 | do_vmode_full = 0; |
| 639 | if (do_blank) { |
| 640 | pvr2_do_blank(); |
| 641 | do_blank = 0; |
| 642 | } |
| 643 | return IRQ_HANDLED; |
| 644 | } |
| 645 | |
| 646 | /* |
| 647 | * Determine the cable type and initialize the cable output format. Don't do |
| 648 | * anything if the cable type has been overidden (via "cable:XX"). |
| 649 | */ |
| 650 | |
| 651 | #define PCTRA 0xff80002c |
| 652 | #define PDTRA 0xff800030 |
| 653 | #define VOUTC 0xa0702c00 |
| 654 | |
| 655 | static int pvr2_init_cable(void) |
| 656 | { |
| 657 | if (cable_type < 0) { |
| 658 | fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000, |
| 659 | PCTRA); |
| 660 | cable_type = (fb_readw(PDTRA) >> 8) & 3; |
| 661 | } |
| 662 | |
| 663 | /* Now select the output format (either composite or other) */ |
| 664 | /* XXX: Save the previous val first, as this reg is also AICA |
| 665 | related */ |
| 666 | if (cable_type == CT_COMPOSITE) |
| 667 | fb_writel(3 << 8, VOUTC); |
| 668 | else |
| 669 | fb_writel(0, VOUTC); |
| 670 | |
| 671 | return cable_type; |
| 672 | } |
| 673 | |
| 674 | #ifdef CONFIG_SH_DMA |
| 675 | static ssize_t pvr2fb_write(struct file *file, const char *buf, |
| 676 | size_t count, loff_t *ppos) |
| 677 | { |
| 678 | unsigned long dst, start, end, len; |
| 679 | unsigned int nr_pages; |
| 680 | struct page **pages; |
| 681 | int ret, i; |
| 682 | |
| 683 | nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT; |
| 684 | |
| 685 | pages = kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); |
| 686 | if (!pages) |
| 687 | return -ENOMEM; |
| 688 | |
| 689 | down_read(¤t->mm->mmap_sem); |
| 690 | ret = get_user_pages(current, current->mm, (unsigned long)buf, |
| 691 | nr_pages, WRITE, 0, pages, NULL); |
| 692 | up_read(¤t->mm->mmap_sem); |
| 693 | |
| 694 | if (ret < nr_pages) { |
| 695 | nr_pages = ret; |
| 696 | ret = -EINVAL; |
| 697 | goto out_unmap; |
| 698 | } |
| 699 | |
| 700 | dma_configure_channel(shdma, 0x12c1); |
| 701 | |
| 702 | dst = (unsigned long)fb_info->screen_base + *ppos; |
| 703 | start = (unsigned long)page_address(pages[0]); |
| 704 | end = (unsigned long)page_address(pages[nr_pages]); |
| 705 | len = nr_pages << PAGE_SHIFT; |
| 706 | |
| 707 | /* Half-assed contig check */ |
| 708 | if (start + len == end) { |
| 709 | /* As we do this in one shot, it's either all or nothing.. */ |
| 710 | if ((*ppos + len) > fb_info->fix.smem_len) { |
| 711 | ret = -ENOSPC; |
| 712 | goto out_unmap; |
| 713 | } |
| 714 | |
| 715 | dma_write(shdma, start, 0, len); |
| 716 | dma_write(pvr2dma, 0, dst, len); |
| 717 | dma_wait_for_completion(pvr2dma); |
| 718 | |
| 719 | goto out; |
| 720 | } |
| 721 | |
| 722 | /* Not contiguous, writeout per-page instead.. */ |
| 723 | for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) { |
| 724 | if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) { |
| 725 | ret = -ENOSPC; |
| 726 | goto out_unmap; |
| 727 | } |
| 728 | |
| 729 | dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0); |
| 730 | dma_write_page(pvr2dma, 0, dst); |
| 731 | dma_wait_for_completion(pvr2dma); |
| 732 | } |
| 733 | |
| 734 | out: |
| 735 | *ppos += count; |
| 736 | ret = count; |
| 737 | |
| 738 | out_unmap: |
| 739 | for (i = 0; i < nr_pages; i++) |
| 740 | page_cache_release(pages[i]); |
| 741 | |
| 742 | kfree(pages); |
| 743 | |
| 744 | return ret; |
| 745 | } |
| 746 | #endif /* CONFIG_SH_DMA */ |
| 747 | |
| 748 | /** |
| 749 | * pvr2fb_common_init |
| 750 | * |
| 751 | * Common init code for the PVR2 chips. |
| 752 | * |
| 753 | * This mostly takes care of the common aspects of the fb setup and |
| 754 | * registration. It's expected that the board-specific init code has |
| 755 | * already setup pvr2_fix with something meaningful at this point. |
| 756 | * |
| 757 | * Device info reporting is also done here, as well as picking a sane |
| 758 | * default from the modedb. For board-specific modelines, simply define |
| 759 | * a per-board modedb. |
| 760 | * |
| 761 | * Also worth noting is that the cable and video output types are likely |
| 762 | * always going to be VGA for the PCI-based PVR2 boards, but we leave this |
| 763 | * in for flexibility anyways. Who knows, maybe someone has tv-out on a |
| 764 | * PCI-based version of these things ;-) |
| 765 | */ |
| 766 | static int __init pvr2fb_common_init(void) |
| 767 | { |
| 768 | struct pvr2fb_par *par = currentpar; |
| 769 | unsigned long modememused, rev; |
| 770 | |
| 771 | fb_info->screen_base = ioremap_nocache(pvr2_fix.smem_start, |
| 772 | pvr2_fix.smem_len); |
| 773 | |
| 774 | if (!fb_info->screen_base) { |
| 775 | printk(KERN_ERR "pvr2fb: Failed to remap smem space\n"); |
| 776 | goto out_err; |
| 777 | } |
| 778 | |
| 779 | par->mmio_base = (unsigned long)ioremap_nocache(pvr2_fix.mmio_start, |
| 780 | pvr2_fix.mmio_len); |
| 781 | if (!par->mmio_base) { |
| 782 | printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n"); |
| 783 | goto out_err; |
| 784 | } |
| 785 | |
| 786 | fb_memset((unsigned long)fb_info->screen_base, 0, pvr2_fix.smem_len); |
| 787 | |
| 788 | pvr2_fix.ypanstep = nopan ? 0 : 1; |
| 789 | pvr2_fix.ywrapstep = nowrap ? 0 : 1; |
| 790 | |
| 791 | fb_info->fbops = &pvr2fb_ops; |
| 792 | fb_info->fix = pvr2_fix; |
| 793 | fb_info->par = currentpar; |
| 794 | fb_info->pseudo_palette = (void *)(fb_info->par + 1); |
| 795 | fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; |
| 796 | |
| 797 | if (video_output == VO_VGA) |
| 798 | defmode = DEFMODE_VGA; |
| 799 | |
| 800 | if (!mode_option) |
| 801 | mode_option = "640x480@60"; |
| 802 | |
| 803 | if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb, |
| 804 | NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16)) |
| 805 | fb_info->var = pvr2_var; |
| 806 | |
| 807 | fb_alloc_cmap(&fb_info->cmap, 256, 0); |
| 808 | |
| 809 | if (register_framebuffer(fb_info) < 0) |
| 810 | goto out_err; |
| 811 | |
| 812 | modememused = get_line_length(fb_info->var.xres_virtual, |
| 813 | fb_info->var.bits_per_pixel); |
| 814 | modememused *= fb_info->var.yres_virtual; |
| 815 | |
| 816 | rev = fb_readl(par->mmio_base + 0x04); |
| 817 | |
| 818 | printk("fb%d: %s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n", |
| 819 | fb_info->node, fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f, |
| 820 | modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10)); |
| 821 | printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n", |
| 822 | fb_info->node, fb_info->var.xres, fb_info->var.yres, |
| 823 | fb_info->var.bits_per_pixel, |
| 824 | get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel), |
| 825 | (char *)pvr2_get_param(cables, NULL, cable_type, 3), |
| 826 | (char *)pvr2_get_param(outputs, NULL, video_output, 3)); |
| 827 | |
| 828 | #ifdef CONFIG_SH_STORE_QUEUES |
| 829 | printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node); |
| 830 | |
| 831 | pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len, |
| 832 | fb_info->fix.id); |
| 833 | |
| 834 | printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n", |
| 835 | fb_info->node, pvr2fb_map->sq_addr); |
| 836 | #endif |
| 837 | |
| 838 | return 0; |
| 839 | |
| 840 | out_err: |
| 841 | if (fb_info->screen_base) |
| 842 | iounmap(fb_info->screen_base); |
| 843 | if (par->mmio_base) |
| 844 | iounmap((void *)par->mmio_base); |
| 845 | |
| 846 | return -ENXIO; |
| 847 | } |
| 848 | |
| 849 | #ifdef CONFIG_SH_DREAMCAST |
| 850 | static int __init pvr2fb_dc_init(void) |
| 851 | { |
| 852 | if (!mach_is_dreamcast()) |
| 853 | return -ENXIO; |
| 854 | |
| 855 | /* Make a guess at the monitor based on the attached cable */ |
| 856 | if (pvr2_init_cable() == CT_VGA) { |
| 857 | fb_info->monspecs.hfmin = 30000; |
| 858 | fb_info->monspecs.hfmax = 70000; |
| 859 | fb_info->monspecs.vfmin = 60; |
| 860 | fb_info->monspecs.vfmax = 60; |
| 861 | } else { |
| 862 | /* Not VGA, using a TV (taken from acornfb) */ |
| 863 | fb_info->monspecs.hfmin = 15469; |
| 864 | fb_info->monspecs.hfmax = 15781; |
| 865 | fb_info->monspecs.vfmin = 49; |
| 866 | fb_info->monspecs.vfmax = 51; |
| 867 | } |
| 868 | |
| 869 | /* |
| 870 | * XXX: This needs to pull default video output via BIOS or other means |
| 871 | */ |
| 872 | if (video_output < 0) { |
| 873 | if (cable_type == CT_VGA) { |
| 874 | video_output = VO_VGA; |
| 875 | } else { |
| 876 | video_output = VO_NTSC; |
| 877 | } |
| 878 | } |
| 879 | |
| 880 | /* |
| 881 | * Nothing exciting about the DC PVR2 .. only a measly 8MiB. |
| 882 | */ |
| 883 | pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */ |
| 884 | pvr2_fix.smem_len = 8 << 20; |
| 885 | |
| 886 | pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */ |
| 887 | pvr2_fix.mmio_len = 0x2000; |
| 888 | |
| 889 | if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, 0, |
| 890 | "pvr2 VBL handler", fb_info)) { |
| 891 | return -EBUSY; |
| 892 | } |
| 893 | |
| 894 | #ifdef CONFIG_SH_DMA |
| 895 | if (request_dma(pvr2dma, "pvr2") != 0) { |
| 896 | free_irq(HW_EVENT_VSYNC, 0); |
| 897 | return -EBUSY; |
| 898 | } |
| 899 | #endif |
| 900 | |
| 901 | return pvr2fb_common_init(); |
| 902 | } |
| 903 | |
| 904 | static void pvr2fb_dc_exit(void) |
| 905 | { |
| 906 | free_irq(HW_EVENT_VSYNC, 0); |
| 907 | #ifdef CONFIG_SH_DMA |
| 908 | free_dma(pvr2dma); |
| 909 | #endif |
| 910 | } |
| 911 | #endif /* CONFIG_SH_DREAMCAST */ |
| 912 | |
| 913 | #ifdef CONFIG_PCI |
| 914 | static int __devinit pvr2fb_pci_probe(struct pci_dev *pdev, |
| 915 | const struct pci_device_id *ent) |
| 916 | { |
| 917 | int ret; |
| 918 | |
| 919 | ret = pci_enable_device(pdev); |
| 920 | if (ret) { |
| 921 | printk(KERN_ERR "pvr2fb: PCI enable failed\n"); |
| 922 | return ret; |
| 923 | } |
| 924 | |
| 925 | ret = pci_request_regions(pdev, "pvr2fb"); |
| 926 | if (ret) { |
| 927 | printk(KERN_ERR "pvr2fb: PCI request regions failed\n"); |
| 928 | return ret; |
| 929 | } |
| 930 | |
| 931 | /* |
| 932 | * Slightly more exciting than the DC PVR2 .. 16MiB! |
| 933 | */ |
| 934 | pvr2_fix.smem_start = pci_resource_start(pdev, 0); |
| 935 | pvr2_fix.smem_len = pci_resource_len(pdev, 0); |
| 936 | |
| 937 | pvr2_fix.mmio_start = pci_resource_start(pdev, 1); |
| 938 | pvr2_fix.mmio_len = pci_resource_len(pdev, 1); |
| 939 | |
| 940 | fb_info->device = &pdev->dev; |
| 941 | |
| 942 | return pvr2fb_common_init(); |
| 943 | } |
| 944 | |
| 945 | static void __devexit pvr2fb_pci_remove(struct pci_dev *pdev) |
| 946 | { |
| 947 | pci_release_regions(pdev); |
| 948 | } |
| 949 | |
| 950 | static struct pci_device_id pvr2fb_pci_tbl[] __devinitdata = { |
| 951 | { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250, |
| 952 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
| 953 | { 0, }, |
| 954 | }; |
| 955 | |
| 956 | MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl); |
| 957 | |
| 958 | static struct pci_driver pvr2fb_pci_driver = { |
| 959 | .name = "pvr2fb", |
| 960 | .id_table = pvr2fb_pci_tbl, |
| 961 | .probe = pvr2fb_pci_probe, |
| 962 | .remove = __devexit_p(pvr2fb_pci_remove), |
| 963 | }; |
| 964 | |
| 965 | static int __init pvr2fb_pci_init(void) |
| 966 | { |
| 967 | return pci_register_driver(&pvr2fb_pci_driver); |
| 968 | } |
| 969 | |
| 970 | static void pvr2fb_pci_exit(void) |
| 971 | { |
| 972 | pci_unregister_driver(&pvr2fb_pci_driver); |
| 973 | } |
| 974 | #endif /* CONFIG_PCI */ |
| 975 | |
| 976 | static int __init pvr2_get_param(const struct pvr2_params *p, const char *s, |
| 977 | int val, int size) |
| 978 | { |
| 979 | int i; |
| 980 | |
| 981 | for (i = 0 ; i < size ; i++ ) { |
| 982 | if (s != NULL) { |
| 983 | if (!strnicmp(p[i].name, s, strlen(s))) |
| 984 | return p[i].val; |
| 985 | } else { |
| 986 | if (p[i].val == val) |
| 987 | return (int)p[i].name; |
| 988 | } |
| 989 | } |
| 990 | return -1; |
| 991 | } |
| 992 | |
| 993 | /* |
| 994 | * Parse command arguments. Supported arguments are: |
| 995 | * inverse Use inverse color maps |
| 996 | * cable:composite|rgb|vga Override the video cable type |
| 997 | * output:NTSC|PAL|VGA Override the video output format |
| 998 | * |
| 999 | * <xres>x<yres>[-<bpp>][@<refresh>] or, |
| 1000 | * <name>[-<bpp>][@<refresh>] Startup using this video mode |
| 1001 | */ |
| 1002 | |
| 1003 | #ifndef MODULE |
| 1004 | int __init pvr2fb_setup(char *options) |
| 1005 | { |
| 1006 | char *this_opt; |
| 1007 | char cable_arg[80]; |
| 1008 | char output_arg[80]; |
| 1009 | |
| 1010 | if (!options || !*options) |
| 1011 | return 0; |
| 1012 | |
| 1013 | while ((this_opt = strsep(&options, ","))) { |
| 1014 | if (!*this_opt) |
| 1015 | continue; |
| 1016 | if (!strcmp(this_opt, "inverse")) { |
| 1017 | fb_invert_cmaps(); |
| 1018 | } else if (!strncmp(this_opt, "cable:", 6)) { |
| 1019 | strcpy(cable_arg, this_opt + 6); |
| 1020 | } else if (!strncmp(this_opt, "output:", 7)) { |
| 1021 | strcpy(output_arg, this_opt + 7); |
| 1022 | } else if (!strncmp(this_opt, "nopan", 5)) { |
| 1023 | nopan = 1; |
| 1024 | } else if (!strncmp(this_opt, "nowrap", 6)) { |
| 1025 | nowrap = 1; |
| 1026 | } else { |
| 1027 | mode_option = this_opt; |
| 1028 | } |
| 1029 | } |
| 1030 | |
| 1031 | if (*cable_arg) |
| 1032 | cable_type = pvr2_get_param(cables, cable_arg, 0, 3); |
| 1033 | if (*output_arg) |
| 1034 | video_output = pvr2_get_param(outputs, output_arg, 0, 3); |
| 1035 | |
| 1036 | return 0; |
| 1037 | } |
| 1038 | #endif |
| 1039 | |
| 1040 | static struct pvr2_board { |
| 1041 | int (*init)(void); |
| 1042 | void (*exit)(void); |
| 1043 | char name[16]; |
| 1044 | } board_list[] = { |
| 1045 | #ifdef CONFIG_SH_DREAMCAST |
| 1046 | { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" }, |
| 1047 | #endif |
| 1048 | #ifdef CONFIG_PCI |
| 1049 | { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" }, |
| 1050 | #endif |
| 1051 | { 0, }, |
| 1052 | }; |
| 1053 | |
| 1054 | int __init pvr2fb_init(void) |
| 1055 | { |
| 1056 | int i, ret = -ENODEV; |
| 1057 | int size; |
| 1058 | |
| 1059 | #ifndef MODULE |
| 1060 | char *option = NULL; |
| 1061 | |
| 1062 | if (fb_get_options("pvr2fb", &option)) |
| 1063 | return -ENODEV; |
| 1064 | pvr2fb_setup(option); |
| 1065 | #endif |
| 1066 | size = sizeof(struct fb_info) + sizeof(struct pvr2fb_par) + 16 * sizeof(u32); |
| 1067 | |
| 1068 | fb_info = kmalloc(size, GFP_KERNEL); |
| 1069 | if (!fb_info) { |
| 1070 | printk(KERN_ERR "Failed to allocate memory for fb_info\n"); |
| 1071 | return -ENOMEM; |
| 1072 | } |
| 1073 | |
| 1074 | memset(fb_info, 0, size); |
| 1075 | |
| 1076 | currentpar = (struct pvr2fb_par *)(fb_info + 1); |
| 1077 | |
| 1078 | for (i = 0; i < ARRAY_SIZE(board_list); i++) { |
| 1079 | struct pvr2_board *pvr_board = board_list + i; |
| 1080 | |
| 1081 | if (!pvr_board->init) |
| 1082 | continue; |
| 1083 | |
| 1084 | ret = pvr_board->init(); |
| 1085 | |
| 1086 | if (ret != 0) { |
| 1087 | printk(KERN_ERR "pvr2fb: Failed init of %s device\n", |
| 1088 | pvr_board->name); |
| 1089 | kfree(fb_info); |
| 1090 | break; |
| 1091 | } |
| 1092 | } |
| 1093 | |
| 1094 | return ret; |
| 1095 | } |
| 1096 | |
| 1097 | static void __exit pvr2fb_exit(void) |
| 1098 | { |
| 1099 | int i; |
| 1100 | |
| 1101 | for (i = 0; i < ARRAY_SIZE(board_list); i++) { |
| 1102 | struct pvr2_board *pvr_board = board_list + i; |
| 1103 | |
| 1104 | if (pvr_board->exit) |
| 1105 | pvr_board->exit(); |
| 1106 | } |
| 1107 | |
| 1108 | #ifdef CONFIG_SH_STORE_QUEUES |
| 1109 | sq_unmap(pvr2fb_map); |
| 1110 | #endif |
| 1111 | |
| 1112 | unregister_framebuffer(fb_info); |
| 1113 | kfree(fb_info); |
| 1114 | } |
| 1115 | |
| 1116 | module_init(pvr2fb_init); |
| 1117 | module_exit(pvr2fb_exit); |
| 1118 | |
| 1119 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>"); |
| 1120 | MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards"); |
| 1121 | MODULE_LICENSE("GPL"); |
| 1122 | |