Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1 | /* |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 2 | * Intel I/OAT DMA Linux driver |
Maciej Sosnowski | 211a22c | 2009-02-26 11:05:43 +0100 | [diff] [blame] | 3 | * Copyright(c) 2004 - 2009 Intel Corporation. |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 17 | * |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 18 | * The full GNU General Public License is included in this distribution in |
| 19 | * the file called "COPYING". |
| 20 | * |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * This driver supports an Intel I/OAT DMA engine, which does asynchronous |
| 25 | * copy operations. |
| 26 | */ |
| 27 | |
| 28 | #include <linux/init.h> |
| 29 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 31 | #include <linux/pci.h> |
| 32 | #include <linux/interrupt.h> |
| 33 | #include <linux/dmaengine.h> |
| 34 | #include <linux/delay.h> |
David S. Miller | 6b00c92 | 2006-05-23 17:37:58 -0700 | [diff] [blame] | 35 | #include <linux/dma-mapping.h> |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 36 | #include <linux/workqueue.h> |
Paul Gortmaker | 70c7160 | 2011-05-22 16:47:17 -0400 | [diff] [blame] | 37 | #include <linux/prefetch.h> |
Venki Pallipadi | 3ad0b02 | 2008-10-22 16:34:52 -0700 | [diff] [blame] | 38 | #include <linux/i7300_idle.h> |
Dan Williams | 584ec22 | 2009-07-28 14:32:12 -0700 | [diff] [blame] | 39 | #include "dma.h" |
| 40 | #include "registers.h" |
| 41 | #include "hw.h" |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 42 | |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 43 | #include "../dmaengine.h" |
| 44 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 45 | int ioat_pending_level = 4; |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 46 | module_param(ioat_pending_level, int, 0644); |
| 47 | MODULE_PARM_DESC(ioat_pending_level, |
| 48 | "high-water mark for pushing ioat descriptors (default: 4)"); |
| 49 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 50 | /* internal functions */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 51 | static void ioat1_cleanup(struct ioat_dma_chan *ioat); |
| 52 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 53 | |
| 54 | /** |
| 55 | * ioat_dma_do_interrupt - handler used for single vector interrupt mode |
| 56 | * @irq: interrupt id |
| 57 | * @data: interrupt data |
| 58 | */ |
| 59 | static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) |
| 60 | { |
| 61 | struct ioatdma_device *instance = data; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 62 | struct ioat_chan_common *chan; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 63 | unsigned long attnstatus; |
| 64 | int bit; |
| 65 | u8 intrctrl; |
| 66 | |
| 67 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); |
| 68 | |
| 69 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) |
| 70 | return IRQ_NONE; |
| 71 | |
| 72 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { |
| 73 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); |
| 74 | return IRQ_NONE; |
| 75 | } |
| 76 | |
| 77 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 78 | for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 79 | chan = ioat_chan_by_index(instance, bit); |
| 80 | tasklet_schedule(&chan->cleanup_task); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 81 | } |
| 82 | |
| 83 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); |
| 84 | return IRQ_HANDLED; |
| 85 | } |
| 86 | |
| 87 | /** |
| 88 | * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode |
| 89 | * @irq: interrupt id |
| 90 | * @data: interrupt data |
| 91 | */ |
| 92 | static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) |
| 93 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 94 | struct ioat_chan_common *chan = data; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 95 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 96 | tasklet_schedule(&chan->cleanup_task); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 97 | |
| 98 | return IRQ_HANDLED; |
| 99 | } |
| 100 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 101 | /* common channel initialization */ |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 102 | void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 103 | { |
| 104 | struct dma_device *dma = &device->common; |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 105 | struct dma_chan *c = &chan->common; |
| 106 | unsigned long data = (unsigned long) c; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 107 | |
| 108 | chan->device = device; |
| 109 | chan->reg_base = device->reg_base + (0x80 * (idx + 1)); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 110 | spin_lock_init(&chan->cleanup_lock); |
| 111 | chan->common.device = dma; |
Russell King - ARM Linux | 8ac6954 | 2012-03-06 22:36:27 +0000 | [diff] [blame] | 112 | dma_cookie_init(&chan->common); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 113 | list_add_tail(&chan->common.device_node, &dma->channels); |
| 114 | device->idx[idx] = chan; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 115 | init_timer(&chan->timer); |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 116 | chan->timer.function = device->timer_fn; |
| 117 | chan->timer.data = data; |
| 118 | tasklet_init(&chan->cleanup_task, device->cleanup_fn, data); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 119 | tasklet_disable(&chan->cleanup_task); |
| 120 | } |
| 121 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 122 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 123 | * ioat1_dma_enumerate_channels - find and initialize the device's channels |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 124 | * @device: the device to be enumerated |
| 125 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 126 | static int ioat1_enumerate_channels(struct ioatdma_device *device) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 127 | { |
| 128 | u8 xfercap_scale; |
| 129 | u32 xfercap; |
| 130 | int i; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 131 | struct ioat_dma_chan *ioat; |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 132 | struct device *dev = &device->pdev->dev; |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 133 | struct dma_device *dma = &device->common; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 134 | |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 135 | INIT_LIST_HEAD(&dma->channels); |
| 136 | dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); |
Dan Williams | bb32078 | 2009-09-08 12:01:14 -0700 | [diff] [blame] | 137 | dma->chancnt &= 0x1f; /* bits [4:0] valid */ |
| 138 | if (dma->chancnt > ARRAY_SIZE(device->idx)) { |
| 139 | dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", |
| 140 | dma->chancnt, ARRAY_SIZE(device->idx)); |
| 141 | dma->chancnt = ARRAY_SIZE(device->idx); |
| 142 | } |
Chris Leech | e382881 | 2007-03-08 09:57:35 -0800 | [diff] [blame] | 143 | xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); |
Dan Williams | bb32078 | 2009-09-08 12:01:14 -0700 | [diff] [blame] | 144 | xfercap_scale &= 0x1f; /* bits [4:0] valid */ |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 145 | xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 146 | dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 147 | |
Venki Pallipadi | f371be6 | 2008-10-23 15:39:06 -0700 | [diff] [blame] | 148 | #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 149 | if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) |
| 150 | dma->chancnt--; |
Andy Henroid | 27471fd | 2008-10-09 11:45:22 -0700 | [diff] [blame] | 151 | #endif |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 152 | for (i = 0; i < dma->chancnt; i++) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 153 | ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 154 | if (!ioat) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 155 | break; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 156 | |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 157 | ioat_init_channel(device, &ioat->base, i); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 158 | ioat->xfercap = xfercap; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 159 | spin_lock_init(&ioat->desc_lock); |
| 160 | INIT_LIST_HEAD(&ioat->free_desc); |
| 161 | INIT_LIST_HEAD(&ioat->used_desc); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 162 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 163 | dma->chancnt = i; |
| 164 | return i; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 165 | } |
| 166 | |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 167 | /** |
| 168 | * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended |
| 169 | * descriptors to hw |
| 170 | * @chan: DMA channel handle |
| 171 | */ |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 172 | static inline void |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 173 | __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat) |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 174 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 175 | void __iomem *reg_base = ioat->base.reg_base; |
| 176 | |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 177 | dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n", |
| 178 | __func__, ioat->pending); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 179 | ioat->pending = 0; |
| 180 | writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) |
| 184 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 185 | struct ioat_dma_chan *ioat = to_ioat_chan(chan); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 186 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 187 | if (ioat->pending > 0) { |
| 188 | spin_lock_bh(&ioat->desc_lock); |
| 189 | __ioat1_dma_memcpy_issue_pending(ioat); |
| 190 | spin_unlock_bh(&ioat->desc_lock); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 191 | } |
| 192 | } |
| 193 | |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 194 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 195 | * ioat1_reset_channel - restart a channel |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 196 | * @ioat: IOAT DMA channel handle |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 197 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 198 | static void ioat1_reset_channel(struct ioat_dma_chan *ioat) |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 199 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 200 | struct ioat_chan_common *chan = &ioat->base; |
| 201 | void __iomem *reg_base = chan->reg_base; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 202 | u32 chansts, chanerr; |
| 203 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 204 | dev_warn(to_dev(chan), "reset\n"); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 205 | chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 206 | chansts = *chan->completion & IOAT_CHANSTS_STATUS; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 207 | if (chanerr) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 208 | dev_err(to_dev(chan), |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 209 | "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 210 | chan_num(chan), chansts, chanerr); |
| 211 | writel(chanerr, reg_base + IOAT_CHANERR_OFFSET); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | /* |
| 215 | * whack it upside the head with a reset |
| 216 | * and wait for things to settle out. |
| 217 | * force the pending count to a really big negative |
| 218 | * to make sure no one forces an issue_pending |
| 219 | * while we're waiting. |
| 220 | */ |
| 221 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 222 | ioat->pending = INT_MIN; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 223 | writeb(IOAT_CHANCMD_RESET, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 224 | reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 225 | set_bit(IOAT_RESET_PENDING, &chan->state); |
| 226 | mod_timer(&chan->timer, jiffies + RESET_DELAY); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 227 | } |
| 228 | |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 229 | static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 230 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 231 | struct dma_chan *c = tx->chan; |
| 232 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 233 | struct ioat_desc_sw *desc = tx_to_ioat_desc(tx); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 234 | struct ioat_chan_common *chan = &ioat->base; |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 235 | struct ioat_desc_sw *first; |
| 236 | struct ioat_desc_sw *chain_tail; |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 237 | dma_cookie_t cookie; |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 238 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 239 | spin_lock_bh(&ioat->desc_lock); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 240 | /* cookie incr and addition to used_list must be atomic */ |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 241 | cookie = dma_cookie_assign(tx); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 242 | dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 243 | |
| 244 | /* write address into NextDescriptor field of last desc in chain */ |
Dan Williams | ea25968 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 245 | first = to_ioat_desc(desc->tx_list.next); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 246 | chain_tail = to_ioat_desc(ioat->used_desc.prev); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 247 | /* make descriptor updates globally visible before chaining */ |
| 248 | wmb(); |
| 249 | chain_tail->hw->next = first->txd.phys; |
Dan Williams | ea25968 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 250 | list_splice_tail_init(&desc->tx_list, &ioat->used_desc); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 251 | dump_desc_dbg(ioat, chain_tail); |
| 252 | dump_desc_dbg(ioat, first); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 253 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 254 | if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state)) |
| 255 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 256 | |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 257 | ioat->active += desc->hw->tx_cnt; |
Dan Williams | ad643f5 | 2009-09-08 12:01:38 -0700 | [diff] [blame] | 258 | ioat->pending += desc->hw->tx_cnt; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 259 | if (ioat->pending >= ioat_pending_level) |
| 260 | __ioat1_dma_memcpy_issue_pending(ioat); |
| 261 | spin_unlock_bh(&ioat->desc_lock); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 262 | |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 263 | return cookie; |
| 264 | } |
| 265 | |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 266 | /** |
| 267 | * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 268 | * @ioat: the channel supplying the memory pool for the descriptors |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 269 | * @flags: allocation flags |
| 270 | */ |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 271 | static struct ioat_desc_sw * |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 272 | ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 273 | { |
| 274 | struct ioat_dma_descriptor *desc; |
| 275 | struct ioat_desc_sw *desc_sw; |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 276 | struct ioatdma_device *ioatdma_device; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 277 | dma_addr_t phys; |
| 278 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 279 | ioatdma_device = ioat->base.device; |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 280 | desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 281 | if (unlikely(!desc)) |
| 282 | return NULL; |
| 283 | |
| 284 | desc_sw = kzalloc(sizeof(*desc_sw), flags); |
| 285 | if (unlikely(!desc_sw)) { |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 286 | pci_pool_free(ioatdma_device->dma_pool, desc, phys); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 287 | return NULL; |
| 288 | } |
| 289 | |
| 290 | memset(desc, 0, sizeof(*desc)); |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 291 | |
Dan Williams | ea25968 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 292 | INIT_LIST_HEAD(&desc_sw->tx_list); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 293 | dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common); |
| 294 | desc_sw->txd.tx_submit = ioat1_tx_submit; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 295 | desc_sw->hw = desc; |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 296 | desc_sw->txd.phys = phys; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 297 | set_desc_id(desc_sw, -1); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 298 | |
| 299 | return desc_sw; |
| 300 | } |
| 301 | |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 302 | static int ioat_initial_desc_count = 256; |
| 303 | module_param(ioat_initial_desc_count, int, 0644); |
| 304 | MODULE_PARM_DESC(ioat_initial_desc_count, |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 305 | "ioat1: initial descriptors per channel (default: 256)"); |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 306 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 307 | * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 308 | * @chan: the channel to be filled out |
| 309 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 310 | static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 311 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 312 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
| 313 | struct ioat_chan_common *chan = &ioat->base; |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 314 | struct ioat_desc_sw *desc; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 315 | u32 chanerr; |
| 316 | int i; |
| 317 | LIST_HEAD(tmp_list); |
| 318 | |
Shannon Nelson | e422397 | 2007-08-24 23:02:53 -0700 | [diff] [blame] | 319 | /* have we already been set up? */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 320 | if (!list_empty(&ioat->free_desc)) |
| 321 | return ioat->desccount; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 322 | |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 323 | /* Setup register to interrupt and write completion status on error */ |
Dan Williams | f6ab95b | 2009-09-08 12:01:21 -0700 | [diff] [blame] | 324 | writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 325 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 326 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 327 | if (chanerr) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 328 | dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr); |
| 329 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 330 | } |
| 331 | |
| 332 | /* Allocate descriptors */ |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 333 | for (i = 0; i < ioat_initial_desc_count; i++) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 334 | desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 335 | if (!desc) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 336 | dev_err(to_dev(chan), "Only %d initial descriptors\n", i); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 337 | break; |
| 338 | } |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 339 | set_desc_id(desc, i); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 340 | list_add_tail(&desc->node, &tmp_list); |
| 341 | } |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 342 | spin_lock_bh(&ioat->desc_lock); |
| 343 | ioat->desccount = i; |
| 344 | list_splice(&tmp_list, &ioat->free_desc); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 345 | spin_unlock_bh(&ioat->desc_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 346 | |
| 347 | /* allocate a completion writeback area */ |
| 348 | /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 349 | chan->completion = pci_pool_alloc(chan->device->completion_pool, |
| 350 | GFP_KERNEL, &chan->completion_dma); |
| 351 | memset(chan->completion, 0, sizeof(*chan->completion)); |
| 352 | writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 353 | chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 354 | writel(((u64) chan->completion_dma) >> 32, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 355 | chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 356 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 357 | tasklet_enable(&chan->cleanup_task); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 358 | ioat1_dma_start_null_desc(ioat); /* give chain to dma device */ |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 359 | dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n", |
| 360 | __func__, ioat->desccount); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 361 | return ioat->desccount; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 362 | } |
| 363 | |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 364 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 365 | * ioat1_dma_free_chan_resources - release all the descriptors |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 366 | * @chan: the channel to be cleaned |
| 367 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 368 | static void ioat1_dma_free_chan_resources(struct dma_chan *c) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 369 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 370 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
| 371 | struct ioat_chan_common *chan = &ioat->base; |
| 372 | struct ioatdma_device *ioatdma_device = chan->device; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 373 | struct ioat_desc_sw *desc, *_desc; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 374 | int in_use_descs = 0; |
| 375 | |
Maciej Sosnowski | c3d4f44 | 2008-11-07 01:45:52 +0000 | [diff] [blame] | 376 | /* Before freeing channel resources first check |
| 377 | * if they have been previously allocated for this channel. |
| 378 | */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 379 | if (ioat->desccount == 0) |
Maciej Sosnowski | c3d4f44 | 2008-11-07 01:45:52 +0000 | [diff] [blame] | 380 | return; |
| 381 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 382 | tasklet_disable(&chan->cleanup_task); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 383 | del_timer_sync(&chan->timer); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 384 | ioat1_cleanup(ioat); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 385 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 386 | /* Delay 100ms after reset to allow internal DMA logic to quiesce |
| 387 | * before removing DMA descriptor resources. |
| 388 | */ |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 389 | writeb(IOAT_CHANCMD_RESET, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 390 | chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 391 | mdelay(100); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 392 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 393 | spin_lock_bh(&ioat->desc_lock); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 394 | list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { |
| 395 | dev_dbg(to_dev(chan), "%s: freeing %d from used list\n", |
| 396 | __func__, desc_id(desc)); |
| 397 | dump_desc_dbg(ioat, desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 398 | in_use_descs++; |
| 399 | list_del(&desc->node); |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 400 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 401 | desc->txd.phys); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 402 | kfree(desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 403 | } |
| 404 | list_for_each_entry_safe(desc, _desc, |
| 405 | &ioat->free_desc, node) { |
| 406 | list_del(&desc->node); |
| 407 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, |
| 408 | desc->txd.phys); |
| 409 | kfree(desc); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 410 | } |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 411 | spin_unlock_bh(&ioat->desc_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 412 | |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 413 | pci_pool_free(ioatdma_device->completion_pool, |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 414 | chan->completion, |
| 415 | chan->completion_dma); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 416 | |
| 417 | /* one is ok since we left it on there on purpose */ |
| 418 | if (in_use_descs > 1) |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 419 | dev_err(to_dev(chan), "Freeing %d in use descriptors!\n", |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 420 | in_use_descs - 1); |
| 421 | |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 422 | chan->last_completion = 0; |
| 423 | chan->completion_dma = 0; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 424 | ioat->pending = 0; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 425 | ioat->desccount = 0; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 426 | } |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 427 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 428 | /** |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 429 | * ioat1_dma_get_next_descriptor - return the next available descriptor |
| 430 | * @ioat: IOAT DMA channel handle |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 431 | * |
| 432 | * Gets the next descriptor from the chain, and must be called with the |
| 433 | * channel's desc_lock held. Allocates more descriptors if the channel |
| 434 | * has run out. |
| 435 | */ |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 436 | static struct ioat_desc_sw * |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 437 | ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 438 | { |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 439 | struct ioat_desc_sw *new; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 440 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 441 | if (!list_empty(&ioat->free_desc)) { |
| 442 | new = to_ioat_desc(ioat->free_desc.next); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 443 | list_del(&new->node); |
| 444 | } else { |
| 445 | /* try to get another desc */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 446 | new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 447 | if (!new) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 448 | dev_err(to_dev(&ioat->base), "alloc failed\n"); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 449 | return NULL; |
| 450 | } |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 451 | } |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 452 | dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n", |
| 453 | __func__, desc_id(new)); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 454 | prefetch(new->hw); |
| 455 | return new; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 456 | } |
| 457 | |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 458 | static struct dma_async_tx_descriptor * |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 459 | ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 460 | dma_addr_t dma_src, size_t len, unsigned long flags) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 461 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 462 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 463 | struct ioat_desc_sw *desc; |
| 464 | size_t copy; |
| 465 | LIST_HEAD(chain); |
| 466 | dma_addr_t src = dma_src; |
| 467 | dma_addr_t dest = dma_dest; |
| 468 | size_t total_len = len; |
| 469 | struct ioat_dma_descriptor *hw = NULL; |
| 470 | int tx_cnt = 0; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 471 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 472 | spin_lock_bh(&ioat->desc_lock); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 473 | desc = ioat1_dma_get_next_descriptor(ioat); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 474 | do { |
| 475 | if (!desc) |
| 476 | break; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 477 | |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 478 | tx_cnt++; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 479 | copy = min_t(size_t, len, ioat->xfercap); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 480 | |
| 481 | hw = desc->hw; |
| 482 | hw->size = copy; |
| 483 | hw->ctl = 0; |
| 484 | hw->src_addr = src; |
| 485 | hw->dst_addr = dest; |
| 486 | |
| 487 | list_add_tail(&desc->node, &chain); |
| 488 | |
| 489 | len -= copy; |
| 490 | dest += copy; |
| 491 | src += copy; |
| 492 | if (len) { |
| 493 | struct ioat_desc_sw *next; |
| 494 | |
| 495 | async_tx_ack(&desc->txd); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 496 | next = ioat1_dma_get_next_descriptor(ioat); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 497 | hw->next = next ? next->txd.phys : 0; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 498 | dump_desc_dbg(ioat, desc); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 499 | desc = next; |
| 500 | } else |
| 501 | hw->next = 0; |
| 502 | } while (len); |
| 503 | |
| 504 | if (!desc) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 505 | struct ioat_chan_common *chan = &ioat->base; |
| 506 | |
| 507 | dev_err(to_dev(chan), |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 508 | "chan%d - get_next_desc failed\n", chan_num(chan)); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 509 | list_splice(&chain, &ioat->free_desc); |
| 510 | spin_unlock_bh(&ioat->desc_lock); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 511 | return NULL; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 512 | } |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 513 | spin_unlock_bh(&ioat->desc_lock); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 514 | |
| 515 | desc->txd.flags = flags; |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 516 | desc->len = total_len; |
Dan Williams | ea25968 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 517 | list_splice(&chain, &desc->tx_list); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 518 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
| 519 | hw->ctl_f.compl_write = 1; |
Dan Williams | ad643f5 | 2009-09-08 12:01:38 -0700 | [diff] [blame] | 520 | hw->tx_cnt = tx_cnt; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 521 | dump_desc_dbg(ioat, desc); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 522 | |
| 523 | return &desc->txd; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 524 | } |
| 525 | |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 526 | static void ioat1_cleanup_event(unsigned long data) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 527 | { |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 528 | struct ioat_dma_chan *ioat = to_ioat_chan((void *) data); |
Dan Williams | f6ab95b | 2009-09-08 12:01:21 -0700 | [diff] [blame] | 529 | |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 530 | ioat1_cleanup(ioat); |
| 531 | writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 532 | } |
| 533 | |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 534 | dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 535 | { |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 536 | dma_addr_t phys_complete; |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 537 | u64 completion; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 538 | |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 539 | completion = *chan->completion; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 540 | phys_complete = ioat_chansts_to_addr(completion); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 541 | |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 542 | dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, |
| 543 | (unsigned long long) phys_complete); |
| 544 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 545 | if (is_ioat_halted(completion)) { |
| 546 | u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 547 | dev_err(to_dev(chan), "Channel halted, chanerr = %x\n", |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 548 | chanerr); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 549 | |
| 550 | /* TODO do something to salvage the situation */ |
| 551 | } |
| 552 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 553 | return phys_complete; |
| 554 | } |
| 555 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 556 | bool ioat_cleanup_preamble(struct ioat_chan_common *chan, |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 557 | dma_addr_t *phys_complete) |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 558 | { |
| 559 | *phys_complete = ioat_get_current_completion(chan); |
| 560 | if (*phys_complete == chan->last_completion) |
| 561 | return false; |
| 562 | clear_bit(IOAT_COMPLETION_ACK, &chan->state); |
| 563 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 564 | |
| 565 | return true; |
| 566 | } |
| 567 | |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 568 | static void __cleanup(struct ioat_dma_chan *ioat, dma_addr_t phys_complete) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 569 | { |
| 570 | struct ioat_chan_common *chan = &ioat->base; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 571 | struct list_head *_desc, *n; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 572 | struct dma_async_tx_descriptor *tx; |
| 573 | |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 574 | dev_dbg(to_dev(chan), "%s: phys_complete: %llx\n", |
| 575 | __func__, (unsigned long long) phys_complete); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 576 | list_for_each_safe(_desc, n, &ioat->used_desc) { |
| 577 | struct ioat_desc_sw *desc; |
| 578 | |
| 579 | prefetch(n); |
| 580 | desc = list_entry(_desc, typeof(*desc), node); |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 581 | tx = &desc->txd; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 582 | /* |
| 583 | * Incoming DMA requests may use multiple descriptors, |
| 584 | * due to exceeding xfercap, perhaps. If so, only the |
| 585 | * last one will have a cookie, and require unmapping. |
| 586 | */ |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 587 | dump_desc_dbg(ioat, desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 588 | if (tx->cookie) { |
Russell King - ARM Linux | f7fbce0 | 2012-03-06 22:35:07 +0000 | [diff] [blame] | 589 | dma_cookie_complete(tx); |
Dan Williams | d38a8c6 | 2013-10-18 19:35:23 +0200 | [diff] [blame] | 590 | dma_descriptor_unmap(tx); |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 591 | ioat->active -= desc->hw->tx_cnt; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 592 | if (tx->callback) { |
| 593 | tx->callback(tx->callback_param); |
| 594 | tx->callback = NULL; |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 595 | } |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 596 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 597 | |
| 598 | if (tx->phys != phys_complete) { |
| 599 | /* |
| 600 | * a completed entry, but not the last, so clean |
| 601 | * up if the client is done with the descriptor |
| 602 | */ |
| 603 | if (async_tx_test_ack(tx)) |
| 604 | list_move_tail(&desc->node, &ioat->free_desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 605 | } else { |
| 606 | /* |
| 607 | * last used desc. Do not remove, so we can |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 608 | * append from it. |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 609 | */ |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 610 | |
| 611 | /* if nothing else is pending, cancel the |
| 612 | * completion timeout |
| 613 | */ |
| 614 | if (n == &ioat->used_desc) { |
| 615 | dev_dbg(to_dev(chan), |
| 616 | "%s cancel completion timeout\n", |
| 617 | __func__); |
| 618 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); |
| 619 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 620 | |
| 621 | /* TODO check status bits? */ |
| 622 | break; |
| 623 | } |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 624 | } |
| 625 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 626 | chan->last_completion = phys_complete; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 627 | } |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 628 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 629 | /** |
| 630 | * ioat1_cleanup - cleanup up finished descriptors |
| 631 | * @chan: ioat channel to be cleaned up |
| 632 | * |
| 633 | * To prevent lock contention we defer cleanup when the locks are |
| 634 | * contended with a terminal timeout that forces cleanup and catches |
| 635 | * completion notification errors. |
| 636 | */ |
| 637 | static void ioat1_cleanup(struct ioat_dma_chan *ioat) |
| 638 | { |
| 639 | struct ioat_chan_common *chan = &ioat->base; |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 640 | dma_addr_t phys_complete; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 641 | |
| 642 | prefetch(chan->completion); |
| 643 | |
| 644 | if (!spin_trylock_bh(&chan->cleanup_lock)) |
| 645 | return; |
| 646 | |
| 647 | if (!ioat_cleanup_preamble(chan, &phys_complete)) { |
| 648 | spin_unlock_bh(&chan->cleanup_lock); |
| 649 | return; |
| 650 | } |
| 651 | |
| 652 | if (!spin_trylock_bh(&ioat->desc_lock)) { |
| 653 | spin_unlock_bh(&chan->cleanup_lock); |
| 654 | return; |
| 655 | } |
| 656 | |
| 657 | __cleanup(ioat, phys_complete); |
| 658 | |
| 659 | spin_unlock_bh(&ioat->desc_lock); |
| 660 | spin_unlock_bh(&chan->cleanup_lock); |
| 661 | } |
| 662 | |
| 663 | static void ioat1_timer_event(unsigned long data) |
| 664 | { |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 665 | struct ioat_dma_chan *ioat = to_ioat_chan((void *) data); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 666 | struct ioat_chan_common *chan = &ioat->base; |
| 667 | |
| 668 | dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state); |
| 669 | |
| 670 | spin_lock_bh(&chan->cleanup_lock); |
| 671 | if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) { |
| 672 | struct ioat_desc_sw *desc; |
| 673 | |
| 674 | spin_lock_bh(&ioat->desc_lock); |
| 675 | |
| 676 | /* restart active descriptors */ |
| 677 | desc = to_ioat_desc(ioat->used_desc.prev); |
| 678 | ioat_set_chainaddr(ioat, desc->txd.phys); |
| 679 | ioat_start(chan); |
| 680 | |
| 681 | ioat->pending = 0; |
| 682 | set_bit(IOAT_COMPLETION_PENDING, &chan->state); |
| 683 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 684 | spin_unlock_bh(&ioat->desc_lock); |
| 685 | } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) { |
Dan Williams | 2750293 | 2012-03-23 13:36:42 -0700 | [diff] [blame] | 686 | dma_addr_t phys_complete; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 687 | |
| 688 | spin_lock_bh(&ioat->desc_lock); |
| 689 | /* if we haven't made progress and we have already |
| 690 | * acknowledged a pending completion once, then be more |
| 691 | * forceful with a restart |
| 692 | */ |
| 693 | if (ioat_cleanup_preamble(chan, &phys_complete)) |
| 694 | __cleanup(ioat, phys_complete); |
| 695 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) |
| 696 | ioat1_reset_channel(ioat); |
| 697 | else { |
| 698 | u64 status = ioat_chansts(chan); |
| 699 | |
| 700 | /* manually update the last completion address */ |
| 701 | if (ioat_chansts_to_addr(status) != 0) |
| 702 | *chan->completion = status; |
| 703 | |
| 704 | set_bit(IOAT_COMPLETION_ACK, &chan->state); |
| 705 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 706 | } |
| 707 | spin_unlock_bh(&ioat->desc_lock); |
| 708 | } |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 709 | spin_unlock_bh(&chan->cleanup_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 710 | } |
| 711 | |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 712 | enum dma_status |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 713 | ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie, |
| 714 | struct dma_tx_state *txstate) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 715 | { |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 716 | struct ioat_chan_common *chan = to_chan_common(c); |
| 717 | struct ioatdma_device *device = chan->device; |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 718 | enum dma_status ret; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 719 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 720 | ret = dma_cookie_status(c, cookie, txstate); |
Vinod Koul | 2f16f80 | 2013-10-16 20:48:52 +0530 | [diff] [blame] | 721 | if (ret == DMA_COMPLETE) |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 722 | return ret; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 723 | |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 724 | device->cleanup_fn((unsigned long) c); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 725 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 726 | return dma_cookie_status(c, cookie, txstate); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 727 | } |
| 728 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 729 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 730 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 731 | struct ioat_chan_common *chan = &ioat->base; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 732 | struct ioat_desc_sw *desc; |
Dan Williams | c7984f4 | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 733 | struct ioat_dma_descriptor *hw; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 734 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 735 | spin_lock_bh(&ioat->desc_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 736 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 737 | desc = ioat1_dma_get_next_descriptor(ioat); |
Maciej Sosnowski | 7f1b358 | 2008-07-22 17:30:57 -0700 | [diff] [blame] | 738 | |
| 739 | if (!desc) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 740 | dev_err(to_dev(chan), |
Maciej Sosnowski | 7f1b358 | 2008-07-22 17:30:57 -0700 | [diff] [blame] | 741 | "Unable to start null desc - get next desc failed\n"); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 742 | spin_unlock_bh(&ioat->desc_lock); |
Maciej Sosnowski | 7f1b358 | 2008-07-22 17:30:57 -0700 | [diff] [blame] | 743 | return; |
| 744 | } |
| 745 | |
Dan Williams | c7984f4 | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 746 | hw = desc->hw; |
| 747 | hw->ctl = 0; |
| 748 | hw->ctl_f.null = 1; |
| 749 | hw->ctl_f.int_en = 1; |
| 750 | hw->ctl_f.compl_write = 1; |
Maciej Sosnowski | 7f1b358 | 2008-07-22 17:30:57 -0700 | [diff] [blame] | 751 | /* set size to non-zero value (channel returns error when size is 0) */ |
Dan Williams | c7984f4 | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 752 | hw->size = NULL_DESC_BUFFER_SIZE; |
| 753 | hw->src_addr = 0; |
| 754 | hw->dst_addr = 0; |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 755 | async_tx_ack(&desc->txd); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 756 | hw->next = 0; |
| 757 | list_add_tail(&desc->node, &ioat->used_desc); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 758 | dump_desc_dbg(ioat, desc); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 759 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 760 | ioat_set_chainaddr(ioat, desc->txd.phys); |
| 761 | ioat_start(chan); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 762 | spin_unlock_bh(&ioat->desc_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 763 | } |
| 764 | |
| 765 | /* |
| 766 | * Perform a IOAT transaction to verify the HW works. |
| 767 | */ |
| 768 | #define IOAT_TEST_SIZE 2000 |
| 769 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 770 | static void ioat_dma_test_callback(void *dma_async_param) |
Shannon Nelson | 9521843 | 2007-10-18 03:07:15 -0700 | [diff] [blame] | 771 | { |
Dan Williams | b9bdcbb | 2009-01-06 11:38:22 -0700 | [diff] [blame] | 772 | struct completion *cmp = dma_async_param; |
| 773 | |
| 774 | complete(cmp); |
Shannon Nelson | 9521843 | 2007-10-18 03:07:15 -0700 | [diff] [blame] | 775 | } |
| 776 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 777 | /** |
| 778 | * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. |
| 779 | * @device: device to be tested |
| 780 | */ |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 781 | int ioat_dma_self_test(struct ioatdma_device *device) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 782 | { |
| 783 | int i; |
| 784 | u8 *src; |
| 785 | u8 *dest; |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 786 | struct dma_device *dma = &device->common; |
| 787 | struct device *dev = &device->pdev->dev; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 788 | struct dma_chan *dma_chan; |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 789 | struct dma_async_tx_descriptor *tx; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 790 | dma_addr_t dma_dest, dma_src; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 791 | dma_cookie_t cookie; |
| 792 | int err = 0; |
Dan Williams | b9bdcbb | 2009-01-06 11:38:22 -0700 | [diff] [blame] | 793 | struct completion cmp; |
Dan Williams | 0c33e1c | 2009-03-02 13:31:35 -0700 | [diff] [blame] | 794 | unsigned long tmo; |
Maciej Sosnowski | 4f005db | 2009-04-23 12:31:51 +0200 | [diff] [blame] | 795 | unsigned long flags; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 796 | |
Christoph Lameter | e94b176 | 2006-12-06 20:33:17 -0800 | [diff] [blame] | 797 | src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 798 | if (!src) |
| 799 | return -ENOMEM; |
Christoph Lameter | e94b176 | 2006-12-06 20:33:17 -0800 | [diff] [blame] | 800 | dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 801 | if (!dest) { |
| 802 | kfree(src); |
| 803 | return -ENOMEM; |
| 804 | } |
| 805 | |
| 806 | /* Fill in src buffer */ |
| 807 | for (i = 0; i < IOAT_TEST_SIZE; i++) |
| 808 | src[i] = (u8)i; |
| 809 | |
| 810 | /* Start copy, using first DMA channel */ |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 811 | dma_chan = container_of(dma->channels.next, struct dma_chan, |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 812 | device_node); |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 813 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { |
| 814 | dev_err(dev, "selftest cannot allocate chan resource\n"); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 815 | err = -ENODEV; |
| 816 | goto out; |
| 817 | } |
| 818 | |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 819 | dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); |
Jiang Liu | 3532e56 | 2014-01-02 12:58:52 -0800 | [diff] [blame] | 820 | if (dma_mapping_error(dev, dma_src)) { |
| 821 | dev_err(dev, "mapping src buffer failed\n"); |
| 822 | goto free_resources; |
| 823 | } |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 824 | dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); |
Jiang Liu | 3532e56 | 2014-01-02 12:58:52 -0800 | [diff] [blame] | 825 | if (dma_mapping_error(dev, dma_dest)) { |
| 826 | dev_err(dev, "mapping dest buffer failed\n"); |
| 827 | goto unmap_src; |
| 828 | } |
Bartlomiej Zolnierkiewicz | 0776ae7 | 2013-10-18 19:35:33 +0200 | [diff] [blame] | 829 | flags = DMA_PREP_INTERRUPT; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 830 | tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src, |
Maciej Sosnowski | 4f005db | 2009-04-23 12:31:51 +0200 | [diff] [blame] | 831 | IOAT_TEST_SIZE, flags); |
Shannon Nelson | 5149fd0 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 832 | if (!tx) { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 833 | dev_err(dev, "Self-test prep failed, disabling\n"); |
Shannon Nelson | 5149fd0 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 834 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 522d974 | 2012-11-05 10:00:13 +0000 | [diff] [blame] | 835 | goto unmap_dma; |
Shannon Nelson | 5149fd0 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 836 | } |
| 837 | |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 838 | async_tx_ack(tx); |
Dan Williams | b9bdcbb | 2009-01-06 11:38:22 -0700 | [diff] [blame] | 839 | init_completion(&cmp); |
Shannon Nelson | 9521843 | 2007-10-18 03:07:15 -0700 | [diff] [blame] | 840 | tx->callback = ioat_dma_test_callback; |
Dan Williams | b9bdcbb | 2009-01-06 11:38:22 -0700 | [diff] [blame] | 841 | tx->callback_param = &cmp; |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 842 | cookie = tx->tx_submit(tx); |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 843 | if (cookie < 0) { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 844 | dev_err(dev, "Self-test setup failed, disabling\n"); |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 845 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 522d974 | 2012-11-05 10:00:13 +0000 | [diff] [blame] | 846 | goto unmap_dma; |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 847 | } |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 848 | dma->device_issue_pending(dma_chan); |
Dan Williams | 532d3b1 | 2008-12-03 17:16:55 -0700 | [diff] [blame] | 849 | |
Dan Williams | 0c33e1c | 2009-03-02 13:31:35 -0700 | [diff] [blame] | 850 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 851 | |
Dan Williams | 0c33e1c | 2009-03-02 13:31:35 -0700 | [diff] [blame] | 852 | if (tmo == 0 || |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 853 | dma->device_tx_status(dma_chan, cookie, NULL) |
Vinod Koul | 2f16f80 | 2013-10-16 20:48:52 +0530 | [diff] [blame] | 854 | != DMA_COMPLETE) { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 855 | dev_err(dev, "Self-test copy timed out, disabling\n"); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 856 | err = -ENODEV; |
Bartlomiej Zolnierkiewicz | 522d974 | 2012-11-05 10:00:13 +0000 | [diff] [blame] | 857 | goto unmap_dma; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 858 | } |
| 859 | if (memcmp(src, dest, IOAT_TEST_SIZE)) { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 860 | dev_err(dev, "Self-test copy failed compare, disabling\n"); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 861 | err = -ENODEV; |
| 862 | goto free_resources; |
| 863 | } |
| 864 | |
Bartlomiej Zolnierkiewicz | 522d974 | 2012-11-05 10:00:13 +0000 | [diff] [blame] | 865 | unmap_dma: |
Bartlomiej Zolnierkiewicz | 522d974 | 2012-11-05 10:00:13 +0000 | [diff] [blame] | 866 | dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); |
Jiang Liu | 3532e56 | 2014-01-02 12:58:52 -0800 | [diff] [blame] | 867 | unmap_src: |
| 868 | dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 869 | free_resources: |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 870 | dma->device_free_chan_resources(dma_chan); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 871 | out: |
| 872 | kfree(src); |
| 873 | kfree(dest); |
| 874 | return err; |
| 875 | } |
| 876 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 877 | static char ioat_interrupt_style[32] = "msix"; |
| 878 | module_param_string(ioat_interrupt_style, ioat_interrupt_style, |
| 879 | sizeof(ioat_interrupt_style), 0644); |
| 880 | MODULE_PARM_DESC(ioat_interrupt_style, |
Dan Williams | 4c5d961 | 2013-11-13 16:29:52 -0800 | [diff] [blame] | 881 | "set ioat interrupt style: msix (default), msi, intx"); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 882 | |
| 883 | /** |
| 884 | * ioat_dma_setup_interrupts - setup interrupt handler |
| 885 | * @device: ioat device |
| 886 | */ |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame] | 887 | int ioat_dma_setup_interrupts(struct ioatdma_device *device) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 888 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 889 | struct ioat_chan_common *chan; |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 890 | struct pci_dev *pdev = device->pdev; |
| 891 | struct device *dev = &pdev->dev; |
| 892 | struct msix_entry *msix; |
| 893 | int i, j, msixcnt; |
| 894 | int err = -EINVAL; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 895 | u8 intrctrl = 0; |
| 896 | |
| 897 | if (!strcmp(ioat_interrupt_style, "msix")) |
| 898 | goto msix; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 899 | if (!strcmp(ioat_interrupt_style, "msi")) |
| 900 | goto msi; |
| 901 | if (!strcmp(ioat_interrupt_style, "intx")) |
| 902 | goto intx; |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 903 | dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); |
Shannon Nelson | 5149fd0 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 904 | goto err_no_irq; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 905 | |
| 906 | msix: |
| 907 | /* The number of MSI-X vectors should equal the number of channels */ |
| 908 | msixcnt = device->common.chancnt; |
| 909 | for (i = 0; i < msixcnt; i++) |
| 910 | device->msix_entries[i].entry = i; |
| 911 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 912 | err = pci_enable_msix(pdev, device->msix_entries, msixcnt); |
Dan Williams | 4c5d961 | 2013-11-13 16:29:52 -0800 | [diff] [blame] | 913 | if (err) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 914 | goto msi; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 915 | |
| 916 | for (i = 0; i < msixcnt; i++) { |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 917 | msix = &device->msix_entries[i]; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 918 | chan = ioat_chan_by_index(device, i); |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 919 | err = devm_request_irq(dev, msix->vector, |
| 920 | ioat_dma_do_interrupt_msix, 0, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 921 | "ioat-msix", chan); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 922 | if (err) { |
| 923 | for (j = 0; j < i; j++) { |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 924 | msix = &device->msix_entries[j]; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 925 | chan = ioat_chan_by_index(device, j); |
| 926 | devm_free_irq(dev, msix->vector, chan); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 927 | } |
Dan Williams | 4c5d961 | 2013-11-13 16:29:52 -0800 | [diff] [blame] | 928 | goto msi; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 929 | } |
| 930 | } |
| 931 | intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame] | 932 | device->irq_mode = IOAT_MSIX; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 933 | goto done; |
| 934 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 935 | msi: |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 936 | err = pci_enable_msi(pdev); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 937 | if (err) |
| 938 | goto intx; |
| 939 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 940 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, |
| 941 | "ioat-msi", device); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 942 | if (err) { |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 943 | pci_disable_msi(pdev); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 944 | goto intx; |
| 945 | } |
Dan Williams | 779e561 | 2013-11-13 16:30:43 -0800 | [diff] [blame] | 946 | device->irq_mode = IOAT_MSI; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 947 | goto done; |
| 948 | |
| 949 | intx: |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 950 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, |
| 951 | IRQF_SHARED, "ioat-intx", device); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 952 | if (err) |
| 953 | goto err_no_irq; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 954 | |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame] | 955 | device->irq_mode = IOAT_INTX; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 956 | done: |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 957 | if (device->intr_quirk) |
| 958 | device->intr_quirk(device); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 959 | intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; |
| 960 | writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET); |
| 961 | return 0; |
| 962 | |
| 963 | err_no_irq: |
| 964 | /* Disable all interrupt generation */ |
| 965 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame] | 966 | device->irq_mode = IOAT_NOIRQ; |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 967 | dev_err(dev, "no usable interrupts\n"); |
| 968 | return err; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 969 | } |
Dave Jiang | 8a52b9f | 2013-03-26 15:42:47 -0700 | [diff] [blame] | 970 | EXPORT_SYMBOL(ioat_dma_setup_interrupts); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 971 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 972 | static void ioat_disable_interrupts(struct ioatdma_device *device) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 973 | { |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 974 | /* Disable all interrupt generation */ |
| 975 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 976 | } |
| 977 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 978 | int ioat_probe(struct ioatdma_device *device) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 979 | { |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 980 | int err = -ENODEV; |
| 981 | struct dma_device *dma = &device->common; |
| 982 | struct pci_dev *pdev = device->pdev; |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 983 | struct device *dev = &pdev->dev; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 984 | |
| 985 | /* DMA coherent memory pool for DMA descriptor allocations */ |
| 986 | device->dma_pool = pci_pool_create("dma_desc_pool", pdev, |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 987 | sizeof(struct ioat_dma_descriptor), |
| 988 | 64, 0); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 989 | if (!device->dma_pool) { |
| 990 | err = -ENOMEM; |
| 991 | goto err_dma_pool; |
| 992 | } |
| 993 | |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 994 | device->completion_pool = pci_pool_create("completion_pool", pdev, |
| 995 | sizeof(u64), SMP_CACHE_BYTES, |
| 996 | SMP_CACHE_BYTES); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 997 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 998 | if (!device->completion_pool) { |
| 999 | err = -ENOMEM; |
| 1000 | goto err_completion_pool; |
| 1001 | } |
| 1002 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1003 | device->enumerate_channels(device); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1004 | |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1005 | dma_cap_set(DMA_MEMCPY, dma->cap_mask); |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1006 | dma->dev = &pdev->dev; |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 1007 | |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 1008 | if (!dma->chancnt) { |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 1009 | dev_err(dev, "channel enumeration error\n"); |
Maciej Sosnowski | 8b794b1 | 2009-02-26 11:04:54 +0100 | [diff] [blame] | 1010 | goto err_setup_interrupts; |
| 1011 | } |
| 1012 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1013 | err = ioat_dma_setup_interrupts(device); |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1014 | if (err) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1015 | goto err_setup_interrupts; |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1016 | |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1017 | err = device->self_test(device); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1018 | if (err) |
| 1019 | goto err_self_test; |
| 1020 | |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1021 | return 0; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1022 | |
| 1023 | err_self_test: |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1024 | ioat_disable_interrupts(device); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1025 | err_setup_interrupts: |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1026 | pci_pool_destroy(device->completion_pool); |
| 1027 | err_completion_pool: |
| 1028 | pci_pool_destroy(device->dma_pool); |
| 1029 | err_dma_pool: |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1030 | return err; |
| 1031 | } |
| 1032 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 1033 | int ioat_register(struct ioatdma_device *device) |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1034 | { |
| 1035 | int err = dma_async_device_register(&device->common); |
| 1036 | |
| 1037 | if (err) { |
| 1038 | ioat_disable_interrupts(device); |
| 1039 | pci_pool_destroy(device->completion_pool); |
| 1040 | pci_pool_destroy(device->dma_pool); |
| 1041 | } |
| 1042 | |
| 1043 | return err; |
| 1044 | } |
| 1045 | |
| 1046 | /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */ |
| 1047 | static void ioat1_intr_quirk(struct ioatdma_device *device) |
| 1048 | { |
| 1049 | struct pci_dev *pdev = device->pdev; |
| 1050 | u32 dmactrl; |
| 1051 | |
| 1052 | pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl); |
| 1053 | if (pdev->msi_enabled) |
| 1054 | dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; |
| 1055 | else |
| 1056 | dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN; |
| 1057 | pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); |
| 1058 | } |
| 1059 | |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 1060 | static ssize_t ring_size_show(struct dma_chan *c, char *page) |
| 1061 | { |
| 1062 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
| 1063 | |
| 1064 | return sprintf(page, "%d\n", ioat->desccount); |
| 1065 | } |
| 1066 | static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size); |
| 1067 | |
| 1068 | static ssize_t ring_active_show(struct dma_chan *c, char *page) |
| 1069 | { |
| 1070 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
| 1071 | |
| 1072 | return sprintf(page, "%d\n", ioat->active); |
| 1073 | } |
| 1074 | static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active); |
| 1075 | |
| 1076 | static ssize_t cap_show(struct dma_chan *c, char *page) |
| 1077 | { |
| 1078 | struct dma_device *dma = c->device; |
| 1079 | |
Bartlomiej Zolnierkiewicz | 48a9db4 | 2013-07-03 15:05:06 -0700 | [diff] [blame] | 1080 | return sprintf(page, "copy%s%s%s%s%s\n", |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 1081 | dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "", |
| 1082 | dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "", |
| 1083 | dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "", |
| 1084 | dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "", |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 1085 | dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : ""); |
| 1086 | |
| 1087 | } |
| 1088 | struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap); |
| 1089 | |
| 1090 | static ssize_t version_show(struct dma_chan *c, char *page) |
| 1091 | { |
| 1092 | struct dma_device *dma = c->device; |
| 1093 | struct ioatdma_device *device = to_ioatdma_device(dma); |
| 1094 | |
| 1095 | return sprintf(page, "%d.%d\n", |
| 1096 | device->version >> 4, device->version & 0xf); |
| 1097 | } |
| 1098 | struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version); |
| 1099 | |
| 1100 | static struct attribute *ioat1_attrs[] = { |
| 1101 | &ring_size_attr.attr, |
| 1102 | &ring_active_attr.attr, |
| 1103 | &ioat_cap_attr.attr, |
| 1104 | &ioat_version_attr.attr, |
| 1105 | NULL, |
| 1106 | }; |
| 1107 | |
| 1108 | static ssize_t |
| 1109 | ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page) |
| 1110 | { |
| 1111 | struct ioat_sysfs_entry *entry; |
| 1112 | struct ioat_chan_common *chan; |
| 1113 | |
| 1114 | entry = container_of(attr, struct ioat_sysfs_entry, attr); |
| 1115 | chan = container_of(kobj, struct ioat_chan_common, kobj); |
| 1116 | |
| 1117 | if (!entry->show) |
| 1118 | return -EIO; |
| 1119 | return entry->show(&chan->common, page); |
| 1120 | } |
| 1121 | |
Emese Revfy | 52cf25d | 2010-01-19 02:58:23 +0100 | [diff] [blame] | 1122 | const struct sysfs_ops ioat_sysfs_ops = { |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 1123 | .show = ioat_attr_show, |
| 1124 | }; |
| 1125 | |
| 1126 | static struct kobj_type ioat1_ktype = { |
| 1127 | .sysfs_ops = &ioat_sysfs_ops, |
| 1128 | .default_attrs = ioat1_attrs, |
| 1129 | }; |
| 1130 | |
| 1131 | void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type) |
| 1132 | { |
| 1133 | struct dma_device *dma = &device->common; |
| 1134 | struct dma_chan *c; |
| 1135 | |
| 1136 | list_for_each_entry(c, &dma->channels, device_node) { |
| 1137 | struct ioat_chan_common *chan = to_chan_common(c); |
| 1138 | struct kobject *parent = &c->dev->device.kobj; |
| 1139 | int err; |
| 1140 | |
| 1141 | err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata"); |
| 1142 | if (err) { |
| 1143 | dev_warn(to_dev(chan), |
| 1144 | "sysfs init error (%d), continuing...\n", err); |
| 1145 | kobject_put(&chan->kobj); |
| 1146 | set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state); |
| 1147 | } |
| 1148 | } |
| 1149 | } |
| 1150 | |
| 1151 | void ioat_kobject_del(struct ioatdma_device *device) |
| 1152 | { |
| 1153 | struct dma_device *dma = &device->common; |
| 1154 | struct dma_chan *c; |
| 1155 | |
| 1156 | list_for_each_entry(c, &dma->channels, device_node) { |
| 1157 | struct ioat_chan_common *chan = to_chan_common(c); |
| 1158 | |
| 1159 | if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) { |
| 1160 | kobject_del(&chan->kobj); |
| 1161 | kobject_put(&chan->kobj); |
| 1162 | } |
| 1163 | } |
| 1164 | } |
| 1165 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 1166 | int ioat1_dma_probe(struct ioatdma_device *device, int dca) |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1167 | { |
| 1168 | struct pci_dev *pdev = device->pdev; |
| 1169 | struct dma_device *dma; |
| 1170 | int err; |
| 1171 | |
| 1172 | device->intr_quirk = ioat1_intr_quirk; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1173 | device->enumerate_channels = ioat1_enumerate_channels; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 1174 | device->self_test = ioat_dma_self_test; |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 1175 | device->timer_fn = ioat1_timer_event; |
| 1176 | device->cleanup_fn = ioat1_cleanup_event; |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1177 | dma = &device->common; |
| 1178 | dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; |
| 1179 | dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1180 | dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources; |
| 1181 | dma->device_free_chan_resources = ioat1_dma_free_chan_resources; |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1182 | dma->device_tx_status = ioat_dma_tx_status; |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1183 | |
| 1184 | err = ioat_probe(device); |
| 1185 | if (err) |
| 1186 | return err; |
| 1187 | ioat_set_tcp_copy_break(4096); |
| 1188 | err = ioat_register(device); |
| 1189 | if (err) |
| 1190 | return err; |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 1191 | ioat_kobject_add(device, &ioat1_ktype); |
| 1192 | |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1193 | if (dca) |
| 1194 | device->dca = ioat_dca_init(pdev, device->reg_base); |
| 1195 | |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1196 | return err; |
| 1197 | } |
| 1198 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 1199 | void ioat_dma_remove(struct ioatdma_device *device) |
Dan Aloni | 428ed60 | 2007-03-08 09:57:36 -0800 | [diff] [blame] | 1200 | { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 1201 | struct dma_device *dma = &device->common; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1202 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1203 | ioat_disable_interrupts(device); |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1204 | |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 1205 | ioat_kobject_del(device); |
| 1206 | |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 1207 | dma_async_device_unregister(dma); |
Shannon Nelson | dfe2299 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 1208 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1209 | pci_pool_destroy(device->dma_pool); |
| 1210 | pci_pool_destroy(device->completion_pool); |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1211 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 1212 | INIT_LIST_HEAD(&dma->channels); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1213 | } |