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Chris Leech0bbd5f42006-05-23 17:35:34 -07001/*
Shannon Nelson43d6e362007-10-16 01:27:39 -07002 * Intel I/OAT DMA Linux driver
Maciej Sosnowski211a22c2009-02-26 11:05:43 +01003 * Copyright(c) 2004 - 2009 Intel Corporation.
Chris Leech0bbd5f42006-05-23 17:35:34 -07004 *
5 * This program is free software; you can redistribute it and/or modify it
Shannon Nelson43d6e362007-10-16 01:27:39 -07006 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
Chris Leech0bbd5f42006-05-23 17:35:34 -07008 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
Shannon Nelson43d6e362007-10-16 01:27:39 -070015 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
Chris Leech0bbd5f42006-05-23 17:35:34 -070017 *
Shannon Nelson43d6e362007-10-16 01:27:39 -070018 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
Chris Leech0bbd5f42006-05-23 17:35:34 -070021 */
22
23/*
24 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
25 * copy operations.
26 */
27
28#include <linux/init.h>
29#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Chris Leech0bbd5f42006-05-23 17:35:34 -070031#include <linux/pci.h>
32#include <linux/interrupt.h>
33#include <linux/dmaengine.h>
34#include <linux/delay.h>
David S. Miller6b00c922006-05-23 17:37:58 -070035#include <linux/dma-mapping.h>
Maciej Sosnowski09177e82008-07-22 10:07:33 -070036#include <linux/workqueue.h>
Paul Gortmaker70c71602011-05-22 16:47:17 -040037#include <linux/prefetch.h>
Venki Pallipadi3ad0b022008-10-22 16:34:52 -070038#include <linux/i7300_idle.h>
Dan Williams584ec222009-07-28 14:32:12 -070039#include "dma.h"
40#include "registers.h"
41#include "hw.h"
Chris Leech0bbd5f42006-05-23 17:35:34 -070042
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000043#include "../dmaengine.h"
44
Dan Williams5cbafa62009-08-26 13:01:44 -070045int ioat_pending_level = 4;
Shannon Nelson7bb67c12007-11-14 16:59:51 -080046module_param(ioat_pending_level, int, 0644);
47MODULE_PARM_DESC(ioat_pending_level,
48 "high-water mark for pushing ioat descriptors (default: 4)");
49
Chris Leech0bbd5f42006-05-23 17:35:34 -070050/* internal functions */
Dan Williams5cbafa62009-08-26 13:01:44 -070051static void ioat1_cleanup(struct ioat_dma_chan *ioat);
52static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
Shannon Nelson3e037452007-10-16 01:27:40 -070053
54/**
55 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
56 * @irq: interrupt id
57 * @data: interrupt data
58 */
59static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
60{
61 struct ioatdma_device *instance = data;
Dan Williamsdcbc8532009-07-28 14:44:50 -070062 struct ioat_chan_common *chan;
Shannon Nelson3e037452007-10-16 01:27:40 -070063 unsigned long attnstatus;
64 int bit;
65 u8 intrctrl;
66
67 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
68
69 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
70 return IRQ_NONE;
71
72 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
73 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
74 return IRQ_NONE;
75 }
76
77 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
Akinobu Mita984b3f52010-03-05 13:41:37 -080078 for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) {
Dan Williamsdcbc8532009-07-28 14:44:50 -070079 chan = ioat_chan_by_index(instance, bit);
80 tasklet_schedule(&chan->cleanup_task);
Shannon Nelson3e037452007-10-16 01:27:40 -070081 }
82
83 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
84 return IRQ_HANDLED;
85}
86
87/**
88 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
89 * @irq: interrupt id
90 * @data: interrupt data
91 */
92static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
93{
Dan Williamsdcbc8532009-07-28 14:44:50 -070094 struct ioat_chan_common *chan = data;
Shannon Nelson3e037452007-10-16 01:27:40 -070095
Dan Williamsdcbc8532009-07-28 14:44:50 -070096 tasklet_schedule(&chan->cleanup_task);
Shannon Nelson3e037452007-10-16 01:27:40 -070097
98 return IRQ_HANDLED;
99}
100
Dan Williams5cbafa62009-08-26 13:01:44 -0700101/* common channel initialization */
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700102void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx)
Dan Williams5cbafa62009-08-26 13:01:44 -0700103{
104 struct dma_device *dma = &device->common;
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700105 struct dma_chan *c = &chan->common;
106 unsigned long data = (unsigned long) c;
Dan Williams5cbafa62009-08-26 13:01:44 -0700107
108 chan->device = device;
109 chan->reg_base = device->reg_base + (0x80 * (idx + 1));
Dan Williams5cbafa62009-08-26 13:01:44 -0700110 spin_lock_init(&chan->cleanup_lock);
111 chan->common.device = dma;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +0000112 dma_cookie_init(&chan->common);
Dan Williams5cbafa62009-08-26 13:01:44 -0700113 list_add_tail(&chan->common.device_node, &dma->channels);
114 device->idx[idx] = chan;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700115 init_timer(&chan->timer);
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700116 chan->timer.function = device->timer_fn;
117 chan->timer.data = data;
118 tasklet_init(&chan->cleanup_task, device->cleanup_fn, data);
Dan Williams5cbafa62009-08-26 13:01:44 -0700119 tasklet_disable(&chan->cleanup_task);
120}
121
Shannon Nelson3e037452007-10-16 01:27:40 -0700122/**
Dan Williams5cbafa62009-08-26 13:01:44 -0700123 * ioat1_dma_enumerate_channels - find and initialize the device's channels
Shannon Nelson3e037452007-10-16 01:27:40 -0700124 * @device: the device to be enumerated
125 */
Dan Williams5cbafa62009-08-26 13:01:44 -0700126static int ioat1_enumerate_channels(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700127{
128 u8 xfercap_scale;
129 u32 xfercap;
130 int i;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700131 struct ioat_dma_chan *ioat;
Dan Williamse6c0b692009-09-08 17:29:44 -0700132 struct device *dev = &device->pdev->dev;
Dan Williamsf2427e22009-07-28 14:42:38 -0700133 struct dma_device *dma = &device->common;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700134
Dan Williamsf2427e22009-07-28 14:42:38 -0700135 INIT_LIST_HEAD(&dma->channels);
136 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
Dan Williamsbb320782009-09-08 12:01:14 -0700137 dma->chancnt &= 0x1f; /* bits [4:0] valid */
138 if (dma->chancnt > ARRAY_SIZE(device->idx)) {
139 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
140 dma->chancnt, ARRAY_SIZE(device->idx));
141 dma->chancnt = ARRAY_SIZE(device->idx);
142 }
Chris Leeche3828812007-03-08 09:57:35 -0800143 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
Dan Williamsbb320782009-09-08 12:01:14 -0700144 xfercap_scale &= 0x1f; /* bits [4:0] valid */
Chris Leech0bbd5f42006-05-23 17:35:34 -0700145 xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
Dan Williams6df91832009-09-08 12:00:55 -0700146 dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700147
Venki Pallipadif371be62008-10-23 15:39:06 -0700148#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
Dan Williamsf2427e22009-07-28 14:42:38 -0700149 if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
150 dma->chancnt--;
Andy Henroid27471fd2008-10-09 11:45:22 -0700151#endif
Dan Williamsf2427e22009-07-28 14:42:38 -0700152 for (i = 0; i < dma->chancnt; i++) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700153 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
Dan Williams5cbafa62009-08-26 13:01:44 -0700154 if (!ioat)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700155 break;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700156
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700157 ioat_init_channel(device, &ioat->base, i);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700158 ioat->xfercap = xfercap;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700159 spin_lock_init(&ioat->desc_lock);
160 INIT_LIST_HEAD(&ioat->free_desc);
161 INIT_LIST_HEAD(&ioat->used_desc);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700162 }
Dan Williams5cbafa62009-08-26 13:01:44 -0700163 dma->chancnt = i;
164 return i;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700165}
166
Shannon Nelson711924b2007-12-17 16:20:08 -0800167/**
168 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
169 * descriptors to hw
170 * @chan: DMA channel handle
171 */
Dan Williamsbc3c7022009-07-28 14:33:42 -0700172static inline void
Dan Williamsdcbc8532009-07-28 14:44:50 -0700173__ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
Shannon Nelson711924b2007-12-17 16:20:08 -0800174{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700175 void __iomem *reg_base = ioat->base.reg_base;
176
Dan Williams6df91832009-09-08 12:00:55 -0700177 dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
178 __func__, ioat->pending);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700179 ioat->pending = 0;
180 writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
Shannon Nelson711924b2007-12-17 16:20:08 -0800181}
182
183static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
184{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700185 struct ioat_dma_chan *ioat = to_ioat_chan(chan);
Shannon Nelson711924b2007-12-17 16:20:08 -0800186
Dan Williamsdcbc8532009-07-28 14:44:50 -0700187 if (ioat->pending > 0) {
188 spin_lock_bh(&ioat->desc_lock);
189 __ioat1_dma_memcpy_issue_pending(ioat);
190 spin_unlock_bh(&ioat->desc_lock);
Shannon Nelson711924b2007-12-17 16:20:08 -0800191 }
192}
193
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700194/**
Dan Williams5cbafa62009-08-26 13:01:44 -0700195 * ioat1_reset_channel - restart a channel
Dan Williamsdcbc8532009-07-28 14:44:50 -0700196 * @ioat: IOAT DMA channel handle
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700197 */
Dan Williams5cbafa62009-08-26 13:01:44 -0700198static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700199{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700200 struct ioat_chan_common *chan = &ioat->base;
201 void __iomem *reg_base = chan->reg_base;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700202 u32 chansts, chanerr;
203
Dan Williams09c8a5b2009-09-08 12:01:49 -0700204 dev_warn(to_dev(chan), "reset\n");
Dan Williamsdcbc8532009-07-28 14:44:50 -0700205 chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700206 chansts = *chan->completion & IOAT_CHANSTS_STATUS;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700207 if (chanerr) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700208 dev_err(to_dev(chan),
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700209 "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
Dan Williamsdcbc8532009-07-28 14:44:50 -0700210 chan_num(chan), chansts, chanerr);
211 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700212 }
213
214 /*
215 * whack it upside the head with a reset
216 * and wait for things to settle out.
217 * force the pending count to a really big negative
218 * to make sure no one forces an issue_pending
219 * while we're waiting.
220 */
221
Dan Williamsdcbc8532009-07-28 14:44:50 -0700222 ioat->pending = INT_MIN;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700223 writeb(IOAT_CHANCMD_RESET,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700224 reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
Dan Williams09c8a5b2009-09-08 12:01:49 -0700225 set_bit(IOAT_RESET_PENDING, &chan->state);
226 mod_timer(&chan->timer, jiffies + RESET_DELAY);
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700227}
228
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800229static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700230{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700231 struct dma_chan *c = tx->chan;
232 struct ioat_dma_chan *ioat = to_ioat_chan(c);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700233 struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700234 struct ioat_chan_common *chan = &ioat->base;
Dan Williamsa0587bc2009-07-28 14:44:04 -0700235 struct ioat_desc_sw *first;
236 struct ioat_desc_sw *chain_tail;
Dan Williams7405f742007-01-02 11:10:43 -0700237 dma_cookie_t cookie;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700238
Dan Williamsdcbc8532009-07-28 14:44:50 -0700239 spin_lock_bh(&ioat->desc_lock);
Dan Williams7405f742007-01-02 11:10:43 -0700240 /* cookie incr and addition to used_list must be atomic */
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000241 cookie = dma_cookie_assign(tx);
Dan Williams6df91832009-09-08 12:00:55 -0700242 dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
Dan Williams7405f742007-01-02 11:10:43 -0700243
244 /* write address into NextDescriptor field of last desc in chain */
Dan Williamsea259682009-09-08 17:53:02 -0700245 first = to_ioat_desc(desc->tx_list.next);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700246 chain_tail = to_ioat_desc(ioat->used_desc.prev);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700247 /* make descriptor updates globally visible before chaining */
248 wmb();
249 chain_tail->hw->next = first->txd.phys;
Dan Williamsea259682009-09-08 17:53:02 -0700250 list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
Dan Williams6df91832009-09-08 12:00:55 -0700251 dump_desc_dbg(ioat, chain_tail);
252 dump_desc_dbg(ioat, first);
Dan Williams7405f742007-01-02 11:10:43 -0700253
Dan Williams09c8a5b2009-09-08 12:01:49 -0700254 if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
255 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
256
Dan Williams5669e312009-09-08 17:42:56 -0700257 ioat->active += desc->hw->tx_cnt;
Dan Williamsad643f52009-09-08 12:01:38 -0700258 ioat->pending += desc->hw->tx_cnt;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700259 if (ioat->pending >= ioat_pending_level)
260 __ioat1_dma_memcpy_issue_pending(ioat);
261 spin_unlock_bh(&ioat->desc_lock);
Dan Williams7405f742007-01-02 11:10:43 -0700262
Dan Williams7405f742007-01-02 11:10:43 -0700263 return cookie;
264}
265
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800266/**
267 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
Dan Williamsdcbc8532009-07-28 14:44:50 -0700268 * @ioat: the channel supplying the memory pool for the descriptors
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800269 * @flags: allocation flags
270 */
Dan Williamsbc3c7022009-07-28 14:33:42 -0700271static struct ioat_desc_sw *
Dan Williamsdcbc8532009-07-28 14:44:50 -0700272ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700273{
274 struct ioat_dma_descriptor *desc;
275 struct ioat_desc_sw *desc_sw;
Shannon Nelson8ab89562007-10-16 01:27:39 -0700276 struct ioatdma_device *ioatdma_device;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700277 dma_addr_t phys;
278
Dan Williamsdcbc8532009-07-28 14:44:50 -0700279 ioatdma_device = ioat->base.device;
Shannon Nelson8ab89562007-10-16 01:27:39 -0700280 desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700281 if (unlikely(!desc))
282 return NULL;
283
284 desc_sw = kzalloc(sizeof(*desc_sw), flags);
285 if (unlikely(!desc_sw)) {
Shannon Nelson8ab89562007-10-16 01:27:39 -0700286 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700287 return NULL;
288 }
289
290 memset(desc, 0, sizeof(*desc));
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800291
Dan Williamsea259682009-09-08 17:53:02 -0700292 INIT_LIST_HEAD(&desc_sw->tx_list);
Dan Williams5cbafa62009-08-26 13:01:44 -0700293 dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
294 desc_sw->txd.tx_submit = ioat1_tx_submit;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700295 desc_sw->hw = desc;
Dan Williamsbc3c7022009-07-28 14:33:42 -0700296 desc_sw->txd.phys = phys;
Dan Williams6df91832009-09-08 12:00:55 -0700297 set_desc_id(desc_sw, -1);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700298
299 return desc_sw;
300}
301
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800302static int ioat_initial_desc_count = 256;
303module_param(ioat_initial_desc_count, int, 0644);
304MODULE_PARM_DESC(ioat_initial_desc_count,
Dan Williams5cbafa62009-08-26 13:01:44 -0700305 "ioat1: initial descriptors per channel (default: 256)");
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800306/**
Dan Williams5cbafa62009-08-26 13:01:44 -0700307 * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800308 * @chan: the channel to be filled out
309 */
Dan Williams5cbafa62009-08-26 13:01:44 -0700310static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700311{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700312 struct ioat_dma_chan *ioat = to_ioat_chan(c);
313 struct ioat_chan_common *chan = &ioat->base;
Shannon Nelson711924b2007-12-17 16:20:08 -0800314 struct ioat_desc_sw *desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700315 u32 chanerr;
316 int i;
317 LIST_HEAD(tmp_list);
318
Shannon Nelsone4223972007-08-24 23:02:53 -0700319 /* have we already been set up? */
Dan Williamsdcbc8532009-07-28 14:44:50 -0700320 if (!list_empty(&ioat->free_desc))
321 return ioat->desccount;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700322
Shannon Nelson43d6e362007-10-16 01:27:39 -0700323 /* Setup register to interrupt and write completion status on error */
Dan Williamsf6ab95b2009-09-08 12:01:21 -0700324 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700325
Dan Williamsdcbc8532009-07-28 14:44:50 -0700326 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700327 if (chanerr) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700328 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
329 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700330 }
331
332 /* Allocate descriptors */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800333 for (i = 0; i < ioat_initial_desc_count; i++) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700334 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700335 if (!desc) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700336 dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700337 break;
338 }
Dan Williams6df91832009-09-08 12:00:55 -0700339 set_desc_id(desc, i);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700340 list_add_tail(&desc->node, &tmp_list);
341 }
Dan Williamsdcbc8532009-07-28 14:44:50 -0700342 spin_lock_bh(&ioat->desc_lock);
343 ioat->desccount = i;
344 list_splice(&tmp_list, &ioat->free_desc);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700345 spin_unlock_bh(&ioat->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700346
347 /* allocate a completion writeback area */
348 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700349 chan->completion = pci_pool_alloc(chan->device->completion_pool,
350 GFP_KERNEL, &chan->completion_dma);
351 memset(chan->completion, 0, sizeof(*chan->completion));
352 writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700353 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700354 writel(((u64) chan->completion_dma) >> 32,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700355 chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700356
Dan Williamsdcbc8532009-07-28 14:44:50 -0700357 tasklet_enable(&chan->cleanup_task);
Dan Williams5cbafa62009-08-26 13:01:44 -0700358 ioat1_dma_start_null_desc(ioat); /* give chain to dma device */
Dan Williams6df91832009-09-08 12:00:55 -0700359 dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
360 __func__, ioat->desccount);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700361 return ioat->desccount;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700362}
363
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800364/**
Dan Williams5cbafa62009-08-26 13:01:44 -0700365 * ioat1_dma_free_chan_resources - release all the descriptors
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800366 * @chan: the channel to be cleaned
367 */
Dan Williams5cbafa62009-08-26 13:01:44 -0700368static void ioat1_dma_free_chan_resources(struct dma_chan *c)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700369{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700370 struct ioat_dma_chan *ioat = to_ioat_chan(c);
371 struct ioat_chan_common *chan = &ioat->base;
372 struct ioatdma_device *ioatdma_device = chan->device;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700373 struct ioat_desc_sw *desc, *_desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700374 int in_use_descs = 0;
375
Maciej Sosnowskic3d4f442008-11-07 01:45:52 +0000376 /* Before freeing channel resources first check
377 * if they have been previously allocated for this channel.
378 */
Dan Williamsdcbc8532009-07-28 14:44:50 -0700379 if (ioat->desccount == 0)
Maciej Sosnowskic3d4f442008-11-07 01:45:52 +0000380 return;
381
Dan Williamsdcbc8532009-07-28 14:44:50 -0700382 tasklet_disable(&chan->cleanup_task);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700383 del_timer_sync(&chan->timer);
Dan Williams5cbafa62009-08-26 13:01:44 -0700384 ioat1_cleanup(ioat);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700385
Shannon Nelson3e037452007-10-16 01:27:40 -0700386 /* Delay 100ms after reset to allow internal DMA logic to quiesce
387 * before removing DMA descriptor resources.
388 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800389 writeb(IOAT_CHANCMD_RESET,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700390 chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
Shannon Nelson3e037452007-10-16 01:27:40 -0700391 mdelay(100);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700392
Dan Williamsdcbc8532009-07-28 14:44:50 -0700393 spin_lock_bh(&ioat->desc_lock);
Dan Williams6df91832009-09-08 12:00:55 -0700394 list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
395 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
396 __func__, desc_id(desc));
397 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700398 in_use_descs++;
399 list_del(&desc->node);
Shannon Nelson8ab89562007-10-16 01:27:39 -0700400 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
Dan Williamsbc3c7022009-07-28 14:33:42 -0700401 desc->txd.phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700402 kfree(desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700403 }
404 list_for_each_entry_safe(desc, _desc,
405 &ioat->free_desc, node) {
406 list_del(&desc->node);
407 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
408 desc->txd.phys);
409 kfree(desc);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700410 }
Dan Williamsdcbc8532009-07-28 14:44:50 -0700411 spin_unlock_bh(&ioat->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700412
Shannon Nelson8ab89562007-10-16 01:27:39 -0700413 pci_pool_free(ioatdma_device->completion_pool,
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700414 chan->completion,
415 chan->completion_dma);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700416
417 /* one is ok since we left it on there on purpose */
418 if (in_use_descs > 1)
Dan Williamsdcbc8532009-07-28 14:44:50 -0700419 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
Chris Leech0bbd5f42006-05-23 17:35:34 -0700420 in_use_descs - 1);
421
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700422 chan->last_completion = 0;
423 chan->completion_dma = 0;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700424 ioat->pending = 0;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700425 ioat->desccount = 0;
Shannon Nelson3e037452007-10-16 01:27:40 -0700426}
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700427
Shannon Nelson3e037452007-10-16 01:27:40 -0700428/**
Dan Williamsdcbc8532009-07-28 14:44:50 -0700429 * ioat1_dma_get_next_descriptor - return the next available descriptor
430 * @ioat: IOAT DMA channel handle
Shannon Nelson3e037452007-10-16 01:27:40 -0700431 *
432 * Gets the next descriptor from the chain, and must be called with the
433 * channel's desc_lock held. Allocates more descriptors if the channel
434 * has run out.
435 */
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700436static struct ioat_desc_sw *
Dan Williamsdcbc8532009-07-28 14:44:50 -0700437ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
Shannon Nelson3e037452007-10-16 01:27:40 -0700438{
Shannon Nelson711924b2007-12-17 16:20:08 -0800439 struct ioat_desc_sw *new;
Shannon Nelson3e037452007-10-16 01:27:40 -0700440
Dan Williamsdcbc8532009-07-28 14:44:50 -0700441 if (!list_empty(&ioat->free_desc)) {
442 new = to_ioat_desc(ioat->free_desc.next);
Shannon Nelson3e037452007-10-16 01:27:40 -0700443 list_del(&new->node);
444 } else {
445 /* try to get another desc */
Dan Williamsdcbc8532009-07-28 14:44:50 -0700446 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
Shannon Nelson711924b2007-12-17 16:20:08 -0800447 if (!new) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700448 dev_err(to_dev(&ioat->base), "alloc failed\n");
Shannon Nelson711924b2007-12-17 16:20:08 -0800449 return NULL;
450 }
Shannon Nelson3e037452007-10-16 01:27:40 -0700451 }
Dan Williams6df91832009-09-08 12:00:55 -0700452 dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
453 __func__, desc_id(new));
Shannon Nelson3e037452007-10-16 01:27:40 -0700454 prefetch(new->hw);
455 return new;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700456}
457
Dan Williamsbc3c7022009-07-28 14:33:42 -0700458static struct dma_async_tx_descriptor *
Dan Williamsdcbc8532009-07-28 14:44:50 -0700459ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
Dan Williamsbc3c7022009-07-28 14:33:42 -0700460 dma_addr_t dma_src, size_t len, unsigned long flags)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700461{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700462 struct ioat_dma_chan *ioat = to_ioat_chan(c);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700463 struct ioat_desc_sw *desc;
464 size_t copy;
465 LIST_HEAD(chain);
466 dma_addr_t src = dma_src;
467 dma_addr_t dest = dma_dest;
468 size_t total_len = len;
469 struct ioat_dma_descriptor *hw = NULL;
470 int tx_cnt = 0;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700471
Dan Williamsdcbc8532009-07-28 14:44:50 -0700472 spin_lock_bh(&ioat->desc_lock);
Dan Williams5cbafa62009-08-26 13:01:44 -0700473 desc = ioat1_dma_get_next_descriptor(ioat);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700474 do {
475 if (!desc)
476 break;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700477
Dan Williamsa0587bc2009-07-28 14:44:04 -0700478 tx_cnt++;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700479 copy = min_t(size_t, len, ioat->xfercap);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700480
481 hw = desc->hw;
482 hw->size = copy;
483 hw->ctl = 0;
484 hw->src_addr = src;
485 hw->dst_addr = dest;
486
487 list_add_tail(&desc->node, &chain);
488
489 len -= copy;
490 dest += copy;
491 src += copy;
492 if (len) {
493 struct ioat_desc_sw *next;
494
495 async_tx_ack(&desc->txd);
Dan Williams5cbafa62009-08-26 13:01:44 -0700496 next = ioat1_dma_get_next_descriptor(ioat);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700497 hw->next = next ? next->txd.phys : 0;
Dan Williams6df91832009-09-08 12:00:55 -0700498 dump_desc_dbg(ioat, desc);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700499 desc = next;
500 } else
501 hw->next = 0;
502 } while (len);
503
504 if (!desc) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700505 struct ioat_chan_common *chan = &ioat->base;
506
507 dev_err(to_dev(chan),
Dan Williams5cbafa62009-08-26 13:01:44 -0700508 "chan%d - get_next_desc failed\n", chan_num(chan));
Dan Williamsdcbc8532009-07-28 14:44:50 -0700509 list_splice(&chain, &ioat->free_desc);
510 spin_unlock_bh(&ioat->desc_lock);
Shannon Nelson711924b2007-12-17 16:20:08 -0800511 return NULL;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700512 }
Dan Williamsdcbc8532009-07-28 14:44:50 -0700513 spin_unlock_bh(&ioat->desc_lock);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700514
515 desc->txd.flags = flags;
Dan Williamsa0587bc2009-07-28 14:44:04 -0700516 desc->len = total_len;
Dan Williamsea259682009-09-08 17:53:02 -0700517 list_splice(&chain, &desc->tx_list);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700518 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
519 hw->ctl_f.compl_write = 1;
Dan Williamsad643f52009-09-08 12:01:38 -0700520 hw->tx_cnt = tx_cnt;
Dan Williams6df91832009-09-08 12:00:55 -0700521 dump_desc_dbg(ioat, desc);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700522
523 return &desc->txd;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700524}
525
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700526static void ioat1_cleanup_event(unsigned long data)
Shannon Nelson3e037452007-10-16 01:27:40 -0700527{
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700528 struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
Dan Williamsf6ab95b2009-09-08 12:01:21 -0700529
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700530 ioat1_cleanup(ioat);
531 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
Shannon Nelson3e037452007-10-16 01:27:40 -0700532}
533
Dan Williams27502932012-03-23 13:36:42 -0700534dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan)
Dan Williams5cbafa62009-08-26 13:01:44 -0700535{
Dan Williams27502932012-03-23 13:36:42 -0700536 dma_addr_t phys_complete;
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700537 u64 completion;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700538
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700539 completion = *chan->completion;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700540 phys_complete = ioat_chansts_to_addr(completion);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700541
Dan Williams6df91832009-09-08 12:00:55 -0700542 dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
543 (unsigned long long) phys_complete);
544
Dan Williams09c8a5b2009-09-08 12:01:49 -0700545 if (is_ioat_halted(completion)) {
546 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700547 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
Dan Williams09c8a5b2009-09-08 12:01:49 -0700548 chanerr);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700549
550 /* TODO do something to salvage the situation */
551 }
552
Dan Williams5cbafa62009-08-26 13:01:44 -0700553 return phys_complete;
554}
555
Dan Williams09c8a5b2009-09-08 12:01:49 -0700556bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
Dan Williams27502932012-03-23 13:36:42 -0700557 dma_addr_t *phys_complete)
Dan Williams09c8a5b2009-09-08 12:01:49 -0700558{
559 *phys_complete = ioat_get_current_completion(chan);
560 if (*phys_complete == chan->last_completion)
561 return false;
562 clear_bit(IOAT_COMPLETION_ACK, &chan->state);
563 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
564
565 return true;
566}
567
Dan Williams27502932012-03-23 13:36:42 -0700568static void __cleanup(struct ioat_dma_chan *ioat, dma_addr_t phys_complete)
Dan Williams5cbafa62009-08-26 13:01:44 -0700569{
570 struct ioat_chan_common *chan = &ioat->base;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700571 struct list_head *_desc, *n;
Dan Williams5cbafa62009-08-26 13:01:44 -0700572 struct dma_async_tx_descriptor *tx;
573
Dan Williams27502932012-03-23 13:36:42 -0700574 dev_dbg(to_dev(chan), "%s: phys_complete: %llx\n",
575 __func__, (unsigned long long) phys_complete);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700576 list_for_each_safe(_desc, n, &ioat->used_desc) {
577 struct ioat_desc_sw *desc;
578
579 prefetch(n);
580 desc = list_entry(_desc, typeof(*desc), node);
Dan Williamsbc3c7022009-07-28 14:33:42 -0700581 tx = &desc->txd;
Dan Williams5cbafa62009-08-26 13:01:44 -0700582 /*
583 * Incoming DMA requests may use multiple descriptors,
584 * due to exceeding xfercap, perhaps. If so, only the
585 * last one will have a cookie, and require unmapping.
586 */
Dan Williams6df91832009-09-08 12:00:55 -0700587 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700588 if (tx->cookie) {
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +0000589 dma_cookie_complete(tx);
Dan Williamsd38a8c62013-10-18 19:35:23 +0200590 dma_descriptor_unmap(tx);
Dan Williams5669e312009-09-08 17:42:56 -0700591 ioat->active -= desc->hw->tx_cnt;
Dan Williams5cbafa62009-08-26 13:01:44 -0700592 if (tx->callback) {
593 tx->callback(tx->callback_param);
594 tx->callback = NULL;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800595 }
Chris Leech0bbd5f42006-05-23 17:35:34 -0700596 }
Dan Williams5cbafa62009-08-26 13:01:44 -0700597
598 if (tx->phys != phys_complete) {
599 /*
600 * a completed entry, but not the last, so clean
601 * up if the client is done with the descriptor
602 */
603 if (async_tx_test_ack(tx))
604 list_move_tail(&desc->node, &ioat->free_desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700605 } else {
606 /*
607 * last used desc. Do not remove, so we can
Dan Williams09c8a5b2009-09-08 12:01:49 -0700608 * append from it.
Dan Williams5cbafa62009-08-26 13:01:44 -0700609 */
Dan Williams09c8a5b2009-09-08 12:01:49 -0700610
611 /* if nothing else is pending, cancel the
612 * completion timeout
613 */
614 if (n == &ioat->used_desc) {
615 dev_dbg(to_dev(chan),
616 "%s cancel completion timeout\n",
617 __func__);
618 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
619 }
Dan Williams5cbafa62009-08-26 13:01:44 -0700620
621 /* TODO check status bits? */
622 break;
623 }
Chris Leech0bbd5f42006-05-23 17:35:34 -0700624 }
625
Dan Williamsdcbc8532009-07-28 14:44:50 -0700626 chan->last_completion = phys_complete;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700627}
Chris Leech0bbd5f42006-05-23 17:35:34 -0700628
Dan Williams09c8a5b2009-09-08 12:01:49 -0700629/**
630 * ioat1_cleanup - cleanup up finished descriptors
631 * @chan: ioat channel to be cleaned up
632 *
633 * To prevent lock contention we defer cleanup when the locks are
634 * contended with a terminal timeout that forces cleanup and catches
635 * completion notification errors.
636 */
637static void ioat1_cleanup(struct ioat_dma_chan *ioat)
638{
639 struct ioat_chan_common *chan = &ioat->base;
Dan Williams27502932012-03-23 13:36:42 -0700640 dma_addr_t phys_complete;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700641
642 prefetch(chan->completion);
643
644 if (!spin_trylock_bh(&chan->cleanup_lock))
645 return;
646
647 if (!ioat_cleanup_preamble(chan, &phys_complete)) {
648 spin_unlock_bh(&chan->cleanup_lock);
649 return;
650 }
651
652 if (!spin_trylock_bh(&ioat->desc_lock)) {
653 spin_unlock_bh(&chan->cleanup_lock);
654 return;
655 }
656
657 __cleanup(ioat, phys_complete);
658
659 spin_unlock_bh(&ioat->desc_lock);
660 spin_unlock_bh(&chan->cleanup_lock);
661}
662
663static void ioat1_timer_event(unsigned long data)
664{
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700665 struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700666 struct ioat_chan_common *chan = &ioat->base;
667
668 dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state);
669
670 spin_lock_bh(&chan->cleanup_lock);
671 if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) {
672 struct ioat_desc_sw *desc;
673
674 spin_lock_bh(&ioat->desc_lock);
675
676 /* restart active descriptors */
677 desc = to_ioat_desc(ioat->used_desc.prev);
678 ioat_set_chainaddr(ioat, desc->txd.phys);
679 ioat_start(chan);
680
681 ioat->pending = 0;
682 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
683 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
684 spin_unlock_bh(&ioat->desc_lock);
685 } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
Dan Williams27502932012-03-23 13:36:42 -0700686 dma_addr_t phys_complete;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700687
688 spin_lock_bh(&ioat->desc_lock);
689 /* if we haven't made progress and we have already
690 * acknowledged a pending completion once, then be more
691 * forceful with a restart
692 */
693 if (ioat_cleanup_preamble(chan, &phys_complete))
694 __cleanup(ioat, phys_complete);
695 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
696 ioat1_reset_channel(ioat);
697 else {
698 u64 status = ioat_chansts(chan);
699
700 /* manually update the last completion address */
701 if (ioat_chansts_to_addr(status) != 0)
702 *chan->completion = status;
703
704 set_bit(IOAT_COMPLETION_ACK, &chan->state);
705 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
706 }
707 spin_unlock_bh(&ioat->desc_lock);
708 }
Dan Williamsdcbc8532009-07-28 14:44:50 -0700709 spin_unlock_bh(&chan->cleanup_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700710}
711
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700712enum dma_status
Linus Walleij07934482010-03-26 16:50:49 -0700713ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
714 struct dma_tx_state *txstate)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700715{
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700716 struct ioat_chan_common *chan = to_chan_common(c);
717 struct ioatdma_device *device = chan->device;
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000718 enum dma_status ret;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700719
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000720 ret = dma_cookie_status(c, cookie, txstate);
Vinod Koul2f16f802013-10-16 20:48:52 +0530721 if (ret == DMA_COMPLETE)
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000722 return ret;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700723
Dan Williamsaa4d72a2010-03-03 21:21:13 -0700724 device->cleanup_fn((unsigned long) c);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700725
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000726 return dma_cookie_status(c, cookie, txstate);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700727}
728
Dan Williams5cbafa62009-08-26 13:01:44 -0700729static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700730{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700731 struct ioat_chan_common *chan = &ioat->base;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700732 struct ioat_desc_sw *desc;
Dan Williamsc7984f42009-07-28 14:44:04 -0700733 struct ioat_dma_descriptor *hw;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700734
Dan Williamsdcbc8532009-07-28 14:44:50 -0700735 spin_lock_bh(&ioat->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700736
Dan Williams5cbafa62009-08-26 13:01:44 -0700737 desc = ioat1_dma_get_next_descriptor(ioat);
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700738
739 if (!desc) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700740 dev_err(to_dev(chan),
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700741 "Unable to start null desc - get next desc failed\n");
Dan Williamsdcbc8532009-07-28 14:44:50 -0700742 spin_unlock_bh(&ioat->desc_lock);
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700743 return;
744 }
745
Dan Williamsc7984f42009-07-28 14:44:04 -0700746 hw = desc->hw;
747 hw->ctl = 0;
748 hw->ctl_f.null = 1;
749 hw->ctl_f.int_en = 1;
750 hw->ctl_f.compl_write = 1;
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700751 /* set size to non-zero value (channel returns error when size is 0) */
Dan Williamsc7984f42009-07-28 14:44:04 -0700752 hw->size = NULL_DESC_BUFFER_SIZE;
753 hw->src_addr = 0;
754 hw->dst_addr = 0;
Dan Williamsbc3c7022009-07-28 14:33:42 -0700755 async_tx_ack(&desc->txd);
Dan Williams5cbafa62009-08-26 13:01:44 -0700756 hw->next = 0;
757 list_add_tail(&desc->node, &ioat->used_desc);
Dan Williams6df91832009-09-08 12:00:55 -0700758 dump_desc_dbg(ioat, desc);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700759
Dan Williams09c8a5b2009-09-08 12:01:49 -0700760 ioat_set_chainaddr(ioat, desc->txd.phys);
761 ioat_start(chan);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700762 spin_unlock_bh(&ioat->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700763}
764
765/*
766 * Perform a IOAT transaction to verify the HW works.
767 */
768#define IOAT_TEST_SIZE 2000
769
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -0800770static void ioat_dma_test_callback(void *dma_async_param)
Shannon Nelson95218432007-10-18 03:07:15 -0700771{
Dan Williamsb9bdcbb2009-01-06 11:38:22 -0700772 struct completion *cmp = dma_async_param;
773
774 complete(cmp);
Shannon Nelson95218432007-10-18 03:07:15 -0700775}
776
Shannon Nelson3e037452007-10-16 01:27:40 -0700777/**
778 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
779 * @device: device to be tested
780 */
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -0800781int ioat_dma_self_test(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700782{
783 int i;
784 u8 *src;
785 u8 *dest;
Dan Williamsbc3c7022009-07-28 14:33:42 -0700786 struct dma_device *dma = &device->common;
787 struct device *dev = &device->pdev->dev;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700788 struct dma_chan *dma_chan;
Shannon Nelson711924b2007-12-17 16:20:08 -0800789 struct dma_async_tx_descriptor *tx;
Dan Williams00367312008-02-02 19:49:57 -0700790 dma_addr_t dma_dest, dma_src;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700791 dma_cookie_t cookie;
792 int err = 0;
Dan Williamsb9bdcbb2009-01-06 11:38:22 -0700793 struct completion cmp;
Dan Williams0c33e1c2009-03-02 13:31:35 -0700794 unsigned long tmo;
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200795 unsigned long flags;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700796
Christoph Lametere94b1762006-12-06 20:33:17 -0800797 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700798 if (!src)
799 return -ENOMEM;
Christoph Lametere94b1762006-12-06 20:33:17 -0800800 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700801 if (!dest) {
802 kfree(src);
803 return -ENOMEM;
804 }
805
806 /* Fill in src buffer */
807 for (i = 0; i < IOAT_TEST_SIZE; i++)
808 src[i] = (u8)i;
809
810 /* Start copy, using first DMA channel */
Dan Williamsbc3c7022009-07-28 14:33:42 -0700811 dma_chan = container_of(dma->channels.next, struct dma_chan,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700812 device_node);
Dan Williamsbc3c7022009-07-28 14:33:42 -0700813 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
814 dev_err(dev, "selftest cannot allocate chan resource\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -0700815 err = -ENODEV;
816 goto out;
817 }
818
Dan Williamsbc3c7022009-07-28 14:33:42 -0700819 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
Jiang Liu3532e562014-01-02 12:58:52 -0800820 if (dma_mapping_error(dev, dma_src)) {
821 dev_err(dev, "mapping src buffer failed\n");
822 goto free_resources;
823 }
Dan Williamsbc3c7022009-07-28 14:33:42 -0700824 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
Jiang Liu3532e562014-01-02 12:58:52 -0800825 if (dma_mapping_error(dev, dma_dest)) {
826 dev_err(dev, "mapping dest buffer failed\n");
827 goto unmap_src;
828 }
Bartlomiej Zolnierkiewicz0776ae72013-10-18 19:35:33 +0200829 flags = DMA_PREP_INTERRUPT;
Dan Williams00367312008-02-02 19:49:57 -0700830 tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200831 IOAT_TEST_SIZE, flags);
Shannon Nelson5149fd02007-10-18 03:07:13 -0700832 if (!tx) {
Dan Williamsbc3c7022009-07-28 14:33:42 -0700833 dev_err(dev, "Self-test prep failed, disabling\n");
Shannon Nelson5149fd02007-10-18 03:07:13 -0700834 err = -ENODEV;
Bartlomiej Zolnierkiewicz522d9742012-11-05 10:00:13 +0000835 goto unmap_dma;
Shannon Nelson5149fd02007-10-18 03:07:13 -0700836 }
837
Dan Williams7405f742007-01-02 11:10:43 -0700838 async_tx_ack(tx);
Dan Williamsb9bdcbb2009-01-06 11:38:22 -0700839 init_completion(&cmp);
Shannon Nelson95218432007-10-18 03:07:15 -0700840 tx->callback = ioat_dma_test_callback;
Dan Williamsb9bdcbb2009-01-06 11:38:22 -0700841 tx->callback_param = &cmp;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800842 cookie = tx->tx_submit(tx);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700843 if (cookie < 0) {
Dan Williamsbc3c7022009-07-28 14:33:42 -0700844 dev_err(dev, "Self-test setup failed, disabling\n");
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700845 err = -ENODEV;
Bartlomiej Zolnierkiewicz522d9742012-11-05 10:00:13 +0000846 goto unmap_dma;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700847 }
Dan Williamsbc3c7022009-07-28 14:33:42 -0700848 dma->device_issue_pending(dma_chan);
Dan Williams532d3b12008-12-03 17:16:55 -0700849
Dan Williams0c33e1c2009-03-02 13:31:35 -0700850 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
Chris Leech0bbd5f42006-05-23 17:35:34 -0700851
Dan Williams0c33e1c2009-03-02 13:31:35 -0700852 if (tmo == 0 ||
Linus Walleij07934482010-03-26 16:50:49 -0700853 dma->device_tx_status(dma_chan, cookie, NULL)
Vinod Koul2f16f802013-10-16 20:48:52 +0530854 != DMA_COMPLETE) {
Dan Williamsbc3c7022009-07-28 14:33:42 -0700855 dev_err(dev, "Self-test copy timed out, disabling\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -0700856 err = -ENODEV;
Bartlomiej Zolnierkiewicz522d9742012-11-05 10:00:13 +0000857 goto unmap_dma;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700858 }
859 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
Dan Williamsbc3c7022009-07-28 14:33:42 -0700860 dev_err(dev, "Self-test copy failed compare, disabling\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -0700861 err = -ENODEV;
862 goto free_resources;
863 }
864
Bartlomiej Zolnierkiewicz522d9742012-11-05 10:00:13 +0000865unmap_dma:
Bartlomiej Zolnierkiewicz522d9742012-11-05 10:00:13 +0000866 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
Jiang Liu3532e562014-01-02 12:58:52 -0800867unmap_src:
868 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700869free_resources:
Dan Williamsbc3c7022009-07-28 14:33:42 -0700870 dma->device_free_chan_resources(dma_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700871out:
872 kfree(src);
873 kfree(dest);
874 return err;
875}
876
Shannon Nelson3e037452007-10-16 01:27:40 -0700877static char ioat_interrupt_style[32] = "msix";
878module_param_string(ioat_interrupt_style, ioat_interrupt_style,
879 sizeof(ioat_interrupt_style), 0644);
880MODULE_PARM_DESC(ioat_interrupt_style,
Dan Williams4c5d9612013-11-13 16:29:52 -0800881 "set ioat interrupt style: msix (default), msi, intx");
Shannon Nelson3e037452007-10-16 01:27:40 -0700882
883/**
884 * ioat_dma_setup_interrupts - setup interrupt handler
885 * @device: ioat device
886 */
Dave Jiang8a52b9f2013-03-26 15:42:47 -0700887int ioat_dma_setup_interrupts(struct ioatdma_device *device)
Shannon Nelson3e037452007-10-16 01:27:40 -0700888{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700889 struct ioat_chan_common *chan;
Dan Williamse6c0b692009-09-08 17:29:44 -0700890 struct pci_dev *pdev = device->pdev;
891 struct device *dev = &pdev->dev;
892 struct msix_entry *msix;
893 int i, j, msixcnt;
894 int err = -EINVAL;
Shannon Nelson3e037452007-10-16 01:27:40 -0700895 u8 intrctrl = 0;
896
897 if (!strcmp(ioat_interrupt_style, "msix"))
898 goto msix;
Shannon Nelson3e037452007-10-16 01:27:40 -0700899 if (!strcmp(ioat_interrupt_style, "msi"))
900 goto msi;
901 if (!strcmp(ioat_interrupt_style, "intx"))
902 goto intx;
Dan Williamse6c0b692009-09-08 17:29:44 -0700903 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
Shannon Nelson5149fd02007-10-18 03:07:13 -0700904 goto err_no_irq;
Shannon Nelson3e037452007-10-16 01:27:40 -0700905
906msix:
907 /* The number of MSI-X vectors should equal the number of channels */
908 msixcnt = device->common.chancnt;
909 for (i = 0; i < msixcnt; i++)
910 device->msix_entries[i].entry = i;
911
Dan Williamse6c0b692009-09-08 17:29:44 -0700912 err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
Dan Williams4c5d9612013-11-13 16:29:52 -0800913 if (err)
Shannon Nelson3e037452007-10-16 01:27:40 -0700914 goto msi;
Shannon Nelson3e037452007-10-16 01:27:40 -0700915
916 for (i = 0; i < msixcnt; i++) {
Dan Williamse6c0b692009-09-08 17:29:44 -0700917 msix = &device->msix_entries[i];
Dan Williamsdcbc8532009-07-28 14:44:50 -0700918 chan = ioat_chan_by_index(device, i);
Dan Williamse6c0b692009-09-08 17:29:44 -0700919 err = devm_request_irq(dev, msix->vector,
920 ioat_dma_do_interrupt_msix, 0,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700921 "ioat-msix", chan);
Shannon Nelson3e037452007-10-16 01:27:40 -0700922 if (err) {
923 for (j = 0; j < i; j++) {
Dan Williamse6c0b692009-09-08 17:29:44 -0700924 msix = &device->msix_entries[j];
Dan Williamsdcbc8532009-07-28 14:44:50 -0700925 chan = ioat_chan_by_index(device, j);
926 devm_free_irq(dev, msix->vector, chan);
Shannon Nelson3e037452007-10-16 01:27:40 -0700927 }
Dan Williams4c5d9612013-11-13 16:29:52 -0800928 goto msi;
Shannon Nelson3e037452007-10-16 01:27:40 -0700929 }
930 }
931 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
Dave Jiang8a52b9f2013-03-26 15:42:47 -0700932 device->irq_mode = IOAT_MSIX;
Shannon Nelson3e037452007-10-16 01:27:40 -0700933 goto done;
934
Shannon Nelson3e037452007-10-16 01:27:40 -0700935msi:
Dan Williamse6c0b692009-09-08 17:29:44 -0700936 err = pci_enable_msi(pdev);
Shannon Nelson3e037452007-10-16 01:27:40 -0700937 if (err)
938 goto intx;
939
Dan Williamse6c0b692009-09-08 17:29:44 -0700940 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
941 "ioat-msi", device);
Shannon Nelson3e037452007-10-16 01:27:40 -0700942 if (err) {
Dan Williamse6c0b692009-09-08 17:29:44 -0700943 pci_disable_msi(pdev);
Shannon Nelson3e037452007-10-16 01:27:40 -0700944 goto intx;
945 }
Dan Williams779e5612013-11-13 16:30:43 -0800946 device->irq_mode = IOAT_MSI;
Shannon Nelson3e037452007-10-16 01:27:40 -0700947 goto done;
948
949intx:
Dan Williamse6c0b692009-09-08 17:29:44 -0700950 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
951 IRQF_SHARED, "ioat-intx", device);
Shannon Nelson3e037452007-10-16 01:27:40 -0700952 if (err)
953 goto err_no_irq;
Shannon Nelson3e037452007-10-16 01:27:40 -0700954
Dave Jiang8a52b9f2013-03-26 15:42:47 -0700955 device->irq_mode = IOAT_INTX;
Shannon Nelson3e037452007-10-16 01:27:40 -0700956done:
Dan Williamsf2427e22009-07-28 14:42:38 -0700957 if (device->intr_quirk)
958 device->intr_quirk(device);
Shannon Nelson3e037452007-10-16 01:27:40 -0700959 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
960 writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
961 return 0;
962
963err_no_irq:
964 /* Disable all interrupt generation */
965 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
Dave Jiang8a52b9f2013-03-26 15:42:47 -0700966 device->irq_mode = IOAT_NOIRQ;
Dan Williamse6c0b692009-09-08 17:29:44 -0700967 dev_err(dev, "no usable interrupts\n");
968 return err;
Shannon Nelson3e037452007-10-16 01:27:40 -0700969}
Dave Jiang8a52b9f2013-03-26 15:42:47 -0700970EXPORT_SYMBOL(ioat_dma_setup_interrupts);
Shannon Nelson3e037452007-10-16 01:27:40 -0700971
Dan Williamse6c0b692009-09-08 17:29:44 -0700972static void ioat_disable_interrupts(struct ioatdma_device *device)
Shannon Nelson3e037452007-10-16 01:27:40 -0700973{
Shannon Nelson3e037452007-10-16 01:27:40 -0700974 /* Disable all interrupt generation */
975 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
Shannon Nelson3e037452007-10-16 01:27:40 -0700976}
977
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -0800978int ioat_probe(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700979{
Dan Williamsf2427e22009-07-28 14:42:38 -0700980 int err = -ENODEV;
981 struct dma_device *dma = &device->common;
982 struct pci_dev *pdev = device->pdev;
Dan Williamse6c0b692009-09-08 17:29:44 -0700983 struct device *dev = &pdev->dev;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700984
985 /* DMA coherent memory pool for DMA descriptor allocations */
986 device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
Shannon Nelson8ab89562007-10-16 01:27:39 -0700987 sizeof(struct ioat_dma_descriptor),
988 64, 0);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700989 if (!device->dma_pool) {
990 err = -ENOMEM;
991 goto err_dma_pool;
992 }
993
Shannon Nelson43d6e362007-10-16 01:27:39 -0700994 device->completion_pool = pci_pool_create("completion_pool", pdev,
995 sizeof(u64), SMP_CACHE_BYTES,
996 SMP_CACHE_BYTES);
Dan Williams5cbafa62009-08-26 13:01:44 -0700997
Chris Leech0bbd5f42006-05-23 17:35:34 -0700998 if (!device->completion_pool) {
999 err = -ENOMEM;
1000 goto err_completion_pool;
1001 }
1002
Dan Williams5cbafa62009-08-26 13:01:44 -07001003 device->enumerate_channels(device);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001004
Dan Williamsf2427e22009-07-28 14:42:38 -07001005 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
Dan Williamsf2427e22009-07-28 14:42:38 -07001006 dma->dev = &pdev->dev;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001007
Dan Williamsbc3c7022009-07-28 14:33:42 -07001008 if (!dma->chancnt) {
Dan Williamsa6d52d72009-12-19 15:36:02 -07001009 dev_err(dev, "channel enumeration error\n");
Maciej Sosnowski8b794b12009-02-26 11:04:54 +01001010 goto err_setup_interrupts;
1011 }
1012
Shannon Nelson3e037452007-10-16 01:27:40 -07001013 err = ioat_dma_setup_interrupts(device);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001014 if (err)
Shannon Nelson3e037452007-10-16 01:27:40 -07001015 goto err_setup_interrupts;
Shannon Nelson8ab89562007-10-16 01:27:39 -07001016
Dan Williams9de6fc72009-09-08 17:42:58 -07001017 err = device->self_test(device);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001018 if (err)
1019 goto err_self_test;
1020
Dan Williamsf2427e22009-07-28 14:42:38 -07001021 return 0;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001022
1023err_self_test:
Dan Williamse6c0b692009-09-08 17:29:44 -07001024 ioat_disable_interrupts(device);
Shannon Nelson3e037452007-10-16 01:27:40 -07001025err_setup_interrupts:
Chris Leech0bbd5f42006-05-23 17:35:34 -07001026 pci_pool_destroy(device->completion_pool);
1027err_completion_pool:
1028 pci_pool_destroy(device->dma_pool);
1029err_dma_pool:
Dan Williamsf2427e22009-07-28 14:42:38 -07001030 return err;
1031}
1032
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08001033int ioat_register(struct ioatdma_device *device)
Dan Williamsf2427e22009-07-28 14:42:38 -07001034{
1035 int err = dma_async_device_register(&device->common);
1036
1037 if (err) {
1038 ioat_disable_interrupts(device);
1039 pci_pool_destroy(device->completion_pool);
1040 pci_pool_destroy(device->dma_pool);
1041 }
1042
1043 return err;
1044}
1045
1046/* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1047static void ioat1_intr_quirk(struct ioatdma_device *device)
1048{
1049 struct pci_dev *pdev = device->pdev;
1050 u32 dmactrl;
1051
1052 pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1053 if (pdev->msi_enabled)
1054 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1055 else
1056 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1057 pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1058}
1059
Dan Williams5669e312009-09-08 17:42:56 -07001060static ssize_t ring_size_show(struct dma_chan *c, char *page)
1061{
1062 struct ioat_dma_chan *ioat = to_ioat_chan(c);
1063
1064 return sprintf(page, "%d\n", ioat->desccount);
1065}
1066static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
1067
1068static ssize_t ring_active_show(struct dma_chan *c, char *page)
1069{
1070 struct ioat_dma_chan *ioat = to_ioat_chan(c);
1071
1072 return sprintf(page, "%d\n", ioat->active);
1073}
1074static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
1075
1076static ssize_t cap_show(struct dma_chan *c, char *page)
1077{
1078 struct dma_device *dma = c->device;
1079
Bartlomiej Zolnierkiewicz48a9db42013-07-03 15:05:06 -07001080 return sprintf(page, "copy%s%s%s%s%s\n",
Dan Williams5669e312009-09-08 17:42:56 -07001081 dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "",
1082 dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "",
1083 dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "",
1084 dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "",
Dan Williams5669e312009-09-08 17:42:56 -07001085 dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : "");
1086
1087}
1088struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap);
1089
1090static ssize_t version_show(struct dma_chan *c, char *page)
1091{
1092 struct dma_device *dma = c->device;
1093 struct ioatdma_device *device = to_ioatdma_device(dma);
1094
1095 return sprintf(page, "%d.%d\n",
1096 device->version >> 4, device->version & 0xf);
1097}
1098struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version);
1099
1100static struct attribute *ioat1_attrs[] = {
1101 &ring_size_attr.attr,
1102 &ring_active_attr.attr,
1103 &ioat_cap_attr.attr,
1104 &ioat_version_attr.attr,
1105 NULL,
1106};
1107
1108static ssize_t
1109ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page)
1110{
1111 struct ioat_sysfs_entry *entry;
1112 struct ioat_chan_common *chan;
1113
1114 entry = container_of(attr, struct ioat_sysfs_entry, attr);
1115 chan = container_of(kobj, struct ioat_chan_common, kobj);
1116
1117 if (!entry->show)
1118 return -EIO;
1119 return entry->show(&chan->common, page);
1120}
1121
Emese Revfy52cf25d2010-01-19 02:58:23 +01001122const struct sysfs_ops ioat_sysfs_ops = {
Dan Williams5669e312009-09-08 17:42:56 -07001123 .show = ioat_attr_show,
1124};
1125
1126static struct kobj_type ioat1_ktype = {
1127 .sysfs_ops = &ioat_sysfs_ops,
1128 .default_attrs = ioat1_attrs,
1129};
1130
1131void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type)
1132{
1133 struct dma_device *dma = &device->common;
1134 struct dma_chan *c;
1135
1136 list_for_each_entry(c, &dma->channels, device_node) {
1137 struct ioat_chan_common *chan = to_chan_common(c);
1138 struct kobject *parent = &c->dev->device.kobj;
1139 int err;
1140
1141 err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata");
1142 if (err) {
1143 dev_warn(to_dev(chan),
1144 "sysfs init error (%d), continuing...\n", err);
1145 kobject_put(&chan->kobj);
1146 set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state);
1147 }
1148 }
1149}
1150
1151void ioat_kobject_del(struct ioatdma_device *device)
1152{
1153 struct dma_device *dma = &device->common;
1154 struct dma_chan *c;
1155
1156 list_for_each_entry(c, &dma->channels, device_node) {
1157 struct ioat_chan_common *chan = to_chan_common(c);
1158
1159 if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) {
1160 kobject_del(&chan->kobj);
1161 kobject_put(&chan->kobj);
1162 }
1163 }
1164}
1165
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08001166int ioat1_dma_probe(struct ioatdma_device *device, int dca)
Dan Williamsf2427e22009-07-28 14:42:38 -07001167{
1168 struct pci_dev *pdev = device->pdev;
1169 struct dma_device *dma;
1170 int err;
1171
1172 device->intr_quirk = ioat1_intr_quirk;
Dan Williams5cbafa62009-08-26 13:01:44 -07001173 device->enumerate_channels = ioat1_enumerate_channels;
Dan Williams9de6fc72009-09-08 17:42:58 -07001174 device->self_test = ioat_dma_self_test;
Dan Williamsaa4d72a2010-03-03 21:21:13 -07001175 device->timer_fn = ioat1_timer_event;
1176 device->cleanup_fn = ioat1_cleanup_event;
Dan Williamsf2427e22009-07-28 14:42:38 -07001177 dma = &device->common;
1178 dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1179 dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
Dan Williams5cbafa62009-08-26 13:01:44 -07001180 dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1181 dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
Linus Walleij07934482010-03-26 16:50:49 -07001182 dma->device_tx_status = ioat_dma_tx_status;
Dan Williamsf2427e22009-07-28 14:42:38 -07001183
1184 err = ioat_probe(device);
1185 if (err)
1186 return err;
1187 ioat_set_tcp_copy_break(4096);
1188 err = ioat_register(device);
1189 if (err)
1190 return err;
Dan Williams5669e312009-09-08 17:42:56 -07001191 ioat_kobject_add(device, &ioat1_ktype);
1192
Dan Williamsf2427e22009-07-28 14:42:38 -07001193 if (dca)
1194 device->dca = ioat_dca_init(pdev, device->reg_base);
1195
Dan Williamsf2427e22009-07-28 14:42:38 -07001196 return err;
1197}
1198
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08001199void ioat_dma_remove(struct ioatdma_device *device)
Dan Aloni428ed602007-03-08 09:57:36 -08001200{
Dan Williamsbc3c7022009-07-28 14:33:42 -07001201 struct dma_device *dma = &device->common;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001202
Dan Williamse6c0b692009-09-08 17:29:44 -07001203 ioat_disable_interrupts(device);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001204
Dan Williams5669e312009-09-08 17:42:56 -07001205 ioat_kobject_del(device);
1206
Dan Williamsbc3c7022009-07-28 14:33:42 -07001207 dma_async_device_unregister(dma);
Shannon Nelsondfe22992007-10-18 03:07:13 -07001208
Chris Leech0bbd5f42006-05-23 17:35:34 -07001209 pci_pool_destroy(device->dma_pool);
1210 pci_pool_destroy(device->completion_pool);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001211
Dan Williamsdcbc8532009-07-28 14:44:50 -07001212 INIT_LIST_HEAD(&dma->channels);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001213}