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gem5 / arm / linux / f730e3dc6dc4698d55fd9bf6de33a5436900e9bd / . / drivers / video / exynos / exynos_dp_core.h
blob: 6c567bbf2fb8fcec22f4f7949916e5a515b7b573 [file] [log] [blame]
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]1/*
2 * Header file for Samsung DP (Display Port) interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef _EXYNOS_DP_CORE_H
14#define _EXYNOS_DP_CORE_H
15
Sean Paulc30ffb92012-11-01 19:13:46 +0900[diff] [blame]16enum dp_irq_type {
17 DP_IRQ_TYPE_HP_CABLE_IN,
18 DP_IRQ_TYPE_HP_CABLE_OUT,
19 DP_IRQ_TYPE_HP_CHANGE,
20 DP_IRQ_TYPE_UNKNOWN,
21};
22
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]23struct link_train {
24 int eq_loop;
25 int cr_loop[4];
26
27 u8 link_rate;
28 u8 lane_count;
29 u8 training_lane[4];
30
31 enum link_training_state lt_state;
32};
33
34struct exynos_dp_device {
35 struct device *dev;
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]36 struct clk *clock;
37 unsigned int irq;
38 void __iomem *reg_base;
Ajay Kumarc4e235c2012-10-13 05:48:00 +0900[diff] [blame]39 void __iomem *phy_addr;
40 unsigned int enable_mask;
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]41
42 struct video_info *video_info;
43 struct link_train link_train;
Sean Paul784fa9a2012-11-09 13:55:08 +0900[diff] [blame]44 struct work_struct hotplug_work;
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]45};
46
47/* exynos_dp_reg.c */
48void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
49void exynos_dp_stop_video(struct exynos_dp_device *dp);
50void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
Jingoo Han8affaf52012-04-16 09:33:12 +0900[diff] [blame]51void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]52void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
53void exynos_dp_reset(struct exynos_dp_device *dp);
Jingoo Han24db03a2012-05-25 16:21:08 +0900[diff] [blame]54void exynos_dp_swreset(struct exynos_dp_device *dp);
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]55void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
Sean Paul09d00d12012-08-07 20:54:20 -0700[diff] [blame]56enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]57void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
58void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
59 enum analog_power_block block,
60 bool enable);
61void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
62void exynos_dp_init_hpd(struct exynos_dp_device *dp);
Sean Paulc30ffb92012-11-01 19:13:46 +0900[diff] [blame]63enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
64void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]65void exynos_dp_reset_aux(struct exynos_dp_device *dp);
66void exynos_dp_init_aux(struct exynos_dp_device *dp);
67int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
68void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
69int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
70int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
71 unsigned int reg_addr,
72 unsigned char data);
73int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
74 unsigned int reg_addr,
75 unsigned char *data);
76int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
77 unsigned int reg_addr,
78 unsigned int count,
79 unsigned char data[]);
80int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
81 unsigned int reg_addr,
82 unsigned int count,
83 unsigned char data[]);
84int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
85 unsigned int device_addr,
86 unsigned int reg_addr);
87int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
88 unsigned int device_addr,
89 unsigned int reg_addr,
90 unsigned int *data);
91int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
92 unsigned int device_addr,
93 unsigned int reg_addr,
94 unsigned int count,
95 unsigned char edid[]);
96void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
97void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
98void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
99void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]100void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
101void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
102 enum pattern_set pattern);
103void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
104void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
105void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
106void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
107void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
108 u32 training_lane);
109void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
110 u32 training_lane);
111void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
112 u32 training_lane);
113void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
114 u32 training_lane);
115u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
116u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
117u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
118u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
119void exynos_dp_reset_macro(struct exynos_dp_device *dp);
Jingoo Han1ec7be92012-08-23 19:54:16 +0900[diff] [blame]120void exynos_dp_init_video(struct exynos_dp_device *dp);
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]121
Ajay Kumar3fcb6eb2012-11-09 14:05:06 +0900[diff] [blame]122void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]123int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
124void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
125 enum clock_recovery_m_value_type type,
126 u32 m_value,
127 u32 n_value);
128void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
129void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
130void exynos_dp_start_video(struct exynos_dp_device *dp);
131int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
Ajay Kumar3fcb6eb2012-11-09 14:05:06 +0900[diff] [blame]132void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]133void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
134void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
135
136/* I2C EDID Chip ID, Slave Address */
137#define I2C_EDID_DEVICE_ADDR 0x50
138#define I2C_E_EDID_DEVICE_ADDR 0x30
139
140#define EDID_BLOCK_LENGTH 0x80
141#define EDID_HEADER_PATTERN 0x00
142#define EDID_EXTENSION_FLAG 0x7e
143#define EDID_CHECKSUM 0x7f
144
145/* Definition for DPCD Register */
146#define DPCD_ADDR_DPCD_REV 0x0000
147#define DPCD_ADDR_MAX_LINK_RATE 0x0001
148#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
149#define DPCD_ADDR_LINK_BW_SET 0x0100
150#define DPCD_ADDR_LANE_COUNT_SET 0x0101
151#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
152#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
153#define DPCD_ADDR_LANE0_1_STATUS 0x0202
Jingoo Hand5c0eed2012-07-19 13:52:59 +0900[diff] [blame]154#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
Jingoo Hane9474be2012-02-03 18:01:55 +0900[diff] [blame]155#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
156#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
157#define DPCD_ADDR_TEST_REQUEST 0x0218
158#define DPCD_ADDR_TEST_RESPONSE 0x0260
159#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
160#define DPCD_ADDR_SINK_POWER_STATE 0x0600
161
162/* DPCD_ADDR_MAX_LANE_COUNT */
163#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
164#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
165
166/* DPCD_ADDR_LANE_COUNT_SET */
167#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
168#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
169
170/* DPCD_ADDR_TRAINING_PATTERN_SET */
171#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
172#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
173#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
174#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
175#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
176
177/* DPCD_ADDR_TRAINING_LANE0_SET */
178#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
179#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
180#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
181#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
182#define DPCD_MAX_SWING_REACHED (0x1 << 2)
183#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
184#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
185#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
186
187/* DPCD_ADDR_LANE0_1_STATUS */
188#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
189#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
190#define DPCD_LANE_CR_DONE (0x1 << 0)
191#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
192 DPCD_LANE_CHANNEL_EQ_DONE|\
193 DPCD_LANE_SYMBOL_LOCKED)
194
195/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
196#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
197#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
198#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
199
200/* DPCD_ADDR_TEST_REQUEST */
201#define DPCD_TEST_EDID_READ (0x1 << 2)
202
203/* DPCD_ADDR_TEST_RESPONSE */
204#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
205
206/* DPCD_ADDR_SINK_POWER_STATE */
207#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
208#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
209
210#endif /* _EXYNOS_DP_CORE_H */