website: Update learning-gem5
This is part of an effort keeping learning gem5 up-to-date
with the current release of gem5.
JIRA: https://gem5.atlassian.net/browse/GEM5-988
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I611a860f99ee476b1cbefe3cb123ae4597d5bc9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-website/+/45639
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
diff --git a/_pages/documentation/learning_gem5/part1/part1_1_building.md b/_pages/documentation/learning_gem5/part1/part1_1_building.md
index e300512..71ed950 100644
--- a/_pages/documentation/learning_gem5/part1/part1_1_building.md
+++ b/_pages/documentation/learning_gem5/part1/part1_1_building.md
@@ -81,10 +81,9 @@
sudo apt install libprotobuf-dev protobuf-compiler libgoogle-perftools-dev
```
-6. [Boost](https://www.boost.org/) (**Optional**) : The Boost library is a set
- of general purpose C++ libraries. It is a necessary dependency if you
- wish to use the SystemC implementation.
-
+6. [Boost](https://www.boost.org/) (**Optional**)
+ : The Boost library is a set of general purpose C++ libraries. It is a
+ necessary dependency if you wish to use the SystemC implementation.
```
sudo apt install libboost-all-dev
```
@@ -124,12 +123,12 @@
directory. These files specify the parameters passed to SCons when
initially building gem5. We'll use the X86 defaults and specify that we
want to compile all of the CPU models. You can look at the file
-`build_opts/X86` to see the default values for the Scons options. You
+`build_opts/X86` to see the default values for the SCons options. You
can also specify these options on the command line to override any
default.
```
-python3 scons build/X86/gem5.opt -j9
+python3 `which scons` build/X86/gem5.opt -j9
```
> **gem5 binary types**
diff --git a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
index 8f5e405..67cdce2 100644
--- a/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
+++ b/_pages/documentation/learning_gem5/part1/part1_2_simple_config.md
@@ -44,6 +44,8 @@
there. Hopefully, by the end of this section you'll have a good idea of
how simulation scripts work.
+---
+
> **An aside on SimObjects**
>
> gem5's modular design is built around the **SimObject** type. Most of
@@ -55,6 +57,9 @@
>
> See [SimObject details](http://doxygen.gem5.org/release/current/classSimObject.html#details) for more information.
+---
+
+
Creating a config file
----------------------
@@ -146,30 +151,49 @@
system.cpu.dcache_port = system.membus.cpu_side_ports
```
+---
> **An aside on gem5 ports**
>
> To connect memory system components together, gem5 uses a port
-> abstraction. Each memory object can have two kinds of ports, *master
-> ports* and *slave ports*. Requests are sent from a master port to a
-> slave port, and responses are sent from a slave port to a master port.
-> When connecting ports, you must connect a master port to a slave port.
+> abstraction. Each memory object can have two kinds of ports,
+> *request ports* and *response ports*. Requests are sent from
+> a request port to a response port, and responses are sent from
+> a response port to a request port. When connecting ports, you
+> must connect a request port to a response port.
>
> Connecting ports together is easy to do from the python configuration
-> files. You can simply set the master port `=` to the slave port and
-> they will be connected. For instance:
+> files. You can simply set the request port `=` to the response port
+> and they will be connected. For instance:
>
> ```
-> memobject1.master = memobject2.slave
+> system.cpu.icache_port = system.l1_cache.cpu_side
> ```
>
-> The master and slave can be on either side of the `=` and the same
-> connection will be made. After making the connection, the master can
-> send requests to the slave port. There is a lot of magic going on
-> behind the scenes to set up the connection, the details of which are
-> unimportant for most users.
+> In this example, the cpu's `icache_port` is a request port, and the cache's
+> `cpu_side` is a response port. The request port and the response port can be
+> on either side of the `=` and the same connection will be made. After making
+> the connection, the requestor can send requests to the responder. There is a
+> lot of magic going on behind the scenes to set up the connection, the details
+> of which are unimportant to most users.
+>
+> Another notable kind of magic of the `=` of two ports in gem5 Python
+> configuration is that, it is allowed to have one port on one side, and an
+> array of ports on the other side. For example:
+>
+> ```
+> system.cpu.icache_port = system.membus.cpu_side_ports
+> ```
+>
+> In this example, the cpu's `icache_port` is a request port, and the membus's
+> `cpu_side_ports` is an array of response ports. In this case, a new response
+> port is spawned on the `cpu_side_ports`, and this newly created port will be
+> connected to the request port.
>
> We will discuss ports and MemObject in more detail in the [MemObject chapter](http://www.gem5.org/documentation/learning_gem5/part2/memoryobject/).
+
+---
+
Next, we need to connect up a few other ports to make sure that our
system will function correctly. We need to create an I/O controller on
the CPU and connect it to the memory bus. Also, we need to connect a
@@ -244,8 +268,8 @@
```
binary = 'tests/test-progs/hello/bin/x86/linux/hello'
-#for gem5 V21 and beyond, uncomment the following line
-#system.workload = SEWorkload.init_compatible(binary)
+# for gem5 V21 and beyond, uncomment the following line
+# system.workload = SEWorkload.init_compatible(binary)
process = Process()
process.cmd = [binary]
@@ -287,13 +311,14 @@
------------
Now that we've created a simple simulation script (the full version of
-which can be found at gem5/configs/learning\_gem5/part1/simple.py) we're
-ready to run gem5. gem5 can take many parameters, but requires just one
-positional argument, the simulation script. So, we can simply run gem5
+which can be found in the gem5 code base at
+[configs/learning\_gem5/part1/simple.py](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/learning_gem5/part1/simple.py)
+) we're ready to run gem5. gem5 can take many parameters, but requires just
+one positional argument, the simulation script. So, we can simply run gem5
from the root gem5 directory as:
```
-build/X86/gem5.opt configs/tutorial/simple.py
+build/X86/gem5.opt configs/tutorial/part1/simple.py
```
The output should be:
@@ -301,18 +326,20 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
- gem5 compiled Mar 16 2018 10:24:24
- gem5 started Mar 16 2018 15:53:27
- gem5 executing on amarillo, pid 41697
- command line: build/X86/gem5.opt configs/tutorial/simple.py
+ gem5 version 21.0.0.0
+ gem5 compiled May 17 2021 18:05:59
+ gem5 started May 17 2021 22:05:20
+ gem5 executing on amarillo, pid 75197
+ command line: build/X86/gem5.opt configs/tutorial/part1/simple.py
Global frequency set at 1000000000000 ticks per second
+ warn: No dot file generated. Please install pydot to generate the dot file and pdf.
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
- 0: system.remote_gdb: listening for remote gdb on port 7000
+ 0: system.remote_gdb: listening for remote gdb on port 7005
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
Hello world!
- Exiting @ tick 507841000 because exiting with last active thread context
+ Exiting @ tick 490394000 because exiting with last active thread context
Parameters in the configuration file can be changed and the results
should be different. For instance, if you double the system clock, the
diff --git a/_pages/documentation/learning_gem5/part1/part1_3_cache_config.md b/_pages/documentation/learning_gem5/part1/part1_3_cache_config.md
index 2cc018f..ecf55bb 100644
--- a/_pages/documentation/learning_gem5/part1/part1_3_cache_config.md
+++ b/_pages/documentation/learning_gem5/part1/part1_3_cache_config.md
@@ -67,7 +67,7 @@
is a string. The string argument of each of the parameters is a
description of what the parameter is (e.g.,
`tag_latency = Param.Cycles("Tag lookup latency")` means that the
-`` `tag_latency `` controls "The hit latency for this cache").
+`` tag_latency `` controls "The hit latency for this cache").
Many of these parameters do not have defaults, so we are required to set
these parameters before calling `m5.instantiate()`.
@@ -76,8 +76,8 @@
Now, to create caches with specific parameters, we are first going to
create a new file, `caches.py`, in the same directory as simple.py,
-`configs/tutorial`. The first step is to import the SimObject(s) we are
-going to extend in this file.
+`configs/tutorial`. The first step is to import the SimObject(s)
+we are going to extend in this file.
```
from m5.objects import Cache
@@ -180,13 +180,13 @@
```
The full file can be found in the gem5 source at
-`gem5/configs/learning_gem5/part1/caches.py`.
+[`configs/learning_gem5/part1/caches.py`](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/learning_gem5/part1/caches.py).
Adding caches to the simple config file
------------------------------------
Now, let's add the caches we just created to the configuration script we
-created in the [last chapter]((http://www.gem5.org/documentation/learning_gem5/part1/simple_config/).
+created in the [last chapter](http://www.gem5.org/documentation/learning_gem5/part1/simple_config/).
First, let's copy the script to a new name.
@@ -243,15 +243,14 @@
```
system.l2cache = L2Cache()
system.l2cache.connectCPUSideBus(system.l2bus)
-
system.l2cache.connectMemSideBus(system.membus)
```
Everything else in the file stays the same! Now we have a complete
configuration with a two-level cache hierarchy. If you run the current
-file, `hello` should now finish in 58513000 ticks. The full script can
+file, `hello` should now finish in 57467000 ticks. The full script can
be found in the gem5 source at
-`gem5/configs/learning_gem5/part1/two_level.py`.
+[`configs/learning_gem5/part1/two_level.py](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/learning_gem5/part1/two_level.py).
Adding parameters to your script
--------------------------------
@@ -261,10 +260,10 @@
different parameters. To get around this, you can add command-line
parameters to your gem5 configuration script. Again, because the
configuration script is just Python, you can use the Python libraries
-that support argument parsing. Although :pyoptparse is officially
+that support argument parsing. Although pyoptparse is officially
deprecated, many of the configuration scripts that ship with gem5 use it
instead of pyargparse since gem5's minimum Python version used to be
-2.5. The minimum Python version is now 2.7, so pyargparse is a better
+2.5. The minimum Python version is now 3.6, so Python's argparse is a better
option when writing new scripts that don't need to interact with the
current gem5 scripts. To get started using :pyoptparse, you can consult
the online Python documentation.
@@ -360,19 +359,21 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
- gem5 compiled Sep 6 2015 14:17:02
- gem5 started Sep 6 2015 15:06:51
- gem5 executing on galapagos-09.cs.wisc.edu
- command line: build/X86/gem5.opt ../tutorial/_static/scripts/part1/two_level_opts.py --l2_size=1MB --l1d_size=128kB
+ gem5 version 21.0.0.0
+ gem5 compiled May 17 2021 18:05:59
+ gem5 started May 18 2021 00:00:33
+ gem5 executing on amarillo, pid 83118
+ command line: build/X86/gem5.opt configs/tutorial/two_level.py --l2_size=1MB --l1d_size=128kB
Global frequency set at 1000000000000 ticks per second
+ warn: No dot file generated. Please install pydot to generate the dot file and pdf.
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
- 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+ 0: system.remote_gdb: listening for remote gdb on port 7005
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
Hello world!
- Exiting @ tick 56742000 because target called exit()
+ Exiting @ tick 57467000 because exiting with last active thread context
The full scripts can be found in the gem5 source at
-`gem5/configs/learning_gem5/part1/caches.py` and
-`gem5/configs/learning_gem5/part1/two_level.py`.
+[`configs/learning_gem5/part1/caches.py`](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/learning_gem5/part1/caches.py) and
+[`configs/learning_gem5/part1/two_level.py`](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/learning_gem5/part1/two_level.py).
diff --git a/_pages/documentation/learning_gem5/part1/part1_4_gem5_stats.md b/_pages/documentation/learning_gem5/part1/part1_4_gem5_stats.md
index b59aa15..65e0ff6 100644
--- a/_pages/documentation/learning_gem5/part1/part1_4_gem5_stats.md
+++ b/_pages/documentation/learning_gem5/part1/part1_4_gem5_stats.md
@@ -35,7 +35,9 @@
this file.
Below is pulled from the config.ini generated when the `simple.py`
-configuration file from simple-config-chapter is run.
+configuration file from
+[simple-config-chapter](http://www.gem5.org/documentation/learning_gem5/part1/simple_config/)
+is run.
[root]
type=Root
@@ -98,10 +100,10 @@
system=system
Here we see that at the beginning of the description of each SimObject
-is first it's name as created in the configuration file surrounded by
+is first its name as created in the configuration file surrounded by
square brackets (e.g., `[system.membus]`).
-Next, every parameter of the SimObject is shown with it's value,
+Next, every parameter of the SimObject is shown with its value,
including parameters not explicitly set in the configuration file. For
instance, the configuration file sets the clock domain to be 1 GHz (1000
ticks in this case). However, it did not set the cache line size (which
@@ -128,28 +130,30 @@
execution:
---------- Begin Simulation Statistics ----------
- sim_seconds 0.000346 # Number of seconds simulated
- sim_ticks 345518000 # Number of ticks simulated
- final_tick 345518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
- sim_freq 1000000000000 # Frequency of simulated ticks
- host_inst_rate 144400 # Simulator instruction rate (inst/s)
- host_op_rate 260550 # Simulator op (including micro ops) rate (op/s)
- host_tick_rate 8718625183 # Simulator tick rate (ticks/s)
- host_mem_usage 778640 # Number of bytes of host memory used
- host_seconds 0.04 # Real time elapsed on the host
- sim_insts 5712 # Number of instructions simulated
- sim_ops 10314 # Number of ops (including micro ops) simulated
+ simSeconds 0.000057 # Number of seconds simulated (Second)
+ simTicks 57467000 # Number of ticks simulated (Tick)
+ finalTick 57467000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
+ simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
+ hostSeconds 0.03 # Real time elapsed on the host (Second)
+ hostTickRate 2295882330 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
+ hostMemory 665792 # Number of bytes of host memory used (Byte)
+ simInsts 6225 # Number of instructions simulated (Count)
+ simOps 11204 # Number of ops (including micro ops) simulated (Count)
+ hostInstRate 247382 # Simulator instruction rate (inst/s) ((Count/Second))
+ hostOpRate 445086 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
---------- Begin Simulation Statistics ----------
- sim_seconds 0.000508 # Number of seconds simulated
- sim_ticks 507841000 # Number of ticks simulated
- final_tick 507841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
- sim_freq 1000000000000 # Frequency of simulated ticks
- host_inst_rate 157744 # Simulator instruction rate (inst/s) host_op_rate 284736 # Simulator op (including micro ops) rate (op/s)
- host_tick_rate 14017997125 # Simulator tick rate (ticks/s)
- host_mem_usage 642808 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host
- sim_insts 5712 # Number of instructions simulated
- sim_ops 10313 # Number of ops (including micro ops) simulated
+ simSeconds 0.000490 # Number of seconds simulated (Second)
+ simTicks 490394000 # Number of ticks simulated (Tick)
+ finalTick 490394000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
+ simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
+ hostSeconds 0.03 # Real time elapsed on the host (Second)
+ hostTickRate 15979964060 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
+ hostMemory 657488 # Number of bytes of host memory used (Byte)
+ simInsts 6225 # Number of instructions simulated (Count)
+ simOps 11204 # Number of ops (including micro ops) simulated (Count)
+ hostInstRate 202054 # Simulator instruction rate (inst/s) ((Count/Second))
+ hostOpRate 363571 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
The statistic dump begins with
`---------- Begin Simulation Statistics ----------`. There may be
@@ -158,7 +162,8 @@
or when restoring from checkpoints.
Each statistic has a name (first column), a value (second column), and a
-description (last column preceded by \#).
+description (last column preceded by \#) followed by the unit of the
+statistic.
Most of the statistics are self explanatory from their descriptions. A
couple of important statistics are `sim_seconds` which is the total
@@ -166,80 +171,92 @@
instructions committed by the CPU, and `host_inst_rate` which tells you
the performance of gem5.
-Next, the SimObjects' statistics are printed. For instance, the memory
-controller statistics. This has information like the bytes read by each
-component and the average bandwidth used by those components.
+Next, the SimObjects' statistics are printed. For instance, the CPU
+statistics, which contains information on the number of syscalls,
+statistics for cache system and translation buffers, etc.
- system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
- system.clk_domain.clock 1000 # Clock period in ticks
- system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states
- system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory
- system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory
- system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory
- system.mem_ctrl.bytes_inst_read::cpu.inst 58264 # Number of instructions bytes read from this memory
- system.mem_ctrl.bytes_inst_read::total 58264 # Number of instructions bytes read from this memory
- system.mem_ctrl.bytes_written::cpu.data 7160 # Number of bytes written to this memory
- system.mem_ctrl.bytes_written::total 7160 # Number of bytes written to this memory
- system.mem_ctrl.num_reads::cpu.inst 7283 # Number of read requests responded to by this memory
- system.mem_ctrl.num_reads::cpu.data 1084 # Number of read requests responded to by this memory
- system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory
- system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory
- system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory
- system.mem_ctrl.bw_read::cpu.inst 114728823 # Total read bandwidth from this memory (bytes/s)
- system.mem_ctrl.bw_read::cpu.data 14112685 # Total read bandwidth from this memory (bytes/s)
- system.mem_ctrl.bw_read::total 128841507 # Total read bandwidth from this memory (bytes/s)
- system.mem_ctrl.bw_inst_read::cpu.inst 114728823 # Instruction read bandwidth from this memory (bytes/s)
- system.mem_ctrl.bw_inst_read::total 114728823 # Instruction read bandwidth from this memory (bytes/s)
- system.mem_ctrl.bw_write::cpu.data 14098901 # Write bandwidth from this memory (bytes/s)
- system.mem_ctrl.bw_write::total 14098901 # Write bandwidth from this memory (bytes/s)
- system.mem_ctrl.bw_total::cpu.inst 114728823 # Total bandwidth to/from this memory (bytes/s)
- system.mem_ctrl.bw_total::cpu.data 28211586 # Total bandwidth to/from this memory (bytes/s)
- system.mem_ctrl.bw_total::total 142940409 # Total bandwidth to/from this memory (bytes/s)
+ system.clk_domain.clock 1000 # Clock period in ticks (Tick)
+ system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
+ system.cpu.numCycles 57467 # Number of cpu cycles simulated (Cycle)
+ system.cpu.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
+ system.cpu.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
+ system.cpu.dcache.demandHits::cpu.data 1941 # number of demand (read+write) hits (Count)
+ system.cpu.dcache.demandHits::total 1941 # number of demand (read+write) hits (Count)
+ system.cpu.dcache.overallHits::cpu.data 1941 # number of overall hits (Count)
+ system.cpu.dcache.overallHits::total 1941 # number of overall hits (Count)
+ system.cpu.dcache.demandMisses::cpu.data 133 # number of demand (read+write) misses (Count)
+ system.cpu.dcache.demandMisses::total 133 # number of demand (read+write) misses (Count)
+ system.cpu.dcache.overallMisses::cpu.data 133 # number of overall misses (Count)
+ system.cpu.dcache.overallMisses::total 133 # number of overall misses (Count)
+ system.cpu.dcache.demandMissLatency::cpu.data 14301000 # number of demand (read+write) miss ticks (Tick)
+ system.cpu.dcache.demandMissLatency::total 14301000 # number of demand (read+write) miss ticks (Tick)
+ system.cpu.dcache.overallMissLatency::cpu.data 14301000 # number of overall miss ticks (Tick)
+ system.cpu.dcache.overallMissLatency::total 14301000 # number of overall miss ticks (Tick)
+ system.cpu.dcache.demandAccesses::cpu.data 2074 # number of demand (read+write) accesses (Count)
+ system.cpu.dcache.demandAccesses::total 2074 # number of demand (read+write) accesses (Count)
+ system.cpu.dcache.overallAccesses::cpu.data 2074 # number of overall (read+write) accesses (Count)
+ system.cpu.dcache.overallAccesses::total 2074 # number of overall (read+write) accesses (Count)
+ system.cpu.dcache.demandMissRate::cpu.data 0.064127 # miss rate for demand accesses (Ratio)
+ system.cpu.dcache.demandMissRate::total 0.064127 # miss rate for demand accesses (Ratio)
+ system.cpu.dcache.overallMissRate::cpu.data 0.064127 # miss rate for overall accesses (Ratio)
+ system.cpu.dcache.overallMissRate::total 0.064127 # miss rate for overall accesses (Ratio)
+ system.cpu.dcache.demandAvgMissLatency::cpu.data 107526.315789 # average overall miss latency ((Cycle/Count))
+ system.cpu.dcache.demandAvgMissLatency::total 107526.315789 # average overall miss latency ((Cycle/Count))
+ system.cpu.dcache.overallAvgMissLatency::cpu.data 107526.315789 # average overall miss latency ((Cycle/Count))
+ system.cpu.dcache.overallAvgMissLatency::total 107526.315789 # average overall miss latency ((Cycle/Count))
+ ...
+ system.cpu.mmu.dtb.rdAccesses 1123 # TLB accesses on read requests (Count)
+ system.cpu.mmu.dtb.wrAccesses 953 # TLB accesses on write requests (Count)
+ system.cpu.mmu.dtb.rdMisses 11 # TLB misses on read requests (Count)
+ system.cpu.mmu.dtb.wrMisses 9 # TLB misses on write requests (Count)
+ system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 57467000 # Cumulative time (in ticks) in various power states (Tick)
+ system.cpu.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
+ system.cpu.mmu.itb.wrAccesses 7940 # TLB accesses on write requests (Count)
+ system.cpu.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
+ system.cpu.mmu.itb.wrMisses 37 # TLB misses on write requests (Count)
+ system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 57467000 # Cumulative time (in ticks) in various power states (Tick)
+ system.cpu.power_state.pwrStateResidencyTicks::ON 57467000 # Cumulative time (in ticks) in various power states (Tick)
+ system.cpu.thread_0.numInsts 0 # Number of Instructions committed (Count)
+ system.cpu.thread_0.numOps 0 # Number of Ops committed (Count)
+ system.cpu.thread_0.numMemRefs 0 # Number of Memory References (Count)
+ system.cpu.workload.numSyscalls 11 # Number of system calls (Count)
-Later in the file is the CPU statistics, which contains information on
-the number of syscalls, the number of branches, total committed
-instructions, etc.
+Later in the file is memory controller statistics. This has information like
+the bytes read by each component and the average bandwidth used by those
+components.
- system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states
- system.cpu.dtb.rdAccesses 1084 # TLB accesses on read requests
- system.cpu.dtb.wrAccesses 941 # TLB accesses on write requests
- system.cpu.dtb.rdMisses 9 # TLB misses on read requests
- system.cpu.dtb.wrMisses 7 # TLB misses on write requests
- system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks
- system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states
- system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states
- system.cpu.itb.rdAccesses 0 # TLB accesses on read requests
- system.cpu.itb.wrAccesses 7284 # TLB accesses on write requests
- system.cpu.itb.rdMisses 0 # TLB misses on read requests
- system.cpu.itb.wrMisses 31 # TLB misses on write requests
- system.cpu.workload.numSyscalls 11 # Number of system calls
- system.cpu.pwrStateResidencyTicks::ON 507841000 # Cumulative time (in ticks) in various power states
- system.cpu.numCycles 507841 # number of cpu cycles simulated
- system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
- system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
- system.cpu.committedInsts 5712 # Number of instructions committed
- system.cpu.committedOps 10313 # Number of ops (including micro ops) committed
- system.cpu.num_int_alu_accesses 10204 # Number of integer alu accesses
- system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
- system.cpu.num_vec_alu_accesses 0 # Number of vector alu accesses
- system.cpu.num_func_calls 221 # number of times a function call or return occured
- system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls
- system.cpu.num_int_insts 10204 # number of integer instructions
- system.cpu.num_fp_insts 0 # number of float instructions
- system.cpu.num_vec_insts 0 # number of vector instructions
- system.cpu.num_int_register_reads 19293 # number of times the integer registers were read
- system.cpu.num_int_register_writes 7976 # number of times the integer registers were written
- system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
- system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
- system.cpu.num_vec_register_reads 0 # number of times the vector registers were read
- system.cpu.num_vec_register_writes 0 # number of times the vector registers were written
- system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read
- system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written
- system.cpu.num_mem_refs 2025 # number of memory refs
- system.cpu.num_load_insts 1084 # Number of load instructions
- system.cpu.num_store_insts 941 # Number of store instructions
- system.cpu.num_idle_cycles 0 # Number of idle cycles
- system.cpu.num_busy_cycles 507841 # Number of busy cycles
- system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
- system.cpu.idle_fraction 0 # Percentage of idle cycles
- system.cpu.Branches 1306 # Number of branches fetched
+ system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
+ system.mem_ctrl.bytesReadSys 23168 # Total read bytes from the system interface side (Byte)
+ system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
+ system.mem_ctrl.avgRdBWSys 403153113.96105593 # Average system read bandwidth in Byte/s ((Byte/Second))
+ system.mem_ctrl.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
+ system.mem_ctrl.totGap 57336000 # Total gap between requests (Tick)
+ system.mem_ctrl.avgGap 158386.74 # Average gap between requests ((Tick/Count))
+ system.mem_ctrl.requestorReadBytes::cpu.inst 14656 # Per-requestor bytes read from memory (Byte)
+ system.mem_ctrl.requestorReadBytes::cpu.data 8512 # Per-requestor bytes read from memory (Byte)
+ system.mem_ctrl.requestorReadRate::cpu.inst 255033323.472601681948 # Per-requestor bytes read from memory rate ((Byte/Second))
+ system.mem_ctrl.requestorReadRate::cpu.data 148119790.488454252481 # Per-requestor bytes read from memory rate ((Byte/Second))
+ system.mem_ctrl.requestorReadAccesses::cpu.inst 229 # Per-requestor read serviced memory accesses (Count)
+ system.mem_ctrl.requestorReadAccesses::cpu.data 133 # Per-requestor read serviced memory accesses (Count)
+ system.mem_ctrl.requestorReadTotalLat::cpu.inst 6234000 # Per-requestor read total memory access latency (Tick)
+ system.mem_ctrl.requestorReadTotalLat::cpu.data 4141000 # Per-requestor read total memory access latency (Tick)
+ system.mem_ctrl.requestorReadAvgLat::cpu.inst 27222.71 # Per-requestor read average memory access latency ((Tick/Count))
+ system.mem_ctrl.requestorReadAvgLat::cpu.data 31135.34 # Per-requestor read average memory access latency ((Tick/Count))
+ system.mem_ctrl.dram.bytesRead::cpu.inst 14656 # Number of bytes read from this memory (Byte)
+ system.mem_ctrl.dram.bytesRead::cpu.data 8512 # Number of bytes read from this memory (Byte)
+ system.mem_ctrl.dram.bytesRead::total 23168 # Number of bytes read from this memory (Byte)
+ system.mem_ctrl.dram.bytesInstRead::cpu.inst 14656 # Number of instructions bytes read from this memory (Byte)
+ system.mem_ctrl.dram.bytesInstRead::total 14656 # Number of instructions bytes read from this memory (Byte)
+ system.mem_ctrl.dram.numReads::cpu.inst 229 # Number of read requests responded to by this memory (Count)
+ system.mem_ctrl.dram.numReads::cpu.data 133 # Number of read requests responded to by this memory (Count)
+ system.mem_ctrl.dram.numReads::total 362 # Number of read requests responded to by this memory (Count)
+ system.mem_ctrl.dram.bwRead::cpu.inst 255033323 # Total read bandwidth from this memory ((Byte/Second))
+ system.mem_ctrl.dram.bwRead::cpu.data 148119790 # Total read bandwidth from this memory ((Byte/Second))
+ system.mem_ctrl.dram.bwRead::total 403153114 # Total read bandwidth from this memory ((Byte/Second))
+ system.mem_ctrl.dram.bwInstRead::cpu.inst 255033323 # Instruction read bandwidth from this memory ((Byte/Second))
+ system.mem_ctrl.dram.bwInstRead::total 255033323 # Instruction read bandwidth from this memory ((Byte/Second))
+ system.mem_ctrl.dram.bwTotal::cpu.inst 255033323 # Total bandwidth to/from this memory ((Byte/Second))
+ system.mem_ctrl.dram.bwTotal::cpu.data 148119790 # Total bandwidth to/from this memory ((Byte/Second))
+ system.mem_ctrl.dram.bwTotal::total 403153114 # Total bandwidth to/from this memory ((Byte/Second))
+ system.mem_ctrl.dram.readBursts 362 # Number of DRAM read bursts (Count)
+ system.mem_ctrl.dram.writeBursts 0 # Number of DRAM write bursts (Count)
diff --git a/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md b/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md
index d706670..fa48250 100644
--- a/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md
+++ b/_pages/documentation/learning_gem5/part1/part1_5_gem5_example_configs.md
@@ -34,30 +34,40 @@
directory structure is shown below:
configs/boot:
- ammp.rcS halt.sh micro_tlblat2.rcS netperf-stream-udp-local.rcS
- ...
+ bbench-gb.rcS bbench-ics.rcS hack_back_ckpt.rcS halt.sh
configs/common:
- Benchmarks.py cpu2000.py Options.py
- Caches.py FSConfig.py O3_ARM_v7a.py SysPaths.py
- CacheConfig.py CpuConfig.py MemConfig.py Simulation.py
+ Benchmarks.py Caches.py cpu2000.py FileSystemConfig.py GPUTLBConfig.py HMC.py MemConfig.py Options.py Simulation.py
+ CacheConfig.py cores CpuConfig.py FSConfig.py GPUTLBOptions.py __init__.py ObjectList.py SimpleOpts.py SysPaths.py
+
+ configs/dist:
+ sw.py
configs/dram:
- sweep.py
+ lat_mem_rd.py low_power_sweep.py sweep.py
configs/example:
- fs.py read_config.py ruby_mem_test.py ruby_random_test.py
- memtest.py ruby_direct_test.py ruby_network_test.py se.py
+ apu_se.py etrace_replay.py garnet_synth_traffic.py hmctest.py hsaTopology.py memtest.py read_config.py ruby_direct_test.py ruby_mem_test.py sc_main.py
+ arm fs.py hmc_hello.py hmc_tgen.cfg memcheck.py noc_config riscv ruby_gpu_random_test.py ruby_random_test.py se.py
+
+ configs/learning_gem5:
+ part1 part2 part3 README
+
+ configs/network:
+ __init__.py Network.py
+
+ configs/nvm:
+ sweep_hybrid.py sweep.py
configs/ruby:
- MESI_Three_Level.py MI_example.py MOESI_CMP_token.py Network_test.py
- MESI_Two_Level.py MOESI_CMP_directory.py MOESI_hammer.py Ruby.py
+ AMD_Base_Constructor.py CHI.py Garnet_standalone.py __init__.py MESI_Three_Level.py MI_example.py MOESI_CMP_directory.py MOESI_hammer.py
+ CHI_config.py CntrlBase.py GPU_VIPER.py MESI_Three_Level_HTM.py MESI_Two_Level.py MOESI_AMD_Base.py MOESI_CMP_token.py Ruby.py
configs/splash2:
cluster.py run.py
configs/topologies:
- BaseTopology.py Cluster.py Crossbar.py MeshDirCorners.py Mesh.py Pt2Pt.py Torus.py
+ BaseTopology.py Cluster.py CrossbarGarnet.py Crossbar.py CustomMesh.py __init__.py MeshDirCorners_XY.py Mesh_westfirst.py Mesh_XY.py Pt2Pt.py
Each directory is briefly described below:
@@ -107,6 +117,17 @@
next section. There are also some other utility configuration
scripts in this directory.
+**learning_gem5/**
+: This directory contains all gem5 configuration scripts found in the
+ learning\_gem5 book.
+
+**network/**
+: This directory contains the configurations scripts for a HeteroGarnet
+ network.
+
+**nvm/**
+: This directory contains example scripts using the NVM interface.
+
**ruby/**
: This directory contains the configurations scripts for Ruby and its
included cache coherence protocols. More details can be found in the
@@ -145,32 +166,34 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
- gem5 compiled Jan 14 2015 16:11:34
- gem5 started Feb 2 2015 15:22:24
- gem5 executing on mustardseed.cs.wisc.edu
+ gem5 version 21.0.0.0
+ gem5 compiled May 17 2021 18:05:59
+ gem5 started May 18 2021 00:33:42
+ gem5 executing on amarillo, pid 85168
command line: build/X86/gem5.opt configs/example/se.py --cmd=tests/test-progs/hello/bin/x86/linux/hello
+
Global frequency set at 1000000000000 ticks per second
+ warn: No dot file generated. Please install pydot to generate the dot file and pdf.
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
- 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+ 0: system.remote_gdb: listening for remote gdb on port 7005
**** REAL SIMULATION ****
info: Entering event queue @ 0. Starting simulation...
Hello world!
- Exiting @ tick 5942000 because target called exit()
+ Exiting @ tick 5943000 because exiting with last active thread context
However, this isn't a very interesting simulation at all! By default,
gem5 uses the atomic CPU and uses atomic memory accesses, so there's no
real timing data reported! To confirm this, you can look at
-m5out/config.ini. The CPU is shown on line 46:
+m5out/config.ini. The CPU is shown on line 51:
[system.cpu]
type=AtomicSimpleCPU
- children=apic_clk_domain dtb interrupts isa itb tracer workload
+ children=interrupts isa mmu power_state tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
- do_quiesce=true
do_statistics_insts=true
To actually run gem5 in timing mode, let's specify a CPU type. While
@@ -183,17 +206,20 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
- gem5 compiled Jan 14 2015 16:11:34
- gem5 started Feb 2 2015 15:26:57
- gem5 executing on mustardseed.cs.wisc.edu
+ gem5 version 21.0.0.0
+ gem5 compiled May 17 2021 18:05:59
+ gem5 started May 18 2021 00:36:10
+ gem5 executing on amarillo, pid 85269
command line: build/X86/gem5.opt configs/example/se.py --cmd=tests/test-progs/hello/bin/x86/linux/hello --cpu-type=TimingSimpleCPU --l1d_size=64kB --l1i_size=16kB
+
Global frequency set at 1000000000000 ticks per second
+ warn: No dot file generated. Please install pydot to generate the dot file and pdf.
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
- 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+ 0: system.remote_gdb: listening for remote gdb on port 7005
**** REAL SIMULATION ****
info: Entering event queue @ 0. Starting simulation...
Hello world!
- Exiting @ tick 344986500 because target called exit()
+ Exiting @ tick 454646000 because exiting with last active thread context
Now, let's check the config.ini file and make sure that these options
propagated correctly to the final system. If you search
@@ -209,47 +235,59 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
- gem5 compiled Jan 14 2015 16:11:34
- gem5 started Feb 2 2015 15:29:20
- gem5 executing on mustardseed.cs.wisc.edu
+ gem5 version 21.0.0.0
+ gem5 compiled May 17 2021 18:05:59
+ gem5 started May 18 2021 00:37:03
+ gem5 executing on amarillo, pid 85560
command line: build/X86/gem5.opt configs/example/se.py --cmd=tests/test-progs/hello/bin/x86/linux/hello --cpu-type=TimingSimpleCPU --l1d_size=64kB --l1i_size=16kB --caches
+
Global frequency set at 1000000000000 ticks per second
+ warn: No dot file generated. Please install pydot to generate the dot file and pdf.
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
- 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+ 0: system.remote_gdb: listening for remote gdb on port 7005
**** REAL SIMULATION ****
info: Entering event queue @ 0. Starting simulation...
Hello world!
- Exiting @ tick 29480500 because target called exit()
+ Exiting @ tick 31680000 because exiting with last active thread context
-On the last line, we see that the total time went from 344986500 ticks
-to 29480500, much faster! Looks like caches are probably enabled now.
+On the last line, we see that the total time went from 454646000 ticks
+to 31680000, much faster! Looks like caches are probably enabled now.
But, it's always a good idea to double check the `config.ini` file.
[system.cpu.dcache]
- type=BaseCache
- children=tags
+ type=Cache
+ children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+ clusivity=mostly_incl
+ compressor=Null
+ data_latency=2
demand_mshr_reserve=1
eventq_index=0
- forward_snoops=true
- hit_latency=2
- is_top_level=true
+ is_read_only=false
max_miss_count=0
+ move_contractions=true
mshrs=4
+ power_model=
+ power_state=system.cpu.dcache.power_state
prefetch_on_access=false
prefetcher=Null
+ replace_expansions=true
+ replacement_policy=system.cpu.dcache.replacement_policy
response_latency=2
sequential_access=false
size=65536
system=system
+ tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
- two_queue=false
+ warmup_percentage=0
+ write_allocator=Null
write_buffers=8
+ writeback_clean=false
cpu_side=system.cpu.dcache_port
- mem_side=system.membus.slave[2]
+ mem_side=system.membus.cpu_side_ports[2]
Some common options `se.py` and `fs.py`
---------------------------------------
diff --git a/_pages/documentation/learning_gem5/part2/part2_1_helloobject.md b/_pages/documentation/learning_gem5/part2/part2_1_helloobject.md
index f19c761..9b4e3e4 100644
--- a/_pages/documentation/learning_gem5/part2/part2_1_helloobject.md
+++ b/_pages/documentation/learning_gem5/part2/part2_1_helloobject.md
@@ -11,6 +11,9 @@
Creating a *very* simple SimObject
==================================
+**Note**: gem5 has SimObject named `SimpleObject`. Implementing another
+`SimpleObject` SimObject will result in confusing compiler issues.
+
Almost all objects in gem5 inherit from the base SimObject type.
SimObjects export the main interfaces to all objects in gem5. SimObjects
are wrapped `C++` objects that are accessible from the `Python`
@@ -39,7 +42,7 @@
>
> The first step when adding a new feature or modifying something in
> gem5, is to create a new branch to store your changes. Details on git
-> branches can be found in the Git book\_.
+> branches can be found in the Git book.
>
> ```
> git checkout -b hello-simobject
@@ -55,7 +58,11 @@
simply need to declare a new class for our SimObject and set it's name
and the C++ header that will define the C++ class for the SimObject.
-We can create a file, HelloObject.py, in `src/learning_gem5/part2`. If you have cloned the gem5 repository you'll have the files mentioned in this tutorial completed under `src/learning_gem5/part2` and `configs/learning_gem5/part2`. You can delete these or move them elsewhere to follow this tutorial.
+We can create a file, `HelloObject.py`, in `src/learning_gem5/part2`.
+If you have cloned the gem5 repository you'll have the files mentioned
+in this tutorial completed under `src/learning_gem5/part2` and
+`configs/learning_gem5/part2`. You can delete these or move them
+elsewhere to follow this tutorial.
```python
from m5.params import *
@@ -82,7 +89,8 @@
Step 2: Implement your SimObject in C++
---------------------------------------
-Next, we need to create `hello_object.hh` and `hello_object.cc` in `src/learning_gem5/part2/` directory which will implement the `HelloObject`.
+Next, we need to create `hello_object.hh` and `hello_object.cc` in
+`src/learning_gem5/part2/` directory which will implement the `HelloObject`.
We'll start with the header file for our `C++` object. By convention,
gem5 wraps all header files in `#ifndef/#endif` with the name of the
@@ -116,7 +124,7 @@
class HelloObject : public SimObject
{
public:
- HelloObject(HelloObjectParams *p);
+ HelloObject(const HelloObjectParams &p);
};
#endif // __LEARNING_GEM5_HELLO_OBJECT_HH__
@@ -140,43 +148,31 @@
#include <iostream>
-HelloObject::HelloObject(HelloObjectParams *params) :
+HelloObject::HelloObject(const HelloObjectParams ¶ms) :
SimObject(params)
{
std::cout << "Hello World! From a SimObject!" << std::endl;
}
```
-There is another function that we have to implement as well for the
-SimObject to be complete. We must implement one function for the
-parameter type that is implicitly created from the SimObject `Python`
-declaration, namely, the `create` function. This function simply returns
-a new instantiation of the SimObject. Usually this function is very
-simple (as below).
+**Note**: If the constructor of your SimObject follows the following
+signature,
```cpp
-HelloObject*
-HelloObjectParams::create()
-{
- return new HelloObject(this);
-}
+Foo(const FooParams &)
```
+then a `FooParams::create()` method will be automatically defined. The purpose
+of the `create()` method is to call the SimObject constructor and return an
+instance of the SimObject. Most SimObject will follow this pattern; however,
+if your SimObject does not follow this pattern,
+[the gem5 SimObject documetation](http://doxygen.gem5.org/release/current/classSimObject.html#details)
+provides more information about manually implementing the `create()` method.
+
+
[//]: # You can find the complete file
[//]: # [here](/_pages/static/scripts/part2/helloobject/hello_object.cc).
-If you forget to add the create function for your SimObject, you will
-get a linker error when you compile. It will look something like the
-following.
-
- build/X86/python/m5/internal/param_HelloObject_wrap.o: In function `_wrap_HelloObjectParams_create':
- /local.chinook/gem5/gem5-tutorial/gem5/build/X86/python/m5/internal/param_HelloObject_wrap.cc:3096: undefined reference to `HelloObjectParams::create()'
- collect2: error: ld returned 1 exit status
- scons: *** [build/X86/gem5.opt] Error 1
- scons: building terminated because of errors.
-
-This `` undefined reference to `HelloObjectParams::create()' `` means
-you need to implement the create function for your SimObject.
Step 3: Register the SimObject and C++ file
-------------------------------------------
@@ -227,7 +223,11 @@
-----------------------------------------------------------
Now that you have implemented a SimObject, and it has been compiled into
-gem5, you need to create or modify a `Python` config file `run_hello.py` in `configs/learning_gem5/part2` to instantiate your object. Since your object is very simple a system object is not required! CPUs are not needed, or caches, or anything, except a `Root` object. All gem5 instances require a `Root` object.
+gem5, you need to create or modify a `Python` config file `run_hello.py` in
+`configs/learning_gem5/part2` to instantiate your object. Since your object
+is very simple a system object is not required! CPUs are not needed, or
+caches, or anything, except a `Root` object. All gem5 instances require a
+`Root` object.
Walking through creating a *very* simple configuration script, first,
import m5 and all of the objects you have compiled.
@@ -270,10 +270,15 @@
[//]: # You can find the complete file
[//]: # [here](/_pages/static/scripts/part2/helloobject/run_hello.py).
-Remember to rebuild gem5 after modifying files in the src/ directory. The command line to run the config file is in the output below after 'command line:'.
-The output should look something like the following:
+Remember to rebuild gem5 after modifying files in the src/ directory. The
+command line to run the config file is in the output below after
+'command line:'. The output should look something like the following:
-Note: If the code for the future section "Adding parameters to SimObjects and more events", (goodbye_object) is in your src/learning_gem5/part2 directory, run_hello.py will cause an error. If you delete those files or move them outside of the gem5 directory `run_hello.py` should give the output below.
+Note: If the code for the future section "Adding parameters to SimObjects
+and more events", (goodbye_object) is in your `src/learning_gem5/part2`
+directory, run_hello.py will cause an error. If you delete those files or
+move them outside of the gem5 directory `run_hello.py` should give the output
+below.
```
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
diff --git a/_pages/documentation/learning_gem5/part2/part2_2_debugging.md b/_pages/documentation/learning_gem5/part2/part2_2_debugging.md
index 1024399..28aad86 100644
--- a/_pages/documentation/learning_gem5/part2/part2_2_debugging.md
+++ b/_pages/documentation/learning_gem5/part2/part2_2_debugging.md
@@ -29,7 +29,7 @@
following output. Note that this generates *a lot* of output to the
console (about 7 MB).
-```sh
+```
build/X86/gem5.opt --debug-flags=DRAM configs/learning_gem5/part1/simple.py | head -n 50
```
@@ -90,7 +90,7 @@
flags shows details of how each instruction is executed by the simulated
CPU.
-```sh
+```
build/X86/gem5.opt --debug-flags=Exec configs/learning_gem5/part1/simple.py | head -n 50
```
@@ -151,40 +151,42 @@
flags. You can see this, and all of the available debug flags, by
running gem5 with the `--debug-help` parameter.
-```sh
+```
build/X86/gem5.opt --debug-help
```
Base Flags:
- Activity: None
- AddrRanges: None
- Annotate: State machine annotation debugging
- AnnotateQ: State machine annotation queue debugging
- AnnotateVerbose: Dump all state machine annotation details
- BaseXBar: None
- Branch: None
- Bridge: None
- CCRegs: None
- CMOS: Accesses to CMOS devices
- Cache: None
- CachePort: None
- CacheRepl: None
- CacheTags: None
- CacheVerbose: None
- Checker: None
- Checkpoint: None
- ClockDomain: None
+ Activity: None
+ AddrRanges: None
+ Annotate: State machine annotation debugging
+ AnnotateQ: State machine annotation queue debugging
+ AnnotateVerbose: Dump all state machine annotation details
+ BaseXBar: None
+ Branch: None
+ Bridge: None
+ CCRegs: None
+ CMOS: Accesses to CMOS devices
+ Cache: None
+ CacheComp: None
+ CachePort: None
+ CacheRepl: None
+ CacheTags: None
+ CacheVerbose: None
+ Checker: None
+ Checkpoint: None
+ ClockDomain: None
...
Compound Flags:
- AnnotateAll: All Annotation flags
- Annotate, AnnotateQ, AnnotateVerbose
- CacheAll: None
- Cache, CachePort, CacheRepl, CacheVerbose, HWPrefetch
- DiskImageAll: None
- DiskImageRead, DiskImageWrite
+ All: Controls all debug flags. It should not be used within C++ code.
+ All Base Flags
+ AnnotateAll: All Annotation flags
+ Annotate, AnnotateQ, AnnotateVerbose
+ CacheAll: None
+ Cache, CacheComp, CachePort, CacheRepl, CacheVerbose, HWPrefetch
+ DiskImageAll: None
+ DiskImageRead, DiskImageWrite
...
XBar: None
- BaseXBar, CoherentXBar, NoncoherentXBar, SnoopFilter XBar: None
BaseXBar, CoherentXBar, NoncoherentXBar, SnoopFilter
Adding a new debug flag
@@ -200,10 +202,10 @@
directory with your hello object code (src/learning\_gem5/).
```python
-DebugFlag('Hello')
+DebugFlag('HelloExample')
```
-This declares a debug flag of "Hello". Now, we can use this in debug
+This declares a debug flag of "HelloExample". Now, we can use this in debug
statements in our SimObject.
By declaring the flag in the SConscript file, a debug header is
@@ -216,14 +218,14 @@
In the `hello_object.cc` file, we need to include the header file.
```cpp
-#include "debug/Hello.hh"
+#include "debug/HelloExample.hh"
```
Now that we have included the necessary header file, let's replace the
`std::cout` call with a debug statement like so.
```cpp
-DPRINTF(Hello, "Created the hello object\n");
+DPRINTF(HelloExample, "Created the hello object\n");
```
`DPRINTF` is a C++ macro. The first parameter is a *debug flag* that has
@@ -235,7 +237,7 @@
Now, if you recompile gem5 and run it with the "Hello" debug flag, you
get the following result.
-```sh
+```
build/X86/gem5.opt --debug-flags=Hello configs/learning_gem5/part2/run_hello.py
```
@@ -254,9 +256,9 @@
Exiting @ tick 18446744073709551615 because simulate() limit reached
You can find the updated SConcript file
-[here](/_pages/static/scripts/part2/debugging/SConscript) and the updated
-hello object code
-[here](/_pages/static/scripts/part2/debugging/hello_object.cc).
+[here](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/learning_gem5/part2/SConscript)
+and the updated hello object code
+[here](https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/learning_gem5/part2/hello_object.cc).
Debug output
------------
diff --git a/_pages/documentation/learning_gem5/part2/part2_3_events.md b/_pages/documentation/learning_gem5/part2/part2_3_events.md
index 58b418b..d7081f2 100644
--- a/_pages/documentation/learning_gem5/part2/part2_3_events.md
+++ b/_pages/documentation/learning_gem5/part2/part2_3_events.md
@@ -13,7 +13,7 @@
gem5 is an event-driven simulator. In this chapter, we will explore how
to create and schedule events. We will be building from the simple
-`HelloObject` from hello-simobject-chapter.
+`HelloObject` from [hello-simobject-chapter](../helloobject).
Creating a simple event callback
--------------------------------
@@ -143,12 +143,12 @@
EventFunctionWrapper event;
- Tick latency;
+ const Tick latency;
int timesLeft;
public:
- HelloObject(HelloObjectParams *p);
+ HelloObject(const HelloObjectParams &p);
void startup();
};
@@ -162,7 +162,7 @@
SimObject(params), event([this]{processEvent();}, name()),
latency(100), timesLeft(10)
{
- DPRINTF(Hello, "Created the hello object\n");
+ DPRINTF(HelloExample, "Created the hello object\n");
}
```
@@ -179,10 +179,10 @@
HelloObject::processEvent()
{
timesLeft--;
- DPRINTF(Hello, "Hello world! Processing the event! %d left\n", timesLeft);
+ DPRINTF(HelloExample, "Hello world! Processing the event! %d left\n", timesLeft);
if (timesLeft <= 0) {
- DPRINTF(Hello, "Done firing!\n");
+ DPRINTF(HelloExample, "Done firing!\n");
} else {
schedule(event, curTick() + latency);
}
