website: Update ARM Implementation page
The older version was providing stale data
JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-244
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3597cc7340672f28a2e836d7f860d143b98eda2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-website/+/26883
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/_pages/documentation/general_docs/architecture_support/arm_implementation.md b/_pages/documentation/general_docs/architecture_support/arm_implementation.md
index 8fc2e5f..5034ec5 100644
--- a/_pages/documentation/general_docs/architecture_support/arm_implementation.md
+++ b/_pages/documentation/general_docs/architecture_support/arm_implementation.md
@@ -8,44 +8,25 @@
# ARM Implementation
-{: .outdated-notice}
-The information and hyperlinks in this page may not be accurate.
-
## Supported features and modes
-The ARM Architecture models within gem5 support an [ARMv8-A](https://developer.arm.com/docs/den0024/latest/armv8-a-architecture-and-processors/armv8-a) profile of the ARM® architecture with multi-processor extensions.
-This includes both AArch32 and AArch64 state.
-In AArch32, this include support for [Thumb®](https://www.embedded.com/introduction-to-arm-thumb/), Thumb-2, VFPv3 (32 double register variant) and [NEON™](https://developer.arm.com/architectures/instruction-sets/simd-isas/neon), and Large Physical Address Extensions (LPAE).
-Optional features of the architecture that are not currently supported are [TrustZone®](https://developer.arm.com/ip-products/security-ip/trustzone), ThumbEE, [Jazelle®](https://en.wikipedia.org/wiki/Jazelle), and [Virtualization](https://developer.arm.com/docs/100942/0100/aarch64-virtualization).
+The ARM Architecture models within gem5 support an [ARMv8.0-A](https://developer.arm.com/docs/den0024/latest/armv8-a-architecture-and-processors/armv8-a) profile of the ARM® architecture with multi-processor extensions.
+This includes both AArch32 and AArch64 state at all ELs. This basically means supporting:
-## Pertinent Non-supported Features
+* [EL2: Virtualization](https://developer.arm.com/docs/100942/0100/aarch64-virtualization)
+* [EL3: TrustZone®](https://developer.arm.com/ip-products/security-ip/trustzone)
-Currently in ARMv8-A implementation in gem5, there isn't support for interworking between AArch32 and AArch64 execution.
-This limits the ability to run some OSes that expect to execute both 32-bit and 64-bit code, but is expected to be fixed in the short term.
-Additionally, there has been limited testing of EL2 and EL3 modes in the implementation.
+The baseline model is ARMv8.0 compliant, we also support some mandatory/optional ARMv8.x features (with x > 0)
+While the best way to get a synced version of Arm architectural features is to have a look at Arm ID registers:
+* [src/arch/arm/ArmISA.py](https://github.com/gem5/gem5/blob/master/src/arch/arm/ArmISA.py)
+* [src/arch/arm/ArmSystem.py](https://github.com/gem5/gem5/blob/master/src/arch/arm/ArmSystem.py)
-## Conditional Execution Support
+Here you will find a summary of some (but not all) notable`architectural extensions supported in gem5:
-Many instructions within the ARM architecture are predicated.
-To handle the predication within the gem5 framework and not have to generate N varieties of each instruction for every condition code, the instructions constructors determine which, if any, conditional execution flags are set and then conditionally read the condition codes or a "zero register" which is always available and doesn't insert any dependencies in the dynamic execution of instructions.
-
-## Special PC management
-
-The PCState object used for ARM® encodes additional execution state information so facilitate the use of the generic gem5 CPU components.
-In addition to the standard program counter, the Thumb® vs.
-ARM® instruction state is included as well as the ITSTATE (predication within Thumb® instructions).
-
-## Boot loader
-
-A simple bootloader for ARM is in the source tree under `system/arm/`.
-Two boot loaders exist, one for AArch64 (`aarch64_bootloader`) and another for AArch32 (`simple_bootloader`).
-
-For the AArch64 bootloader: The initial conditions of the boot loader are the same as those for Linux, `r0 = device tree blob address; r6 = kernel start address`.
-The boot loader starts the kernel with CPU 0 and places the other CPUs in a WFE spin-loop until the kernel starts them later.
-
-For the AArch32 boot loader: The initial conditions of the bootloader running are the same as those ffor Linux, `r0 = 0; r1 = machine number; r2 = atags ptr;` and some special registers for the boot loader to use `r3 = start address of kernel; r4 = address of GIC; r5 = adderss of flags register`.
-The bootloader works by reading the MPIDR register to determine the CPU number.
-CPU0 jumps immediately to the kernel while CPUn enables their interrupt interface and and wait for an interrupt.
-When CPU0 generates an IPI, CPUn reads the flags register until it is non-zero and then jumps to that address.
+* ARMv8.1-LSE, Armv8.1 Large System Extensions
+* ARMv8.1-PAN, Privileged access never
+* ARMv8.2-SVE, Scalable Vector Extension
+* ARMv8.3-JSConv, Javascript conversion instructions
+* ARMv8.3-PAuth, Pointer Authentication
