website: fix links and markup of publications (2009)
Signed-off-by: Masanori Ogino <masanori.ogino@gmail.com>
Change-Id: If18e42da67007feca70e61904ddc6a1d7e6ea9b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-website/+/56023
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby Bruce <bbruce@ucdavis.edu>
diff --git a/_pages/publications.md b/_pages/publications.md
index b145679..1331231 100644
--- a/_pages/publications.md
+++ b/_pages/publications.md
@@ -217,35 +217,32 @@
## 2009<span class="anchor" data-clipboard-text="http://www.gem5.org/publications/#2009"></span>
-* _Efficient Implementation of Decoupling Capacitors in 3D Processor-DRAM Integrated Computing Systems._ Q. Wu, J. Lu, K. Rose, and T. Zhang. Great Lakes Symposium on VLSI. 2009.
-* _Evaluating the Impact of Job Scheduling and Power Management on Processor Lifetime for Chip Multiprocessors._ A. K. Coskun, R. Strong, D. M. Tullsen, and T. S. Rosing. Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems. 2009.
-* ” Devices and architectures for photonic chip-scale integration.” J. Ahn, M. Fiorentino1, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease and Q. Xu. Journal of Applied Physics A: Materials Science & Processing. February 2009.
-* _System-Level Power, Thermal and Reliability Optimization._ C. Zhu. Thesis at Queen’s University. 2009.
-
-* _A light-weight fairness mechanism for chip multiprocessor memory systems._ M. Jahre, L. Natvig. Proceedings of the 6th ACM conference on Computing Frontiers. 2009.
-* _Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices._ H. Zheng, J. Lin, Z. Zhang, and Z. Zhu. International Symposium on Computer Architecture (ISCA). 2009.
-* _On the Performance of Commit-Time-Locking Based Software Transactional Memory._ Z. He and B. Hong. The 11th IEEE International Conference on. High Performance Computing and Communications (HPCC-09). 2009.
-
-* _A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures._ M. Jahre, M. Grannaes and L. Natvig. The 11th IEEE International Conference on. High Performance Computing and Communications (HPCC-09). 2009.
-* _Hardware Support for Debugging Message Passing Applications for Many-Core Architectures._ C. Svensson. Masters Thesis at the University of Illinois at Urbana-Champaign, 2009.
-* _Initial Experiments in Visualizing Fine-Grained Execution of Parallel Software Through Cycle-Level Simulation._ R. Strong, J. Mudigonda, J. C. Mogul, N. Binkert. USENIX Workshop on Hot Topics in Parallelism (HotPar). 2009.
-* _MPreplay: Architecture Support for Deterministic Replay of Message Passing Programs on Message Passing Many-core Processors._ C. Erik-Svensson, D. Kesler, R. Kumar, and G. Pokam. University of Illinois Technical Report number UILU-09-2209.
-* _Low-power Inter-core Communication through Cache Partitioning in Embedded Multiprocessors._ C. Yu, X. Zhou, and P. Petrov .Symposium on Integrated Circuits and System Design (sbcci). 2009.
-* _Integrating NAND flash devices onto servers._ D. Roberts, T. Kgil, T. Mudge. Communications of the ACM (CACM). 2009.
-* _A High-Performance Low-Power Nanophotonic On-Chip Network._ Z. Li, J. Wu, L. Shang, A. Mickelson, M. Vachharajani, D. Filipovic, W. Park∗ and Y. Sun. International Symposium on Low Power Electronic Design (ISLPED). 2009.
-* _Core monitors: monitoring performance in multicore processors._ P. West, Y. Peress, G. S. Tyson, and S. A. McKee. Computing Frontiers. 2009.
-* _Parallel Assertion Processing using Memory Snapshots._ M. F. Iqbal, J. H. Siddiqui, and D. Chiou. Workshop on Unique Chips and Systems (UCAS). April 2009.
-* _Leveraging Memory Level Parallelism Using Dynamic Warp Subdivision._ J. Meng, D. Tarjan, and K. Skadron. Univ. of Virginia Dept. of Comp. Sci. Tech Report (CS-2009-02).
-* _Reconfigurable Multicore Server Processors for Low Power Operation._ R. G. Dreslinski, D. Fick, D. Blaauw, D. Sylvester and T. Mudge. 9th International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS). July 2009.
-* _Near Threshold Computing: Overcoming Performance Degradation from Aggressive Voltage Scaling_ R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge. Workshop on Energy Efficient Design (WEED), June 2009.
-* _Workload Adaptive Shared Memory Multicore Processors with Reconfigurable Interconnects._ S. Akram, R. Kumar, and D. Chen. IEEE Symposium on Application Specific Processors, July 2009.
-
-* _Eliminating Microarchitectural Dependency from Architectural Vulnerability._ V. Sridharan, D. R. Kaeli. Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA-15), February 2009.
-* _Producing Wrong Data Without Doing Anything Obviously Wrong!_ T. Mytkowicz, A. Diwan, M. Hauswirth, P. F. Sweeney. Proceedings of the 14th international conference on Architectural support for programming languages and operating systems (ASPLOS). 2009.
-* _End-To-End Performance Forecasting: Finding Bottlenecks Before They Happen_ A. Saidi, N. Binkert, S. Reinhardt, T. Mudge. Proceedings of the 36th International Symposium on Computer Architecture (ISCA-36), June 2009.
-* _Fast Switching of Threads Between Cores._ R. Strong, J. Mudigonda, J. C. Mogul, N. Binkert, D. Tullsen. ACM SIGOPS Operating Systems Review. 2009.
-* _Express Cube Topologies for On-Chip Interconnects._ B. Grot, J. Hestness, S. W. Keckler, O. Mutlu. Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA-15), February 2009.
-* _Enhancing LTP-Driven Cache Management Using Reuse Distance Information._ W. Lieu, D. Yeung. Journal of Instruction-Level Parallelism 11 (2009).
+* [**Efficient Implementation of Decoupling Capacitors in 3D Processor-DRAM Integrated Computing Systems**](https://dl.acm.org/doi/10.1145/1531542.1531602). Q. Wu, J. Lu, K. Rose, and T. Zhang. Great Lakes Symposium on VLSI. 2009. doi:[10.1145/1531542.1531602](https://dx.doi.org/10.1145/1531542.1531602).
+* [**Evaluating the Impact of Job Scheduling and Power Management on Processor Lifetime for Chip Multiprocessors**](https://dl.acm.org/doi/10.1145/1555349.1555369). A. K. Coskun, R. Strong, D. M. Tullsen, and T. S. Rosing. Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems. 2009. doi:[10.1145/1555349.1555369](https://dx.doi.org/10.1145/1555349.1555369). <!-- XXX: The DOI URL is redirected to doi:10.1145/2492101.1555369. -->
+* [**Devices and architectures for photonic chip-scale integration**](https://link.springer.com/article/10.1007%2Fs00339-009-5109-2). J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease and Q. Xu. Journal of Applied Physics A: Materials Science & Processing. February 2009. doi:[10.1007/s00339-009-5109-2](https://dx.doi.org/10.1007/s00339-009-5109-2).
+* _System-Level Power, Thermal and Reliability Optimization_. C. Zhu. Thesis at Queen’s University. 2009. [link](https://hdl.handle.net/1974/1979)
+* [**A light-weight fairness mechanism for chip multiprocessor memory systems**](https://dl.acm.org/doi/10.1145/1531743.1531747). M. Jahre, L. Natvig. Proceedings of the 6th ACM conference on Computing Frontiers. 2009. doi:[10.1145/1531743.1531747](https://dx.doi.org/10.1145/1531743.1531747).
+* [**Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices**](https://dl.acm.org/doi/10.1145/1555754.1555788). H. Zheng, J. Lin, Z. Zhang, and Z. Zhu. International Symposium on Computer Architecture (ISCA). 2009. doi:[10.1145/1555754.1555788](https://dx.doi.org/10.1145/1555754.1555788).
+* [**On the Performance of Commit-Time-Locking Based Software Transactional Memory**](https://ieeexplore.ieee.org/document/5166992). Z. He and B. Hong. The 11th IEEE International Conference on High Performance Computing and Communications (HPCC-09). 2009. doi:[10.1109/HPCC.2009.64](https://dx.doi.org/10.1109/HPCC.2009.64).
+* [**A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures**](https://ieeexplore.ieee.org/document/5167054). M. Jahre, M. Grannaes and L. Natvig. The 11th IEEE International Conference on High Performance Computing and Communications (HPCC-09). 2009. doi:[10.1109/HPCC.2009.77](https://dx.doi.org/10.1109/HPCC.2009.77). [pdf](https://folk.idi.ntnu.no/jahre/publications/jahreMMAPCameraReady-v2.pdf)
+* _Hardware Support for Debugging Message Passing Applications for Many-Core Architectures_. C. Svensson. Masters Thesis at the University of Illinois at Urbana-Champaign, 2009.
+* _Initial Experiments in Visualizing Fine-Grained Execution of Parallel Software Through Cycle-Level Simulation_. R. Strong, J. Mudigonda, J. C. Mogul, N. Binkert. USENIX Workshop on Hot Topics in Parallelism (HotPar). 2009. <!-- XXX: Not found in https://www.usenix.org/legacy/events/hotpar09/tech/ -->
+* _MPreplay: Architecture Support for Deterministic Replay of Message Passing Programs on Message Passing Many-core Processors._ C. Erik-Svensson, D. Kesler, R. Kumar, and G. Pokam. University of Illinois Technical Report number UILU-ENG-09-2209, CRHC-09-06. [link](https://hdl.handle.net/2142/74613)
+* [**Low-power Inter-core Communication through Cache Partitioning in Embedded Multiprocessors**](https://dl.acm.org/doi/10.1145/1601896.1601903). C. Yu, X. Zhou, and P. Petrov. Symposium on Integrated Circuits and System Design (SBCCI). 2009. doi:[10.1145/1601896.1601903](https://dx.doi.org/10.1145/1601896.1601903).
+* [**Integrating NAND flash devices onto servers**](https://dl.acm.org/doi/10.1145/1498765.1498791). D. Roberts, T. Kgil, T. Mudge. Communications of the ACM (CACM). 2009. doi:[10.1145/1498765.1498791](https://dx.doi.org/10.1145/1498765.1498791). [pdf](https://tnm.engin.umich.edu/wp-content/uploads/sites/353/2017/12/2009.04.Integrating-NAND-Flash.pdf)
+* [**A High-Performance Low-Power Nanophotonic On-Chip Network**](https://dl.acm.org/doi/10.1145/1594233.1594305). Z. Li, J. Wu, L. Shang, A. Mickelson, M. Vachharajani, D. Filipovic, W. Park, and Y. Sun. International Symposium on Low Power Electronic Design (ISLPED). 2009. doi:[10.1145/1594233.1594305](https://dx.doi.org/10.1145/1594233.1594305).
+* [**Core monitors: monitoring performance in multicore processors**](https://dl.acm.org/doi/10.1145/1531743.1531751). P. West, Y. Peress, G. S. Tyson, and S. A. McKee. Computing Frontiers. 2009. doi:[10.1145/1531743.1531751](https://dx.doi.org/10.1145/1531743.1531751). [pdf](https://ww2.cs.fsu.edu/~peress/publications/CF2009.pdf)
+* _Parallel Assertion Processing using Memory Snapshots_. J. H. Siddiqui, M. F. Iqbal, and D. Chiou. Workshop on Unique Chips and Systems (UCAS). April 2009. [pdf](https://ispass.org/ucas5/session3_3_ut.pdf)
+* _Leveraging Memory Level Parallelism Using Dynamic Warp Subdivision._ J. Meng, D. Tarjan, and K. Skadron. Univ. of Virginia Dept. of Comp. Sci. Tech Report (CS-2009-02). [pdf](https://www.cs.virginia.edu/~skadron/Papers/warpshuffle_tr09.pdf)
+* [**Reconfigurable Multicore Server Processors for Low Power Operation**](https://link.springer.com/chapter/10.1007%2F978-3-642-03138-0_27). R. G. Dreslinski, D. Fick, D. Blaauw, D. Sylvester and T. Mudge. 9th International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS). July 2009. doi:[10.1007/978-3-642-03138-0\_27](https://dx.doi.org/10.1007/978-3-642-03138-0_27). [pdf](https://blaauw.engin.umich.edu/wp-content/uploads/sites/342/2017/11/392.pdf)
+* _Near Threshold Computing: Overcoming Performance Degradation from Aggressive Voltage Scaling_. R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge. Workshop on Energy Efficient Design (WEED), June 2009. [pdf](https://tnm.engin.umich.edu/wp-content/uploads/sites/353/2017/12/2009.06.Near-Threshold-Computing.pdf)
+* [**Workload Adaptive Shared Memory Multicore Processors with Reconfigurable Interconnects**](https://ieeexplore.ieee.org/document/5226329). S. Akram, R. Kumar, and D. Chen. IEEE Symposium on Application Specific Processors, July 2009. doi:[10.1109/SASP.2009.5226329](https://doi.org/10.1109/SASP.2009.5226329). [pdf](https://dchen.ece.illinois.edu/research/SASP09_Shoaib.pdf)
+* [**Eliminating Microarchitectural Dependency from Architectural Vulnerability**](https://ieeexplore.ieee.org/document/4798243). V. Sridharan, D. R. Kaeli. Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA-15), February 2009. doi:[10.1109/HPCA.2009.4798243](https://dx.doi.org/10.1109/HPCA.2009.4798243). [pdf](https://ece.northeastern.edu/groups/nucar/publications/HPCA09.pdf)
+* [**Producing Wrong Data Without Doing Anything Obviously Wrong!**](https://dl.acm.org/doi/10.1145/1508244.1508275) T. Mytkowicz, A. Diwan, M. Hauswirth, P. F. Sweeney. Proceedings of the 14th international conference on Architectural support for programming languages and operating systems (ASPLOS). 2009. doi:[10.1145/1508244.1508275](https://dx.doi.org/10.1145/1508244.1508275). <!-- XXX: Also published as doi:10.1145/2528521.1508275 and doi:10.1145/1508284.1508275. Are they all the same? -->
+* [**End-To-End Performance Forecasting: Finding Bottlenecks Before They Happen**](https://dl.acm.org/doi/10.1145/1555754.1555800). A. Saidi, N. Binkert, S. Reinhardt, T. Mudge. Proceedings of the 36th International Symposium on Computer Architecture (ISCA-36), June 2009. doi:[10.1145/1555754.1555800](https://dx.doi.org/10.1145/1555754.1555800). [pdf](https://tnm.engin.umich.edu/wp-content/uploads/sites/353/2017/12/2009.6.End-to-end_performance_ISCA.pdf)
+* [**Fast Switching of Threads Between Cores**](https://dl.acm.org/doi/10.1145/1531793.1531801). R. Strong, J. Mudigonda, J. C. Mogul, N. Binkert, D. Tullsen. ACM SIGOPS Operating Systems Review. 2009. doi:[10.1145/1531793.1531801](https://dx.doi.org/10.1145/1531793.1531801).
+* [**Express Cube Topologies for On-Chip Interconnects**](https://ieeexplore.ieee.org/document/4798251). B. Grot, J. Hestness, S. W. Keckler, O. Mutlu. Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA-15), February 2009. doi:[10.1109/HPCA.2009.4798251](https://dx.doi.org/10.1109/HPCA.2009.4798251). [pdf](https://pages.cs.wisc.edu/~hestness/links/MECS_HPCA09.pdf)
+* _Enhancing LTP-Driven Cache Management Using Reuse Distance Information._ W. Lieu, D. Yeung. Journal of Instruction-Level Parallelism 11 (2009). [pdf](https://jilp.org/vol11/v11paper1.pdf)
## 2008<span class="anchor" data-clipboard-text="http://www.gem5.org/publications/#2008"></span>
@@ -304,7 +301,7 @@
* [**On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology**](https://ieeexplore.ieee.org/document/4341526). D. Roberts, N. Kim,T. Mudge. Digital System Design Architectures, Methods and Tools (DSD). August 2007. doi:[10.1109/DSD.2007.4341526](https://dx.doi.org/10.1109/DSD.2007.4341526). [pdf](https://tnm.engin.umich.edu/wp-content/uploads/sites/353/2017/12/2007.08.On-chip-cache-device-scaling-limits-and-effective-fault-repair.pdf)
* [**Energy Efficient Near-threshold Chip Multi-processing**](https://dl.acm.org/doi/10.1145/1283780.1283789). B. Zhai, R. Dreslinski, D. Blaauw, T. Mudge, D. Sylvester. International Symposium on Low Power Electronics and Design (ISLPED). August 2007. doi:[10.1145/1283780.1283789](https://dx.doi.org/10.1145/1283780.1283789). [pdf](https://blaauw.engin.umich.edu/wp-content/uploads/sites/342/2018/02/Zhai-Energy-Efficent-Near-threshold-Chip-Multi-processing.pdf)
* [**A Burst Scheduling Access Reordering Mechanism**](https://ieeexplore.ieee.org/document/4147669). J. Shao, B.T. Davis. IEEE 13th International Symposium on High Performance Computer Architecture (HPCA). 2007. doi:[10.1109/HPCA.2007.346206](https://dx.doi.org/10.1109/HPCA.2007.346206). [pdf](http://mercury.pr.erau.edu/~davisb22/papers/burst_scheduling_hpca13.pdf)
-* _Enhancing LTP-Driven Cache Management Using Reuse Distance Information_. W. Liu, D. Yeung. University of Maryland Technical Report UMIACS-TR-2007-33. June 2007. [pdf](http://maggini.eng.umd.edu/pub/UMIACS-TR-2007-33.pdf) <!-- XXX: Also published in Journal of Instruction-Level Parallelism, Volume 11 (2009). https://jilp.org/vol11/ -->
+* _Enhancing LTP-Driven Cache Management Using Reuse Distance Information_. W. Liu, D. Yeung. University of Maryland Technical Report UMIACS-TR-2007-33. June 2007. [pdf](http://maggini.eng.umd.edu/pub/UMIACS-TR-2007-33.pdf)
* [**Thermal modeling and management of DRAM memory systems**](https://ieeexplore.ieee.org/document/6212452). J. Lin, H. Zheng, Z. Zhu, H. David, and Z. Zhang. Proceedings of the 34th Annual international Symposium on Computer Architecture (ISCA). June 2007. doi:[10.1109/TC.2012.118](https://dx.doi.org/10.1109/TC.2012.118).
* _Duplicating and Verifying LogTM with OS Support in the M5 Simulator_. G. Blake, T. Mudge. Sixth Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD). June 2007. [pdf](https://pharm.ece.wisc.edu/wddd/2007/papers/wddd_03.pdf)
* [**Analysis of Hardware Prefetching Across Virtual Page Boundaries**](https://dl.acm.org/doi/10.1145/1242531.1242537). R. Dreslinski, A. Saidi, T. Mudge, S. Reinhardt. Proc. of the 4th Conference on Computing Frontiers. May 2007. doi:[10.1145/1242531.1242537](https://dx.doi.org/10.1145/1242531.1242537). [pdf](https://tnm.engin.umich.edu/wp-content/uploads/sites/353/2017/12/2007.07.Analysis_of_hardware_prefetching.pdf)
