website: Fix Doxygen links in documentation to new link
Change-Id: Iae91f36065c1fd33287f6b8a071f6d0bf842b39f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-website/+/26903
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/_pages/documentation/general_docs/cpu_models/minor_cpu.md b/_pages/documentation/general_docs/cpu_models/minor_cpu.md
index 49a9306..39a7cdd 100644
--- a/_pages/documentation/general_docs/cpu_models/minor_cpu.md
+++ b/_pages/documentation/general_docs/cpu_models/minor_cpu.md
@@ -10,21 +10,21 @@
Minor CPU Model
This document contains a description of the structure and function of the
-[Minor](https://gem5.github.io/gem5-doxygen/namespaceMinor.html) gem5 in-order
+[Minor](http://doxygen.gem5.org/release/current/namespaceMinor.html) gem5 in-order
processor model.
It is recommended reading for anyone who wants to understand
-[Minor](https://gem5.github.io/gem5-doxygen/namespaceMinor.html)'s internal
+[Minor](http://doxygen.gem5.org/release/current/namespaceMinor.html)'s internal
organisation, design decisions, C++ implementation and Python configuration. A
familiarity with gem5 and some of its internal structures is assumed. This
document is meant to be read alongside the
-[Minor](https://gem5.github.io/gem5-doxygen/namespaceMinor.html) source code
+[Minor](http://doxygen.gem5.org/release/current/namespaceMinor.html) source code
and to explain its general structure without being too slavish about naming
every function and data type.
## What is Minor?
-[Minor](https://gem5.github.io/gem5-doxygen/namespaceMinor.html) is an in-order
+[Minor](http://doxygen.gem5.org/release/current/namespaceMinor.html) is an in-order
processor model with a fixed pipeline but configurable data structures and
execute behaviour. It is intended to be used to model processors with strict
in-order execution behaviour and allows visualisation of an instruction's
@@ -45,46 +45,46 @@
Decorating data structures with large amounts of life-cycle information is
avoided. Only instructions
([MinorDynInst](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html)) contain a
+http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html)) contain a
significant proportion of their data content whose values are not set at
construction.
All internal structures have fixed sizes on construction. Data held in queues
and FIFOs ([MinorBuffer](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorBuffer.html),
+http://doxygen.gem5.org/release/current/classMinor_1_1MinorBuffer.html),
[FUPipeline](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1FUPipeline.html)) should have
-a [BubbleIF](https://gem5.github.io/gem5-doxygen/classMinor_1_1BubbleIF.html)
+http://doxygen.gem5.org/release/current/classMinor_1_1FUPipeline.html)) should have
+a [BubbleIF](http://doxygen.gem5.org/release/current/classMinor_1_1BubbleIF.html)
interface to allow a distinct 'bubble'/no data value option for each type.
Inter-stage 'struct' data is packaged in structures which are passed by value.
Only [MinorDynInst](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html), the line
+http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html), the line
data in [ForwardLineData](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a36a7ec6a8c5a6d27fd013d8b0238029d)
+http://doxygen.gem5.org/release/current/classMinorCPU.html#a36a7ec6a8c5a6d27fd013d8b0238029d)
and the memory-interfacing objects [Fetch1::FetchRequest](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1_1_1FetchRequest.html)
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1_1_1FetchRequest.html)
and [LSQ::LSQRequest](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ_1_1LSQRequest.html) are
+http://doxygen.gem5.org/release/current/classMinor_1_1LSQ_1_1LSQRequest.html) are
`::new` allocated while running the model.
## Model structure
Objects of class [MinorCPU](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html) are provided by the
+http://doxygen.gem5.org/release/current/classMinorCPU.html) are provided by the
model to gem5. [MinorCPU](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html) implements the
+http://doxygen.gem5.org/release/current/classMinorCPU.html) implements the
interfaces of (cpu.hh) and can provide data and instruction interfaces for
connection to a cache system. The model is configured in a similar way to other
gem5 models through Python. That configuration is passed on to
[MinorCPU::pipeline](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a36a7ec6a8c5a6d27fd013d8b0238029d)
+http://doxygen.gem5.org/release/current/classMinorCPU.html#a36a7ec6a8c5a6d27fd013d8b0238029d)
(of class [Pipeline](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Pipeline.html)) which
+http://doxygen.gem5.org/release/current/classMinor_1_1Pipeline.html)) which
actually implements the processor pipeline.
The hierarchy of major unit ownership from [MinorCPU](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html) down looks like this:
+http://doxygen.gem5.org/release/current/classMinorCPU.html) down looks like this:
```
MinorCPU
@@ -114,23 +114,23 @@
- 0/10.12/5/6.7
```
-[InstId](https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html) fields
+[InstId](http://doxygen.gem5.org/release/current/classMinor_1_1InstId.html) fields
are:
|Field|Symbol|Generated by|Checked by|Function|
|:----|:-----|:-----------|:---------|:-------|
-|InstId::threadId|T|[Fetch1](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) | Everywhere the thread number is needed| Thread number (currently always 0).
-|InstId::streamSeqNum|S|[Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) | Fetch1, Fetch2, Execute (to discard lines/insts) | Stream sequence number as chosen by Execute. Stream sequence numbers change after changes of PC (branches, exceptions) in Execue and are used to separate pre and post brnach instrucion streams.|
-|InstId::predictionSeqNum|[Fetch2](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html)| Fetch2 (while discarding lines after prediction)| Prediction sequence numbers represent branch prediction decisions. This is used by Fetch2 to mark lines/instructions/ according to the last followed branch prediction made by Fetch2. Fetch2 can signal to Fetch1 that it should change its fetch address and mark lines with a new prediction sequence number (which it will only do if the stream sequence number Fetch1 expects matches that of the request).
-|InstId::lineSeqNum|[Fetch1](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html)| (just for debugging) | Line fetch sequence number of this cache line or the line this instruction was extracted from.|
-|InstId::fetchSeqNum|[Fetch2](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) | Fetch2 (as the inst. sequence number for branches) | Instruction fetch order assigned by Fetch2 when lines are decomposed into instructions.|
-|InstId::execSeqNum|[Decode](https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html)|Execute (to check instruction identify in queues/FUs/LSQ| Instruction order after micro-op decomposition|
+|InstId::threadId|T|[Fetch1](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) | Everywhere the thread number is needed| Thread number (currently always 0).
+|InstId::streamSeqNum|S|[Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) | Fetch1, Fetch2, Execute (to discard lines/insts) | Stream sequence number as chosen by Execute. Stream sequence numbers change after changes of PC (branches, exceptions) in Execue and are used to separate pre and post brnach instrucion streams.|
+|InstId::predictionSeqNum|[Fetch2](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html)| Fetch2 (while discarding lines after prediction)| Prediction sequence numbers represent branch prediction decisions. This is used by Fetch2 to mark lines/instructions/ according to the last followed branch prediction made by Fetch2. Fetch2 can signal to Fetch1 that it should change its fetch address and mark lines with a new prediction sequence number (which it will only do if the stream sequence number Fetch1 expects matches that of the request).
+|InstId::lineSeqNum|[Fetch1](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html)| (just for debugging) | Line fetch sequence number of this cache line or the line this instruction was extracted from.|
+|InstId::fetchSeqNum|[Fetch2](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) | Fetch2 (as the inst. sequence number for branches) | Instruction fetch order assigned by Fetch2 when lines are decomposed into instructions.|
+|InstId::execSeqNum|[Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html)|Execute (to check instruction identify in queues/FUs/LSQ| Instruction order after micro-op decomposition|
The sequence number fields are all independent of each other and although, for
instance, [InstId::execSeqNum](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html#a064b0e4480268559e68510311be2a9b0)
+http://doxygen.gem5.org/release/current/classMinor_1_1InstId.html#a064b0e4480268559e68510311be2a9b0)
for an instruction will always be >= [InstId::fetchSeqNum](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html#a06677e68051a2a52f384e55e9368e33d),
+http://doxygen.gem5.org/release/current/classMinor_1_1InstId.html#a06677e68051a2a52f384e55e9368e33d),
the comparison is not useful.
The originating stage of each sequence number field keeps a counter for that
@@ -140,33 +140,33 @@
### Instructi ns: MinorDynInst (`dyn_inst.hh`)
[MinorDynInst](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html) represents
+http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html) represents
an instruction's progression through the pipeline. An instruction can be three
things:
|Things |Predicate |Explanation|
|:---------------------|:---------------------------------------------------------------------------------------------------------------------------------|:----------|
-|A bubble |[MinorDynInst::isBubble()](https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#a24e835fa495026ca63ffec43ee9cc07e) | no instruction at all, just a space-filler|
-|A fault |[MinorDynInst::isFault()](https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#a24029f3cd1835928d572737a548a824e) | a fault to pass down the pipeline in an insturction's clothing|
-|A decoded instruction |[MinorDynInst::isInst()](https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#adc55cdcf9f7c6588bb27eddb4c7fe38e) | instructions are actually passed to the gem5 decoder in Fetch2 and so are created fully decoded. MinorDynInst::staticInst is the decoded instruction form. |
+|A bubble |[MinorDynInst::isBubble()](http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html#a24e835fa495026ca63ffec43ee9cc07e) | no instruction at all, just a space-filler|
+|A fault |[MinorDynInst::isFault()](http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html#a24029f3cd1835928d572737a548a824e) | a fault to pass down the pipeline in an insturction's clothing|
+|A decoded instruction |[MinorDynInst::isInst()](http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html#adc55cdcf9f7c6588bb27eddb4c7fe38e) | instructions are actually passed to the gem5 decoder in Fetch2 and so are created fully decoded. MinorDynInst::staticInst is the decoded instruction form. |
Instructions are reference counted using the gem5 [RefCountingPtr](
-https://gem5.github.io/gem5-doxygen/classRefCountingPtr.html)
-([base/refcnt.hh](https://gem5.github.io/gem5-doxygen/refcnt_8hh.html))
+http://doxygen.gem5.org/release/current/classRefCountingPtr.html)
+([base/refcnt.hh](http://doxygen.gem5.org/release/current/refcnt_8hh.html))
wrapper. They therefore usually appear as MinorDynInstPtr in code. Note that as
-[RefCountingPtr](https://gem5.github.io/gem5-doxygen/classRefCountingPtr.html)
+[RefCountingPtr](http://doxygen.gem5.org/release/current/classRefCountingPtr.html)
initialises as nullptr rather than an object that supports
[BubbleIF::isBubble](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1BubbleIF.html#a7ce121301dba2e89b94235d96bf339ae)
+http://doxygen.gem5.org/release/current/classMinor_1_1BubbleIF.html#a7ce121301dba2e89b94235d96bf339ae)
passing raw MinorDynInstPtrs to [Queues](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Queue.html) and other similar
+http://doxygen.gem5.org/release/current/classMinor_1_1Queue.html) and other similar
structures from stage.hh without boxing is dangerous.
### ForwardLineData (`pipe_data.hh`)
ForwardLineData is used to pass cache lines from Fetch1 to Fetch2. Like
MinorDynInsts, they can be bubbles ([ForwardLineData::isBubble()](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardLineData.html#a46789690719acf167be0a57c9d7d4f8f)),
+http://doxygen.gem5.org/release/current/classMinor_1_1ForwardLineData.html#a46789690719acf167be0a57c9d7d4f8f)),
fault-carrying or can contain a line (partial line) fetched by Fetch1. The data
carried by ForwardLineData is owned by a Packet object returned from memory and
is explicitly memory managed and do must be deleted once processed (by Fetch2
@@ -175,9 +175,9 @@
### ForwardInstData (`pipe_data.hh`)
ForwardInstData can contain up to [ForwardInstData::width()](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardInstData.html#ad5db21f655f2f1dfff69e6f6d5cc606e)
+http://doxygen.gem5.org/release/current/classMinor_1_1ForwardInstData.html#ad5db21f655f2f1dfff69e6f6d5cc606e)
instructions in its [ForwardInstData::insts](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardInstData.html#ab54a61c683376aaf5a12ea19ab758340)
+http://doxygen.gem5.org/release/current/classMinor_1_1ForwardInstData.html#ab54a61c683376aaf5a12ea19ab758340)
vector. This structure is used to carry instructions between Fetch2, Decode and
Execute and to store input buffer vectors in Decode and Execute.
@@ -185,13 +185,13 @@
FetchRequests represent I-cache line fetch requests. The are used in the memory
queues of Fetch1 and are pushed into/popped from [Packet::senderState](
-https://gem5.github.io/gem5-doxygen/classPacket.html#ad1dd4fa4370e508806fe4a8253a0ad12)
+http://doxygen.gem5.org/release/current/classPacket.html#ad1dd4fa4370e508806fe4a8253a0ad12)
while traversing the memory system.
FetchRequests contain a memory system Request ([mem/request.hh](
-https://gem5.github.io/gem5-doxygen/request_8hh.html)) for that fetch access, a
+http://doxygen.gem5.org/release/current/request_8hh.html)) for that fetch access, a
packet (Packet, [mem/packet.hh](
-https://gem5.github.io/gem5-doxygen/packet_8hh.html)), if the request gets to
+http://doxygen.gem5.org/release/current/packet_8hh.html)), if the request gets to
memory, and a fault field that can be populated with a TLB-sourced prefetch
fault (if any).
@@ -225,11 +225,11 @@
```
The four pipeline stages are connected together by [MinorBuffer](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorBuffer.html) FIFO
+http://doxygen.gem5.org/release/current/classMinor_1_1MinorBuffer.html) FIFO
(stage.hh, derived ultimately from [TimeBuffer](
-https://gem5.github.io/gem5-doxygen/classTimeBuffer.html)) structures which
+http://doxygen.gem5.org/release/current/classTimeBuffer.html)) structures which
allow inter-stage delays to be modelled. There is a [MinorBuffers](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorBuffer.html) between
+http://doxygen.gem5.org/release/current/classMinor_1_1MinorBuffer.html) between
adjacent stages in the forward direction (for example: passing lines from
Fetch1 to Fetch2) and, between Fetch2 and Fetch1, a buffer in the backwards
direction carrying branch predictions.
@@ -239,13 +239,13 @@
is not ready to process it. Input buffers store data in the same form as it is
received and so Decode and Execute's input buffers contain the output
instruction vector ([ForwardInstData](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardInstData.html)
-([pipe_data.hh](https://gem5.github.io/gem5-doxygen/pipe__data_8hh.html))) from
+http://doxygen.gem5.org/release/current/classMinor_1_1ForwardInstData.html)
+([pipe_data.hh](http://doxygen.gem5.org/release/current/pipe__data_8hh.html))) from
their previous stages with the instructions and bubbles in the same positions
as a single buffer entry.
Stage input buffers provide a [Reservable](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Reservable.html) (stage.hh)
+http://doxygen.gem5.org/release/current/classMinor_1_1Reservable.html) (stage.hh)
interface to their previous stages, to allow slots to be reserved in their
input buffers, and communicate their input buffer occupancy backwards to allow
the previous stage to plan whether it should make an output in a given cycle.
@@ -255,32 +255,32 @@
Minor is essentially a cycle-callable model with some ability to skip cycles
based on pipeline activity. External events are mostly received by callbacks
(e.g. [Fetch1::IcachePort::recvTimingResp](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1_1_1IcachePort.html#aec62b3d89dfe61e8528cdcdf3729eeab))
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1_1_1IcachePort.html#aec62b3d89dfe61e8528cdcdf3729eeab))
and cause the pipeline to be woken up to service advancing request queues.
-[Ticked](https://gem5.github.io/gem5-doxygen/classTicked.html) (sim/ticked.hh)
+[Ticked](http://doxygen.gem5.org/release/current/classTicked.html) (sim/ticked.hh)
is a base class bringing together an evaluate member function and a provided
-[SimObject](https://gem5.github.io/gem5-doxygen/classSimObject.html). It
+[SimObject](http://doxygen.gem5.org/release/current/classSimObject.html). It
provides a [Ticked::start](
-https://gem5.github.io/gem5-doxygen/classTicked.html#a798d1e248c27161de6eb2bc6fef5e425)/stop
+http://doxygen.gem5.org/release/current/classTicked.html#a798d1e248c27161de6eb2bc6fef5e425)/stop
interface to start and pause clock events from being periodically issued.
-[Pipeline](https://gem5.github.io/gem5-doxygen/classMinor_1_1Pipeline.html) is
+[Pipeline](http://doxygen.gem5.org/release/current/classMinor_1_1Pipeline.html) is
a derived class of Ticked.
During evaluate calls, stages can signal that they still have work to do in the
next cycle by calling either [MinorCPU::activityRecorder](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html#ae3b03c96ee234e2c5c6c68f4567245a7)->activity()
+http://doxygen.gem5.org/release/current/classMinorCPU.html#ae3b03c96ee234e2c5c6c68f4567245a7)->activity()
(for non-callable related activity) or MinorCPU::wakeupOnEvent(<stageId>) (for
stage callback-related 'wakeup' activity).
[Pipeline::evaluate](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Pipeline.html#af07fdce00c8937e9de5b6450a1cd62bf)
+http://doxygen.gem5.org/release/current/classMinor_1_1Pipeline.html#af07fdce00c8937e9de5b6450a1cd62bf)
contains calls to evaluate for each unit and a test for pipeline idling which
can turns off the clock tick if no unit has signalled that it may become active
next cycle.
Within Pipeline ([pipeline.hh](
-https://gem5.github.io/gem5-doxygen/pipeline_8hh.html)), the stages are
+http://doxygen.gem5.org/release/current/pipeline_8hh.html)), the stages are
evaluated in reverse order (and so will ::evaluate in reverse order) and their
backwards data can be read immediately after being written in each cycle
allowing output decisions to be 'perfect' (allowing synchronous stalling of the
@@ -289,9 +289,9 @@
configurable delay which can be set as low as 0 cycles.
The [MinorCPU::activateContext](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a854596342bfb9dd889437e494c4ddb27)
+http://doxygen.gem5.org/release/current/classMinorCPU.html#a854596342bfb9dd889437e494c4ddb27)
and [MinorCPU::suspendContext](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html#ae6aa9b1bb798d8938f0b35e11d9e68b8)
+http://doxygen.gem5.org/release/current/classMinorCPU.html#ae6aa9b1bb798d8938f0b35e11d9e68b8)
interface can be called to start and pause threads (threads in the MT sense)
and to start and pause the pipeline. Executing instructions can call this
interface (indirectly through the ThreadContext) to idle the CPU/their threads.
@@ -328,43 +328,43 @@
### Fetch1 stage
-[Fetch1](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) is
+[Fetch1](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) is
responsible for fetching cache lines or partial cache lines from the I-cache
and passing them on to [Fetch2](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) to be decomposed
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) to be decomposed
into instructions. It can receive 'change of stream' indications from both
-[Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) and
-[Fetch2](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) to
+[Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) and
+[Fetch2](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) to
signal that it should change its internal fetch address and tag newly fetched
lines with new stream or prediction sequence numbers. When both Execute and
-[Fetch2](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) signal
+[Fetch2](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) signal
changes of stream at the same time, [Fetch1](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) takes
-[Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html)'s
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) takes
+[Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html)'s
change.
Every line issued by [Fetch1](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) will bear a
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) will bear a
unique line sequence number which can be used for debugging stream changes.
When fetching from the I-cache, [Fetch1](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) will ask for
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) will ask for
data from the current fetch address (Fetch1::pc) up to the end of the 'data
snap' size set in the parameter fetch1LineSnapWidth. Subsequent autonomous line
fetches will fetch whole lines at a snap boundary and of size fetch1LineWidth.
-[Fetch1](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) will
+[Fetch1](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) will
only initiate a memory fetch if it can reserve space in [Fetch2](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) input buffer.
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) input buffer.
That input buffer serves an the fetch queue/LFL for the system.
-[Fetch1](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html)
+[Fetch1](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html)
contains two queues: requests and transfers to handle the stages of translating
the address of a line fetch (via the TLB) and accommodating the
request/response of fetches to/from memory.
Fetch requests from [Fetch1](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) are pushed into
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) are pushed into
the requests queue as newly allocated FetchRequest objects once they have been
sent to the ITLB with a call to itb->translateTiming.
@@ -374,11 +374,11 @@
queue. In that case, the TLB response is marked up as a state change to
Translated in the request object, and advancing the request to transfers (and
the memory system) is left to calls to [Fetch1::stepQueues](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html#ac143710b93ec9f55bfc3e2882ef2fe4c)
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html#ac143710b93ec9f55bfc3e2882ef2fe4c)
which is called in the cycle following any event is received.
[Fetch1::tryToSendToTransfers](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html#a9ace21e8131caf360190ea876cfa2934)
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html#a9ace21e8131caf360190ea876cfa2934)
---
layout: documentation
title: Execution Basics
@@ -393,14 +393,14 @@
Responses from memory change the request object state to Complete and
[Fetch1::evaluate](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html#a68a0a88ce6ee3dd170c977318cfb4ca9)
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html#a68a0a88ce6ee3dd170c977318cfb4ca9)
can pick up response data, package it in the [ForwardLineData](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1ForwardLineData.html) object,
+http://doxygen.gem5.org/release/current/classMinor_1_1ForwardLineData.html) object,
and forward it to [Fetch2](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html)'s input buffer.
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html)'s input buffer.
As space is always reserved in [Fetch2::inputBuffer](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html#afdaa27275e2f605d9aaa637e8c39f96d),
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html#afdaa27275e2f605d9aaa637e8c39f96d),
setting the input buffer's size to 1 results in non-prefetching behaviour.
When a change of stream occurs, translated requests queue members and completed
@@ -412,7 +412,7 @@
Fetch2 receives a line from Fetch1 into its input buffer. The data in the head
line in that buffer is iterated over and separated into individual instructions
which are packed into a vector of instructions which can be passed to
-[Decode](https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html).
+[Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html).
Packing instructions can be aborted early if a fault is found in either the
input line as a whole or a decomposed instruction.
@@ -422,10 +422,10 @@
Branches are predicted for any control instructions found. If prediction is
attempted for an instruction, the [MinorDynInst::triedToPredict](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#a905b0516019ae7f47b5795ceda33f5cd)
+http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html#a905b0516019ae7f47b5795ceda33f5cd)
flag is set on that instruction.
-When a branch is predicted to take, the [MinorDynInst::predictedTaken](https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#aa57659ef9d30162ddcf10fcb0f3963ac) flag is set and [MinorDynInst::predictedTarget](https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#a5eaf9547bcaefa2c0fd37f32c828691b) is set to the predicted target PC value. The predicted branch instruction is then packed into Fetch2's output vector, the prediction sequence number is incremented, and the branch is communicated to Fetch1.
+When a branch is predicted to take, the [MinorDynInst::predictedTaken](http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html#aa57659ef9d30162ddcf10fcb0f3963ac) flag is set and [MinorDynInst::predictedTarget](http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html#a5eaf9547bcaefa2c0fd37f32c828691b) is set to the predicted target PC value. The predicted branch instruction is then packed into Fetch2's output vector, the prediction sequence number is incremented, and the branch is communicated to Fetch1.
After signalling a prediction, Fetch2 will discard its input buffer contents
and will reject any new lines which have the same stream sequence number as
@@ -441,7 +441,7 @@
Branches (and instructions predicted to branch) which are processed by Execute
will generate BranchData ([pipe_data.hh](
-https://gem5.github.io/gem5-doxygen/pipe__data_8hh.html)) data explaining the
+http://doxygen.gem5.org/release/current/pipe__data_8hh.html)) data explaining the
outcome of the branch which is sent forwards to Fetch1 and Fetch2. Fetch1 uses
this data to change stream (and update its stream sequence number and address
for new lines). Fetch2 uses it to update the branch predictor. Minor does not
@@ -449,7 +449,7 @@
discarded on the way to commit.
BranchData::BranchReason ([pipe_data.hh](
-https://gem5.github.io/gem5-doxygen/pipe__data_8hh.html)) encodes the possible
+http://doxygen.gem5.org/release/current/pipe__data_8hh.html)) encodes the possible
branch scenarios:
@@ -474,15 +474,15 @@
### Decode Stage
-[Decode](https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html) takes a
+[Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html) takes a
vector of instructions from [Fetch2](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) (via its input
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) (via its input
buffer) and decomposes those instructions into micro-ops (if necessary) and
packs them into its output instruction vector.
The parameter executeInputWidth sets the number of instructions which can be
packed into the output per cycle. If the parameter decodeCycleInput is true,
-[Decode](https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html) can try
+[Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html) can try
to take instructions from more than one entry in its input buffer per cycle.
### Execute Stage
@@ -508,7 +508,7 @@
capable of more complicated timing.
Each active cycle, [Execute::evaluate](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#a2d6ca9a694bf99ef82da7759cba8c3da)
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html#a2d6ca9a694bf99ef82da7759cba8c3da)
performs this action:
```
@@ -536,10 +536,10 @@
Functional units are implemented as SelfStallingPipelines (stage.hh). These are
-[TimeBuffer](https://gem5.github.io/gem5-doxygen/classTimeBuffer.html) FIFOs
+[TimeBuffer](http://doxygen.gem5.org/release/current/classTimeBuffer.html) FIFOs
with two distinct 'push' and 'pop' wires. They respond to
[SelfStallingPipeline::advance](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1SelfStallingPipeline.html#ad933640bc6aab559c009302e478c3768)
+http://doxygen.gem5.org/release/current/classMinor_1_1SelfStallingPipeline.html#ad933640bc6aab559c009302e478c3768)
in the same way as TimeBuffers unless there is data at the far, 'pop', end of
the FIFO. A 'stalled' flag is provided for signalling stalling and to allow a
stall to be cleared. The intention is to provide a pipeline for each functional
@@ -571,11 +571,11 @@
Memory operation instructions traverse their functional units to perform their
EA calculations. On 'commit', the [ExecContext](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1ExecContext.html)::initiateAcc
+http://doxygen.gem5.org/release/current/classMinor_1_1ExecContext.html)::initiateAcc
execution phase is performed and any memory access is issued (via.
ExecContext::{read,write}Mem calling [LSQ::pushRequest](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html#a18594a4baa4eef7bfc3be45c03f4d544))
-to the [LSQ](https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html).
+http://doxygen.gem5.org/release/current/classMinor_1_1LSQ.html#a18594a4baa4eef7bfc3be45c03f4d544))
+to the [LSQ](http://doxygen.gem5.org/release/current/classMinor_1_1LSQ.html).
Note that faults are issued as if they are instructions and can (currently) be
issued to any functional unit.
@@ -601,13 +601,13 @@
sent from their FU to the LSQ before reaching the head of
Execute::inFlightInsts but after their dependencies are met.
[MinorDynInst::instToWaitFor](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1MinorDynInst.html#ac72a9dcff570bbaf24da9ee74392e6d0)
+http://doxygen.gem5.org/release/current/classMinor_1_1MinorDynInst.html#ac72a9dcff570bbaf24da9ee74392e6d0)
is marked up with the latest dependent instruction execSeqNum required to be
committed for a memory operation to progress to the LSQ.
Once a memory response is available (by testing the head of
Execute::inFlightInsts against [LSQ::findResponse](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html#a458abe5d220a0f66600bf339bceb2100)),
+http://doxygen.gem5.org/release/current/classMinor_1_1LSQ.html#a458abe5d220a0f66600bf339bceb2100)),
commit will process that response (ExecContext::completeAcc) and pop the
instruction from Execute::inFlightInsts.
@@ -624,7 +624,7 @@
#### Scoreboard
The scoreboard ([Scoreboard](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Scoreboard.html)) is used to
+http://doxygen.gem5.org/release/current/classMinor_1_1Scoreboard.html)) is used to
control instruction issue. It contains a count of the number of in flight
instructions which will write each general purpose CPU integer or float
register. Instructions will only be issued where the scoreboard contains a
@@ -641,17 +641,17 @@
#### Execute::inFlightInsts
The Execute::inFlightInsts queue will always contain all instructions in flight
-in [Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) in
+in [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) in
the correct issue order. [Execute::issue](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#af0b90170a273f1a0d41f4164ba3fe456)
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html#af0b90170a273f1a0d41f4164ba3fe456)
is the only process which will push an instruction into the queue.
[Execute::commit](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#ac2da0ae4202602ce4ad976f33a004237)
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html#ac2da0ae4202602ce4ad976f33a004237)
is the only process that can pop an instruction.
#### LSQ
-The [LSQ](https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html) can
+The [LSQ](http://doxygen.gem5.org/release/current/classMinor_1_1LSQ.html) can
support multiple outstanding transactions to memory in a number of conservative
cases.
@@ -666,7 +666,7 @@
unprocessed and progress that queue maintaining order with other transactions.
The conditions in [LSQ::tryToSendToTransfers](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html#a7d7b8ddc7c69fd9eb3b8594fe261d8e8)
+http://doxygen.gem5.org/release/current/classMinor_1_1LSQ.html#a7d7b8ddc7c69fd9eb3b8594fe261d8e8)
dictate when requests can be sent to memory.
All uncacheable transactions, split transactions and locked transactions are
@@ -677,7 +677,7 @@
store buffer.
At the end of transfers, requests which are [LSQ::LSQRequest::Complete](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ_1_1LSQRequest.html#a429d50f5dd6be4217d5dba93f8c289d3a81b9dbf6670e396d0266949d59b57428)
+http://doxygen.gem5.org/release/current/classMinor_1_1LSQ_1_1LSQRequest.html#a429d50f5dd6be4217d5dba93f8c289d3a81b9dbf6670e396d0266949d59b57428)
(are faulting, are cacheable stores, or have been sent to memory and received a
response) can be picked off by Execute and either committed
(ExecContext::completeAcc) and, for stores, be sent to the store buffer.
@@ -691,7 +691,7 @@
change.
After commit, [LSQ::BarrierDataRequest](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ_1_1BarrierDataRequest.html)
+http://doxygen.gem5.org/release/current/classMinor_1_1LSQ_1_1BarrierDataRequest.html)
requests are inserted into the store buffer to track each barrier until all
preceding memory transactions have drained from the store buffer. No further
memory transactions will be issued from the ends of FUs until after the barrier
@@ -700,27 +700,27 @@
#### Draining
Draining is mostly handled by the [Execute](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) stage. When
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) stage. When
initiated by calling [MinorCPU::drain](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a3191c9247cd80dfc603bfcd154cf09a0),
+http://doxygen.gem5.org/release/current/classMinorCPU.html#a3191c9247cd80dfc603bfcd154cf09a0),
[Pipeline::evaluate](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Pipeline.html#af07fdce00c8937e9de5b6450a1cd62bf)
+http://doxygen.gem5.org/release/current/classMinor_1_1Pipeline.html#af07fdce00c8937e9de5b6450a1cd62bf)
checks the draining status of each unit each cycle and keeps the pipeline
active until draining is complete. It is Pipeline that signals the completion
of draining. Execute is triggered by [MinorCPU::drain](
-https://gem5.github.io/gem5-doxygen/classMinorCPU.html#a3191c9247cd80dfc603bfcd154cf09a0)
+http://doxygen.gem5.org/release/current/classMinorCPU.html#a3191c9247cd80dfc603bfcd154cf09a0)
and starts stepping through its [Execute::DrainState](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40)
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40)
state machine, starting from state Execute::NotDraining, in this order:
|State|Meaning|
-|[Execute::NotDraining](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40aeecf47987ef0d4aa0a6a59403d085ec9)|Not trying to drain, normal execution|
-|[Execute::DrainCurrentInst](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40aec53785380b6256e2baa889739311570)|Draining micro-ops to complete inst.|
-|[Execute::DrainHaltFetch](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40a516d421a79c458d376bedeb067fc207f)|Halt fetching instructions|
-|[Execute::DrainAllInsts](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40ade3ca2567fed8d893896d71bb95f13ca)|Discarding all instructions presented|
+|[Execute::NotDraining](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40aeecf47987ef0d4aa0a6a59403d085ec9)|Not trying to drain, normal execution|
+|[Execute::DrainCurrentInst](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40aec53785380b6256e2baa889739311570)|Draining micro-ops to complete inst.|
+|[Execute::DrainHaltFetch](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40a516d421a79c458d376bedeb067fc207f)|Halt fetching instructions|
+|[Execute::DrainAllInsts](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40ade3ca2567fed8d893896d71bb95f13ca)|Discarding all instructions presented|
When complete, a drained Execute unit will be in the [Execute::DrainAllInsts](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40ade3ca2567fed8d893896d71bb95f13ca)
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html#aeb21dbbbbde40d8cdc68e9b17ddd3d40ade3ca2567fed8d893896d71bb95f13ca)
state where it will continue to discard instructions but has no knowledge of
the drained state of the rest of the model.
@@ -733,21 +733,21 @@
|Debug flag | Unit which will generate debugging output |
|:---------------|:------------------------------------------|
-|Activity | [Debug](https://gem5.github.io/gem5-doxygen/namespaceDebug.html) ActivityMonitor actions |
-|Branch | [Fetch2](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) and [Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) branch prediction decisions |
-|[MinorCPU](https://gem5.github.io/gem5-doxygen/classMinorCPU.html) | CPU global actions such as wakeup/thread suspension |
-|[Decode](https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html) | [Decode](https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html) |
-|MinorExec | [Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) behaviour |
-|Fetch |[Fetch1](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) and [Fetch2](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) |
-|MinorInterrupt | [Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) interrupt handling |
-|MinorMem | [Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) memory interactions |
-|MinorScoreboard | [Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) scoreboard activity |
+|Activity | [Debug](http://doxygen.gem5.org/release/current/namespaceDebug.html) ActivityMonitor actions |
+|Branch | [Fetch2](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) and [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) branch prediction decisions |
+|[MinorCPU](http://doxygen.gem5.org/release/current/classMinorCPU.html) | CPU global actions such as wakeup/thread suspension |
+|[Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html) | [Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html) |
+|MinorExec | [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) behaviour |
+|Fetch |[Fetch1](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) and [Fetch2](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) |
+|MinorInterrupt | [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) interrupt handling |
+|MinorMem | [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) memory interactions |
+|MinorScoreboard | [Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) scoreboard activity |
|MinorTrace | Generate MinorTrace cyclic state trace output (see below) |
|MinorTiming | MinorTiming instruction timing modification operations |
-The group flag [Minor](https://gem5.github.io/gem5-doxygen/namespaceMinor.html)
+The group flag [Minor](http://doxygen.gem5.org/release/current/namespaceMinor.html)
enables all the flags beginning with [Minor](
-https://gem5.github.io/gem5-doxygen/namespaceMinor.html).
+http://doxygen.gem5.org/release/current/namespaceMinor.html).
## MinorTrace and minorview.py
@@ -772,7 +772,7 @@
#### MinorInst - summaries of instructions issued by Decode
-[Decode](https://gem5.github.io/gem5-doxygen/classMinor_1_1Decode.html)
+[Decode](http://doxygen.gem5.org/release/current/classMinor_1_1Decode.html)
For example:
@@ -785,7 +785,7 @@
#### MinorLine - summaries of line fetches issued by Fetch1
-[Fetch1](https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html)
+[Fetch1](http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html)
For example:
@@ -838,14 +838,14 @@
used to control the displayed simulation time.
The diagonally striped coloured blocks are showing the [InstId](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html) of the
+http://doxygen.gem5.org/release/current/classMinor_1_1InstId.html) of the
instruction or line they represent. Note that lines in [Fetch1](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) and f1ToF2.F
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) and f1ToF2.F
only show the id fields of a line and that instructions in [Fetch2](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html), f2ToD, and
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html), f2ToD, and
decode.inputBuffer do not yet have execute sequence numbers. The T/S.P/L/F.E
buttons can be used to toggle parts of [InstId](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1InstId.html) on and off to
+http://doxygen.gem5.org/release/current/classMinor_1_1InstId.html) on and off to
make it easier to understand the display. Useful combinations are:
|Combination|Reason |
@@ -899,8 +899,8 @@
their outputs (to the right).
The backwards FIFO between [Fetch2](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) and [Fetch1](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) shows branch
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) and [Fetch1](
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) shows branch
prediction data.
In general, all displayed data is correct at the end of a cycle's activity at
@@ -915,28 +915,28 @@
stage from generating output.
Fetch queues and [LSQ](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1LSQ.html) show the
+http://doxygen.gem5.org/release/current/classMinor_1_1LSQ.html) show the
lines/instructions in the queues of each interface and show the number of
lines/instructions in TLB and memory in the two striped colours of the top of
their frames.
Inside [Execute](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html), the horizontal
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html), the horizontal
bars represent the individual FU pipelines. The vertical bar to the left is the
input buffer and the bar to the right, the instructions committed this cycle.
The background of [Execute](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) shows
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) shows
instructions which are being committed this cycle in their original FU pipeline
positions.
The strip at the top of the [Execute](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) block shows the
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) block shows the
current streamSeqNum that [Execute](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) is committing.
+http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) is committing.
A similar stripe at the top of [Fetch1](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch1.html) shows that
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch1.html) shows that
stage's expected streamSeqNum and the stripe at the top of [Fetch2](
-https://gem5.github.io/gem5-doxygen/classMinor_1_1Fetch2.html) shows its
+http://doxygen.gem5.org/release/current/classMinor_1_1Fetch2.html) shows its
issuing predictionSeqNum.
The scoreboard shows the number of instructions in flight which will commit a
@@ -944,7 +944,7 @@
each integer and floating point register.
The Execute::inFlightInsts queue shows all the instructions in flight in
-[Execute](https://gem5.github.io/gem5-doxygen/classMinor_1_1Execute.html) with
+[Execute](http://doxygen.gem5.org/release/current/classMinor_1_1Execute.html) with
the oldest instruction (the next instruction to be committed) to the right.
`Stage activity` shows the signalled activity (as E/1) for each stage (with CPU
diff --git a/_pages/documentation/general_docs/developement/coding_style.md b/_pages/documentation/general_docs/developement/coding_style.md
index ff608a4..31598ba 100644
--- a/_pages/documentation/general_docs/developement/coding_style.md
+++ b/_pages/documentation/general_docs/developement/coding_style.md
@@ -199,7 +199,7 @@
## Documenting the code
-Each file/class/member should be documented using doxygen style comments.Doxygen allows users to quickly create documentation for our code by extracting the relavent information from the code and comments. It is able to document all the code structures including classes, namespaces, files, members, defines, etc. Most of these are quite simple to document, you only need to place a special documentation block before the declaration. The Doxygen documentation within gem5 is processed every night and the following web pages are generated: [Doxygen](https://gem5.github.io/gem5-doxygen/)
+Each file/class/member should be documented using doxygen style comments.Doxygen allows users to quickly create documentation for our code by extracting the relavent information from the code and comments. It is able to document all the code structures including classes, namespaces, files, members, defines, etc. Most of these are quite simple to document, you only need to place a special documentation block before the declaration. The Doxygen documentation within gem5 is processed every night and the following web pages are generated: [Doxygen](http://doxygen.gem5.org/release/current/index.html)
### Using Doxygen
diff --git a/_pages/documentation/general_docs/memory_system/gem5_memory_system.md b/_pages/documentation/general_docs/memory_system/gem5_memory_system.md
index b7d5799..68c7169 100644
--- a/_pages/documentation/general_docs/memory_system/gem5_memory_system.md
+++ b/_pages/documentation/general_docs/memory_system/gem5_memory_system.md
@@ -33,7 +33,7 @@
## CPU
-Data [Cache](https://gem5.github.io/gem5-doxygen/classCache.html) object
+Data [Cache](http://doxygen.gem5.org/release/current/classcache.html) object
implements a standard cache structure:
@@ -65,13 +65,13 @@
## Data Cache Object
-Data [Cache](https://gem5.github.io/gem5-doxygen/classCache.html) object
+Data [Cache](http://doxygen.gem5.org/release/current/classCache.html) object
implements a standard cache structure:
**Cached memory reads** that match particular cache tag (with Valid & Read
flags) will be completed (by sending ReadResp to CPU) after a configurable
time. Otherwise, the request is forwarded to Miss Status and Handling Register
-([MSHR](https://gem5.github.io/gem5-doxygen/classMSHR.html)) block.
+([MSHR](http://doxygen.gem5.org/release/current/classMSHR.html)) block.
**Cached memory writes** that match particular cache tag (with Valid, Read &
Write flags) will be completed (by sending WriteResp CPU) after the same
@@ -79,36 +79,36 @@
Handling Register(MSHR) block.
**Uncached memory reads** are forwarded to [MSHR](
-https://gem5.github.io/gem5-doxygen/classMSHR.html) block.
+http://doxygen.gem5.org/release/current/classMSHR.html) block.
**Uncached memory writes** are forwarded to WriteBuffer block.
**Evicted (& dirty) cache lines** are forwarded to WriteBuffer block.
CPU’s access to Data [Cache](
-https://gem5.github.io/gem5-doxygen/classCache.html) is blocked if any of the
+http://doxygen.gem5.org/release/current/classCache.html) is blocked if any of the
following is true:
-* [MSHR](https://gem5.github.io/gem5-doxygen/classMSHR.html) block is full.
+* [MSHR](http://doxygen.gem5.org/release/current/classMSHR.html) block is full.
(The size of MSHR’s buffer is configurable.)
* Writeback block is full. (The size of the block’s buffer is configurable.)
* The number of outstanding memory accesses against the same memory cache line
has reached configurable threshold value – see [MSHR](
-https://gem5.github.io/gem5-doxygen/classMSHR.html) and Write Buffer for
+http://doxygen.gem5.org/release/current/classMSHR.html) and Write Buffer for
details.
-Data [Cache](https://gem5.github.io/gem5-doxygen/classCache.html) in block
+Data [Cache](http://doxygen.gem5.org/release/current/classCache.html) in block
state will reject any request from slave port (from CPU) regardless of whether
it would result in cache hit or miss. Note that incoming messages on master
port (response messages and snoop requests) are never rejected.
-[Cache](https://gem5.github.io/gem5-doxygen/classCache.html) hit on uncachable
+[Cache](http://doxygen.gem5.org/release/current/classCache.html) hit on uncachable
memory region (unpredicted behaviour according to ARM ARM) will invalidate
cache line and fetch data from memory.
### Tags & Data Block
-[Cache](https://gem5.github.io/gem5-doxygen/classCache.html) lines (referred as
+[Cache](http://doxygen.gem5.org/release/current/classCache.html) lines (referred as
blocks in source code) are organised into sets with configurable associativity
and size. They have the following status flags:
@@ -127,7 +127,7 @@
### MSHR and Write Buffer Queues
Miss Status and Handling Register ([MSHR](
-https://gem5.github.io/gem5-doxygen/classMSHR.html)) queue holds the list of
+http://doxygen.gem5.org/release/current/classMSHR.html)) queue holds the list of
CPU’s outstanding memory requests that require read access to lower memory
level. They are:
@@ -143,11 +143,11 @@
Each memory request is assigned to corresponding [MSHR](
-https://gem5.github.io/gem5-doxygen/classMSHR.html) object (READ or WRITE on
+http://doxygen.gem5.org/release/current/classMSHR.html) object (READ or WRITE on
diagram above) that represents particular block (cache line) of memory that has
to be read or written in order to complete the command(s). As shown on gigure
above, cached read/writes against the same cache line have a common [MSHR](
-https://gem5.github.io/gem5-doxygen/classMSHR.html) object and will be
+http://doxygen.gem5.org/release/current/classMSHR.html) object and will be
completed with a single memory access.
The size of the block (and therefore the size of read/write access to lower
@@ -156,7 +156,7 @@
* The size of cache line for cached access & writeback;
* As specified in CPU instruction for uncached access.
-In general, Data [Cache](https://gem5.github.io/gem5-doxygen/classCache.html)
+In general, Data [Cache](http://doxygen.gem5.org/release/current/classCache.html)
model distinguishes between just two memory types:
* Normal Cached memory. It is always treated as write back, read and write
@@ -168,13 +168,13 @@
An unique order number is assigned to each CPU read/write request(as they
appear on slave port). Order numbers of [MSHR](
-https://gem5.github.io/gem5-doxygen/classMSHR.html) objects are copied from the
+http://doxygen.gem5.org/release/current/classMSHR.html) objects are copied from the
first assigned read/write.
Memory read/writes from each of these two queues are executed in order
(according to the assigned order number). When both queues are not empty the
model will execute memory read from [MSHR](
-https://gem5.github.io/gem5-doxygen/classMSHR.html) block unless WriteBuffer is
+http://doxygen.gem5.org/release/current/classMSHR.html) block unless WriteBuffer is
full. It will, however, always preserve the order of read/writes on the same
(or overlapping) memory cache line (block).
diff --git a/_pages/documentation/general_docs/thermal_model.md b/_pages/documentation/general_docs/thermal_model.md
index 1ff3759..4de1e76 100644
--- a/_pages/documentation/general_docs/thermal_model.md
+++ b/_pages/documentation/general_docs/thermal_model.md
@@ -18,49 +18,49 @@
Classes involved in the power model are:
-* [PowerModel](https://gem5.github.io/gem5-doxygen/classPowerModel.html):
+* [PowerModel](http://doxygen.gem5.org/release/current/classPowerModel.html):
Represents a power model for a hardware component.
* [PowerModelState](
-https://gem5.github.io/gem5-doxygen/classPowerModelState.html): Represents a
+http://doxygen.gem5.org/release/current/classPowerModelState.html): Represents a
power model for a hardware component in a certain power state. It is an
abstract class that defines an interface that must be implemented for each
model.
* [MathExprPowerModel](
-https://gem5.github.io/gem5-doxygen/classMathExprPowerModel.html): Simple
+http://doxygen.gem5.org/release/current/classMathExprPowerModel.html): Simple
implementation of [PowerModelState](
-https://gem5.github.io/gem5-doxygen/classPowerModelState.html) that assumes
+http://doxygen.gem5.org/release/current/classPowerModelState.html) that assumes
that power can be modeled using a simple power.
Classes involved in the thermal model are:
-* [ThermalModel](https://gem5.github.io/gem5-doxygen/classThermalModel.html):
+* [ThermalModel](http://doxygen.gem5.org/release/current/classThermalModel.html):
Contains the system thermal model logic and state. It performs the power query
and temperature update. It also enables gem5 to query for temperature (for OS
reporting).
-* [ThermalDomain](https://gem5.github.io/gem5-doxygen/classThermalDomain.html):
+* [ThermalDomain](http://doxygen.gem5.org/release/current/classThermalDomain.html):
Represents an entity that generates heat. It's essentially a group of
-[SimObjects](https://gem5.github.io/gem5-doxygen/classSubSystem.html) grouped
+[SimObjects](http://doxygen.gem5.org/release/current/classSubSystem.html) grouped
under a SubSystem component that have its own thermal behaviour.
-* [ThermalNode](https://gem5.github.io/gem5-doxygen/classThermalNode.html):
+* [ThermalNode](http://doxygen.gem5.org/release/current/classThermalNode.html):
Represents a node in the thermal circuital equivalent. The node has a
temperature and interacts with other nodes through connections (thermal
resistors and capacitors).
* [ThermalReference](
-https://gem5.github.io/gem5-doxygen/classThermalReference.html): Temperature
+http://doxygen.gem5.org/release/current/classThermalReference.html): Temperature
reference for the thermal model (essentially a thermal node with a fixed
temperature), can be used to model air or any other constant temperature
domains.
-* [ThermalEntity](https://gem5.github.io/gem5-doxygen/classThermalEntity.html):
+* [ThermalEntity](http://doxygen.gem5.org/release/current/classThermalEntity.html):
A thermal component that connects two thermal nodes and models a thermal
impedance between them. This class is just an abstract interface.
* [ThermalResistor](
-https://gem5.github.io/gem5-doxygen/classThermalResistor.html): Implements
-[ThermalEntity](https://gem5.github.io/gem5-doxygen/classThermalEntity.html) to
+http://doxygen.gem5.org/release/current/classThermalResistor.html): Implements
+[ThermalEntity](http://doxygen.gem5.org/release/current/classThermalEntity.html) to
model a thermal resistance between the two nodes it connects. Thermal
resistances model the capacity of a material to transfer heat (units in K/W).
* [ThermalCapacitor](
-https://gem5.github.io/gem5-doxygen/classThermalCapacitor.html): Implements
-[ThermalEntity](https://gem5.github.io/gem5-doxygen/classThermalEntity.html) to
+http://doxygen.gem5.org/release/current/classThermalCapacitor.html): Implements
+[ThermalEntity](http://doxygen.gem5.org/release/current/classThermalEntity.html) to
model a thermal capacitance. Thermal capacitors are used to model material's
thermal capacitance, this is, the ability to change a certain material
temperature (units in J/K).
@@ -78,7 +78,7 @@
entities (capacitors and resistors).
Last step to conclude the thermal model is to create the [ThermalModel](
-https://gem5.github.io/gem5-doxygen/classThermalModel.html) instance itself and
+http://doxygen.gem5.org/release/current/classThermalModel.html) instance itself and
attach all the instances used to it, so it can properly update them at runtime.
Only one thermal model instance is supported right now and it will
automatically report temperature when appropriate (ie. platform sensor
@@ -87,7 +87,7 @@
## Power model
Every [ClockedObject](
-https://gem5.github.io/gem5-doxygen/classClockedObject.html) has a power model
+http://doxygen.gem5.org/release/current/classClockedObject.html) has a power model
associated. If this power model is non-null power will be calculated at every
stats dump (although it might be possible to force power evaluation at any
other point, if the power model uses the stats, it is a good idea to keep both
@@ -100,7 +100,7 @@
A power state model is essentially an interface that allows us to define two
power functions for dynamic and static. As an example implementation a class
called [MathExprPowerModel](
-https://gem5.github.io/gem5-doxygen/classMathExprPowerModel.html) has been
+http://doxygen.gem5.org/release/current/classMathExprPowerModel.html) has been
provided. This implementation allows the user to define a power model as an
equation involving several statistics. There's also some automatic (or "magic")
variables such as "temp", which reports temperature.
diff --git a/_pages/documentation/index.md b/_pages/documentation/index.md
index 585e2d5..b0da1c4 100644
--- a/_pages/documentation/index.md
+++ b/_pages/documentation/index.md
@@ -32,7 +32,7 @@
## gem5 API documentation
-You can find the doxygen-based documentation here: <https://gem5.github.io/gem5-doxygen/>
+You can find the doxygen-based documentation here: <http://doxygen.gem5.org/release/current/index.html>
## Other general gem5 documentation
