website: fix links and markup of publications (2012)
Signed-off-by: Masanori Ogino <masanori.ogino@gmail.com>
Change-Id: Iaee80a918574c63c24762cf567b03d1746825434
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-website/+/56064
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby Bruce <bbruce@ucdavis.edu>
diff --git a/_pages/publications.md b/_pages/publications.md
index d5ce809..0f159dc 100644
--- a/_pages/publications.md
+++ b/_pages/publications.md
@@ -195,12 +195,12 @@
## 2012<span class="anchor" data-clipboard-text="http://www.gem5.org/publications/#2012"></span>
-* _Hardware Prefetchers for Emerging Parallel Applications_, Biswabandan Panda, Shankar Balachandran. In the proceedings of the IEEE/ACM Parallel Architectures and Compilation Techniques,PACT, Minneapolis, October 2012.
-* [**Lazy Cache Invalidation for Self-Modifying Codes**](https://doi.org/10.1145/2380403.2380433). A. Gutierrez, J. Pusdesris, R.G. Dreslinski, and T. Mudge. In the proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Tampere, Finland, October 2012.
-* _Accuracy Evaluation of GEM5 Simulator System_. A. Butko, R. Garibotti, L. Ost, and G. Sassatelli. In the proceeding of the IEEE International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, United Kingdom, July 2012.
-* _Viper: Virtual Pipelines for Enhanced Reliability_. A. Pellegrini, J. L. Greathouse, and V. Bertacco. In the proceedings of the International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.
-* [**Reducing memory reference energy with opportunistic virtual caching**](http://dx.doi.org/10.1109/ISCA.2012.6237026). Arkaprava Basu, Mark D. Hill, Michael M. Swift. In the proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012).
-* [**Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs**](http://www.cse.psu.edu/~axj936/docs/Revive-DAC-2012.pdf). Adwait Jog, Asit Mishra, Cong Xu, Yuan Xie, V. Narayanan, Ravi Iyer, Chita Das. In the proceedings oF the IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, June 2012.
+* [**Hardware Prefetchers for Emerging Parallel Applications**](https://dl.acm.org/doi/10.1145/2370816.2370909). Biswabandan Panda, Shankar Balachandran. In the proceedings of the IEEE/ACM Parallel Architectures and Compilation Techniques,PACT, Minneapolis, October 2012. doi:[10.1145/2370816.2370909](https://dx.doi.org/10.1145/2370816.2370909).
+* [**Lazy Cache Invalidation for Self-Modifying Codes**](https://dl.acm.org/doi/10.1145/2380403.2380433). A. Gutierrez, J. Pusdesris, R.G. Dreslinski, and T. Mudge. In the proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Tampere, Finland, October 2012. doi:[10.1145/2380403.2380433](https://dx.doi.org/10.1145/2380403.2380433).
+* [**Accuracy Evaluation of GEM5 Simulator System**](https://ieeexplore.ieee.org/document/6322869). A. Butko, R. Garibotti, L. Ost, and G. Sassatelli. In the proceeding of the IEEE International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, United Kingdom, July 2012. doi:[10.1109/ReCoSoC.2012.6322869](https://dx.doi.org/10.1109/ReCoSoC.2012.6322869).
+* [**Viper: Virtual Pipelines for Enhanced Reliability**](https://ieeexplore.ieee.org/document/6237030). A. Pellegrini, J. L. Greathouse, and V. Bertacco. In the proceedings of the International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012. doi:[10.1109/ISCA.2012.6237030](https://dx.doi.org/10.1109/ISCA.2012.6237030).
+* [**Reducing memory reference energy with opportunistic virtual caching**](https://ieeexplore.ieee.org/document/6237026). Arkaprava Basu, Mark D. Hill, Michael M. Swift. In the proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012). doi:[10.1109/ISCA.2012.6237026](https://dx.doi.org/10.1109/ISCA.2012.6237026).
+* [**Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs**](https://dl.acm.org/doi/10.1145/2228360.2228406). Adwait Jog, Asit Mishra, Cong Xu, Yuan Xie, V. Narayanan, Ravi Iyer, Chita Das. In the proceedings of the IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, June 2012. doi:[10.1145/2228360.2228406](https://dx.doi.org/10.1145/2228360.2228406). [pdf](http://www.cse.psu.edu/hpcl/docs/2012_DAC_Adwait.pdf)
## 2011<span class="anchor" data-clipboard-text="http://www.gem5.org/publications/#2011"></span>
